A power semiconductor module substrate

Abstract

The present invention provides a power semiconductor module substrate, comprising a main power substrate, on which a plurality of auxiliary power substrates are arranged; the main power substrate is provided with a plurality of main metal claddings and a plurality of secondary metal claddings, and the plurality of auxiliary power substrates are arranged on one or more of the plurality of secondary metal claddings; the main metal cladding is arranged in the middle of the main power substrate, and a chip is arranged on the main metal cladding; the auxiliary power substrate is arranged on the side of the main power substrate, and a signal terminal is arranged on the auxiliary power substrate; the chip on the main power substrate is connected to the signal terminal on the auxiliary power substrate away from the main power substrate for source and gate connection; the chip on the main power substrate is connected to the adjacent main metal cladding or secondary metal cladding by bonding wires, and the bonding wires are oblique lines, and the closer the bonding wires are to the connected auxiliary power substrates, the greater the inclination of the bonding wires.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a power semiconductor module substrate. Background Art

[0002] As the overall size of new energy vehicle motor controllers continues to develop in the direction of miniaturization and high density, the demand for compact module design is increasing. How to balance the junction temperature distribution of each chip while reducing the overall substrate size of the module, reduce the high-frequency oscillation of voltage and current stimulated by parasitic parameters, and thus ensure the efficient operation and long-term reliability of the power module has become a difficult problem in substrate layout design.

[0003] In order to solve the electrical and heat dissipation problems of automotive-grade power modules, electronic control manufacturers tend to increase the RC time constant of the absorption circuit in the driver board to suppress voltage and current overshoot and oscillation, or optimize the relevant structural design of the cooling system. This is bound to increase the overall cost of the system, reduce the operating efficiency of the electronic control, and lose the relevant competitive advantages of some products.

[0004] Existing power module substrate designs are mostly qualitative analyses, the reliability influencing mechanism is unclear, and the verification cycle is long. Summary of the invention

[0005] In order to overcome the above technical defects, an object of the present invention is to provide a power semiconductor module substrate with small volume and module-balanced flow.

[0006] The present invention discloses a power semiconductor module substrate, comprising a main power substrate, on which a plurality of auxiliary power substrates are arranged; the main power substrate is provided with a plurality of main metal claddings and a plurality of secondary metal claddings, and the plurality of auxiliary power substrates are arranged on one or more of the plurality of secondary metal claddings; the main metal cladding is arranged in the middle of the main power substrate, and a chip is arranged on the main metal cladding; the auxiliary power substrate is arranged on the side of the main power substrate, and a signal terminal is arranged on the auxiliary power substrate; the chip on the main power substrate is connected to the signal terminal on the auxiliary power substrate away from the main power substrate for source and gate connection; the chip on the main power substrate is connected to the adjacent main metal cladding or secondary metal cladding through bonding wires, and the bonding wires are oblique lines, and the closer the bonding wires are to the connected auxiliary power substrates, the greater the inclination of the bonding wires.

[0007] Preferably, a first main metal cladding and a second main metal cladding are provided on the main power substrate, and the first main metal cladding is embedded in the second main metal cladding in a first direction, so that a first part of the second main metal cladding is provided on both sides of the first main metal cladding, and a second part is provided at one end of the first main metal cladding along the first direction; a plurality of chips are arranged on the first main metal cladding and the second part of the second main metal cladding; the chip on the first main metal cladding is connected to the first part on the adjacent second main metal cladding through bonding wires.

[0008] Preferably, secondary metal coatings are provided on both sides of the combined coating formed by the first main metal coating and the second main metal coating; and the plurality of auxiliary power substrates are respectively provided on the secondary metal coatings on both sides.

[0009] Preferably, the plurality of auxiliary power substrates include a first auxiliary power substrate and a second auxiliary power substrate, and the first auxiliary power substrate and the second auxiliary power substrate are respectively arranged along diagonals of the main power substrate.

[0010] Preferably, a plurality of connecting metal claddings are provided on the main power substrate, and the connecting metal claddings are arranged between a plurality of chips and connected to the gate-level circuits of the chips; the connecting metal claddings are also connected to the signal terminals on the auxiliary power substrate, so that the chips are connected to the signal terminals on the auxiliary power substrate.

[0011] Preferably, the connecting metal cladding includes a first connecting metal cladding group and a second connecting metal cladding group; a portion of the first connecting metal cladding group is embedded in the first main metal cladding in the first direction to connect to the chip on the first main metal cladding, and a portion of the second connecting metal cladding group is embedded in the second main metal cladding in the first direction to connect to the chip on the second main metal cladding; the first connecting metal cladding group and the second connecting metal cladding group include two connecting metal claddings.

[0012] Preferably, the temperature sensor is connected to the first auxiliary power substrate or the second auxiliary power substrate.

[0013] Preferably, a lower cladding layer is provided between the first auxiliary power substrate and the main power substrate, between the second auxiliary power substrate and the main power substrate, and at the bottom of the main power substrate.

[0014] Compared with the prior art, the above technical solution has the following beneficial effects:

[0015] 1. The auxiliary power substrate is used to receive the wiring of the signal terminals of the module, avoiding the use of the signal terminal lead frame, reducing the longitudinal size of the module, making the module more compact and smaller in size, and helping to achieve high power density and miniaturization design of the converter;

[0016] 2. By connecting the chip on the main power substrate to the signal terminal on the auxiliary power substrate far away from the main power substrate through source and gate connection, the chip source and gate signal routing is lengthened, the imbalance of the stray inductance of the gate-level loop of each chip is reduced, and a better module current sharing design is achieved;

[0017] 3. By making the bonding wire an oblique line, and the closer the bonding wire is to the connected auxiliary power substrate, the greater the inclination is, the imbalance of the source stray inductance caused by the asymmetry of the chip substrates is compensated, and a better module current sharing design is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic structural diagram of a preferred embodiment of a power semiconductor module substrate provided by the present invention;

[0019] Figure 2 A schematic structural diagram of the main power substrate of the power semiconductor module substrate provided by the present invention;

[0020] Figure 3 A schematic structural diagram of the first auxiliary power substrate of the power semiconductor module substrate provided by the present invention;

[0021] Figure 4 A schematic structural diagram of the second auxiliary power substrate of the power semiconductor module substrate provided by the present invention;

[0022] Figure 5 A side view of a power semiconductor module substrate provided by the present invention;

[0023] Figure 6 The stray inductance of each chip commutation loop of a preferred embodiment of the power semiconductor module substrate provided by the present invention;

[0024] Figure 7 The simulation results of stray inductance of each chip driving circuit of a preferred embodiment of the power semiconductor module substrate provided by the present invention;

[0025] Figure 8 The simulation result of the source stray inductance of each chip of a preferred embodiment of the power semiconductor module substrate provided by the present invention;

[0026] Fig. 9A source current waveform of the upper bridge SiC MOSFET during the turn-on and turn-off process of a preferred embodiment of the power semiconductor module substrate provided by the present invention;

[0027] Fig.10 The source current waveform of the lower bridge SiCMOSFET during the turn-on and turn-off process of a preferred embodiment of the power semiconductor module substrate provided by the present invention.

[0028] Among them: 1-first main metal coating, 2-second main metal coating, 3-secondary metal coating, 4-first connecting metal coating group, 5-second connecting metal coating group, 6-insulating layer, 7-auxiliary metal coating, 8-auxiliary metal coating for connecting temperature sensor, 9-signal terminal, 10-signal terminal for connecting temperature sensor, 11-chip, 12-temperature sensor, 13-lower coating. DETAILED DESCRIPTION

[0029] The advantages of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments.

[0030] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0031] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0032] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0033] In the description of the present invention, it is necessary to understand that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal connection between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0035] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings. Therefore, "module" and "component" can be used interchangeably.

[0036] See attached Figure 1-2 The present invention discloses a power semiconductor module substrate, including a main power substrate and a plurality of auxiliary power substrates. The plurality of auxiliary power substrates are arranged on the main power substrate to undertake the routing of the signal terminal 9 of the module, avoid the use of the lead frame of the signal terminal 9, reduce the longitudinal size of the module, and make the module more compact as a whole.

[0037] Specifically, the main power substrate is provided with a plurality of main metal cladding layers and a plurality of secondary metal cladding layers 3. A preferred understanding (but not limited thereto) is that the main metal cladding layers are used to arrange the chip 11, while the secondary metal cladding layers 3 are used to arrange the wiring or other power devices. In particular, a plurality of auxiliary power substrates are provided on one or more of the plurality of secondary metal cladding layers 3.

[0038] The main metal cladding is arranged in the middle of the main power substrate, and the chip 11 is arranged on the main metal cladding. The secondary metal cladding 3 is arranged on the side of the main power substrate, and the auxiliary power substrate is arranged on the secondary metal cladding 3, so that the auxiliary power substrate is arranged on the side of the main power substrate, and the signal terminal 9 is arranged on the auxiliary power substrate.

[0039] The chip 11 on the main metal coating is connected to the signal terminal 9 on the auxiliary power substrate through routing. Specifically, the chip 11 on the main power substrate is connected to the signal terminal 9 on the auxiliary power substrate away from the main power substrate for source and gate connection, which lengthens the source and gate signal routing of the chip 11, reduces the imbalance of the stray inductance of the gate-level loop of each chip 11, and realizes a better module current sharing design.

[0040] The chip 11 on the main power substrate is also connected to the adjacent main metal coating or secondary metal coating 3 through bonding wires. The bonding wires are oblique lines, and the closer to the connected auxiliary power substrate, the greater the slope of the bonding wire, so that the routing is longer, compensating for the imbalance of source stray inductance caused by the asymmetry of the substrates of each chip 11, and achieving a better module current sharing design.

[0041] The present invention solves the problem of uneven distribution of thermal stress in the module from the source, suppresses abnormal oscillations excited by the feedback loop between the parallel chips 11, and can provide more margin for the electronic control design. Each chip 11 can achieve excellent dynamic and static current sharing characteristics and has lower losses, which helps to achieve high-reliability design of the module and efficient operation of the converter.

[0042] The present invention provides a preferred embodiment, in which a first main metal cladding 1 and a second main metal cladding 2 are provided on the main power substrate, and the first main metal cladding 1 is embedded in the second main metal cladding 2 in the first direction, so that the first part of the second main metal cladding 2 is provided on both sides of the first main metal cladding 1, and the second part is provided at one end of the first main metal cladding 1 along the first direction. The first direction in the description of the present invention represents the longitudinal direction, and can also be understood as the up and down direction, so the first main metal cladding 1 is provided below the second main metal cladding 2.

[0043] A plurality of chips 11 are arranged on the second parts of the first main metallization layer 1 and the second main metallization layer 2. The chips 11 on the first main metallization layer 1 are connected to the first part on the adjacent second main metallization layer 2 through bonding wires.

[0044] Sub-metal claddings 3 are provided on both sides of the combined cladding formed by the first main metal cladding 1 and the second main metal cladding 2. The auxiliary power substrate comprises a first auxiliary power substrate and a second auxiliary power substrate, which are respectively provided on the sub-metal claddings 3 on both sides, and the first auxiliary power substrate and the second auxiliary power substrate are respectively arranged along the diagonal of the main power substrate.

[0045] In this embodiment, the first auxiliary power substrate is disposed at the upper left corner, and the second auxiliary power substrate is disposed at the lower right corner.

[0046] In other embodiments, if the first auxiliary power substrate is disposed at the lower left corner, the second auxiliary power substrate is disposed at the upper right corner.

[0047] In this embodiment, the chip 11 on the first main metal cladding 1 located at the lower part of the first direction is connected to the signal terminal 9 on the first auxiliary power substrate located at the upper part of the first direction, and the chip 11 on the second main metal cladding 2 located at the upper part of the first direction is connected to the signal terminal 9 on the second auxiliary power substrate located at the lower part of the first direction, so as to lengthen the source and gate signal lines of the chip 11.

[0048] The chip 11 on the first main metal cladding 1 is connected to the first part on the adjacent second main metal cladding 2 through a bonding wire, and the closer to the connected first auxiliary power substrate, the greater the slope of the bonding wire, so that the routing is farther, so that the routing distance from several chips 11 to the first auxiliary power substrate is closer, making the stray inductance more balanced.

[0049] Similarly, the chip 11 on the second main metal coating 2 is connected to the adjacent secondary metal coating 3 through bonding wires. The closer to the connected second auxiliary power substrate, the greater the slope of the bonding wire, and thus the longer the routing, so that the routing distances from several chips 11 to the second auxiliary power substrate are closer, making the stray inductance more balanced.

[0050] Specifically, a plurality of connecting metal coatings are provided on the main power substrate. The connecting metal coatings are provided between a plurality of chips 11 and connected to the gate-level circuit of the chip 11. The connecting metal coatings are also connected to the signal terminal 9 on the auxiliary power substrate, thereby connecting the chip 11 to the signal terminal 9 on the auxiliary power substrate.

[0051] The connection metal cladding layer includes a first connection metal cladding layer group 4 and a second connection metal cladding layer group. A portion of the first connection metal cladding layer group 4 is embedded in the first main metal cladding layer 1 in the first direction to connect with the chip 11 on the first main metal cladding layer 1, and another portion extends along a second direction perpendicular to the first direction to connect with the first auxiliary power substrate. A portion of the second connection metal cladding layer group 5 is embedded in the second main metal cladding layer 2 in the first direction to connect with the chip 11 on the second main metal cladding layer 2, and another portion extends along a second direction perpendicular to the first direction to connect with the second auxiliary power substrate.

[0052] The first connection metallization group 4 and the second connection metallization group each include two connection metallizations.

[0053] Preferably, the temperature sensor 12 is connected to the first auxiliary power substrate or the second auxiliary power substrate.

[0054] In the preferred embodiment provided by the present invention, see the attached Figure 3The first auxiliary power substrate includes four auxiliary metal cladding layers 7 for connecting the chip 11 and one auxiliary metal cladding layer 87 for connecting the temperature sensor 12. The metal cladding layer is provided with a signal terminal 910 for connecting the temperature sensor 12. Figure 4 The second auxiliary power substrate includes three auxiliary metal cladding layers 7 for connecting the chip 11 .

[0055] An insulating layer 6 is provided between the main power substrate, the first auxiliary power substrate, and the second auxiliary power substrate.

[0056] See attached Figure 5 A lower cladding layer 13 is provided between the first auxiliary power substrate and the main power substrate, between the second auxiliary power substrate and the main power substrate, and at the bottom of the main power substrate.

[0057] The power semiconductor module designed with the power semiconductor module substrate of the present invention can reduce the volume by about 20% compared with the same type of products with similar power levels, and has excellent current and temperature balancing characteristics, thereby facilitating the miniaturization design of the motor controller. An example of the use effect of the power semiconductor module substrate of the present invention is provided below.

[0058] Take SiC MOSFET power semiconductor module as an example.

[0059] Figure 6 The electromagnetic simulation results of the stray inductance of the commutation circuit of each chip 11 of the substrate of the present invention are shown. Due to the packaging design of the oblique binding wire, the mismatch of the stray inductance caused by the difference in the copper layer path of the substrate is avoided. The balance of the stray inductance of each circuit is very high. The unbalance of the stray inductance between the chips 11 of the upper bridge is only 2.4%, and that of the lower bridge is 2.9%. The extremely high balance of the stray inductance of the commutation circuit avoids the high-frequency oscillation of the current in the reverse recovery process of the SiC body diode between the chips 11. At the same time, the total commutation circuit stray inductance of about 6nH can improve the voltage stress of the module and ensure that the module has a high operating efficiency.

[0060] Figure 7 The simulation results of the stray inductance of the drive circuit of each chip 11 of the substrate of the present invention are shown in Figure 1. Due to the use of an auxiliary substrate design to lengthen the drive circuit path, the mismatch of the drive circuit stray inductance of about 10nH between each bridge arm chip 11 is weakened, the upper bridge mismatch is 5.1%, and the lower bridge mismatch is 5.2%. Since the switching speed of the power module can be adjusted by the driving resistor, increasing the total stray inductance of the driving circuit has little effect on the switching speed of the module, and it can be considered that the module still has a faster switching speed and lower switching loss.

[0061] Figure 8This is the simulation result of the source stray inductance of each chip 11 on the substrate of the present invention. The oblique binding wires also achieve a uniform design of the source stray inductance between each bridge arm. The mismatch of the source stray inductance of the upper bridge is 8.5%, and that of the lower bridge is 3.4%. The matching degree of the stray inductance is an important influencing factor of the dynamic current sharing during the switching process of the SiC MOSFET. The simulation results show that the switching process of each chip 11 on the upper and lower bridges has a high consistency, and the switching losses generated are also similar, which is conducive to the uniform distribution of the junction temperature of each chip 11.

[0062] Based on the above electromagnetic simulation results, the self-inductance-mutual inductance matrix of each chip 11 is extracted and imported into the circuit simulation software for switching transient simulation analysis. The bus voltage is 800V and the total current is 600A. Fig. 9 is the source current waveform of the upper bridge SiC MOSFET during the turn-on and turn-off process. Fig.10 The source current waveform of the lower bridge SiC MOSFET during the turn-on and turn-off process, the left is the turn-on waveform, and the right is the turn-off waveform. It can be seen that the chips 11 of the upper and lower bridge arms have extremely high current consistency, and the current imbalance is less than 7%, which can significantly reduce the risk of abnormal gate-level oscillation caused by inconsistent module current sharing, balance the switching losses between the chips 11, and improve the uniformity of the junction temperature between the chips 11.

[0063] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A power semiconductor module substrate, characterized in that: It comprises a main power substrate, on which a plurality of auxiliary power substrates are arranged; The main power substrate is provided with a plurality of main metal coatings and a plurality of secondary metal coatings, and the plurality of auxiliary power substrates are provided on one or more of the plurality of secondary metal coatings; The main metal cladding is arranged in the middle of the main power substrate, and a chip is arranged on the main metal cladding; the auxiliary power substrate is arranged on the side of the main power substrate, and a signal terminal is arranged on the auxiliary power substrate; the chip on the main power substrate is connected to the signal terminal on the auxiliary power substrate away from the main power substrate for source and gate connection; The chip on the main power substrate is connected to the adjacent main metal cladding or secondary metal cladding via bonding wires. The bonding wires are oblique lines, and the closer the bonding wires are to the connected auxiliary power substrate, the greater the inclination of the bonding wires.

2. The power semiconductor module substrate according to claim 1, characterized in that The main power substrate is provided with a first main metal cladding and a second main metal cladding, the first main metal cladding is embedded in the second main metal cladding in a first direction, so that a first part of the second main metal cladding is provided on both sides of the first main metal cladding, and a second part is provided at one end of the first main metal cladding along the first direction; A plurality of chips are arranged on the first main metal cladding layer and the second part of the second main metal cladding layer; the chip on the first main metal cladding layer is connected to the first part on the adjacent second main metal cladding layer through bonding wires.

3. The power semiconductor module substrate according to claim 2, characterized in that: Sub-metal coatings are provided on both sides of the combined coating formed by the first main metal coating and the second main metal coating; The plurality of auxiliary power substrates are respectively arranged on the secondary metal cladding layers at both sides.

4. The power semiconductor module substrate according to claim 3, characterized in that: The plurality of auxiliary power substrates include a first auxiliary power substrate and a second auxiliary power substrate, and the first auxiliary power substrate and the second auxiliary power substrate are respectively arranged along diagonals of the main power substrate.

5. The power semiconductor module substrate according to claim 4, characterized in that: The main power substrate is provided with a plurality of connection metal cladding layers, and the connection metal cladding layers are provided between a plurality of chips and connected to the gate-level circuits of the chips; The connection metal cladding is also connected to the signal terminal on the auxiliary power substrate, so that the chip is connected to the signal terminal on the auxiliary power substrate.

6. The power semiconductor module substrate according to claim 5, characterized in that The connection metal cladding layer includes a first connection metal cladding layer group and a second connection metal cladding layer group; a portion of the first connection metal cladding layer group is embedded in the first main metal cladding layer in a first direction to connect with the chip on the first main metal cladding layer, and a portion of the second connection metal cladding layer group is embedded in the second main metal cladding layer in a first direction to connect with the chip on the second main metal cladding layer; The first connection metallization group and the second connection metallization group include two connection metallizations.

7. The power semiconductor module substrate according to claim 6, characterized in that: The temperature sensor is connected to the first auxiliary power substrate or the second auxiliary power substrate.

8. The power semiconductor module substrate according to claim 4, characterized in that: A lower cladding layer is provided between the first auxiliary power substrate and the main power substrate, between the second auxiliary power substrate and the main power substrate, and at the bottom of the main power substrate.

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