A device and method for converting BMS-AFE low-side drive to high-side drive

Abstract

The present invention discloses a device and method for converting a BMS-AFE low-side drive to a high-side drive. The device includes a self-locking low-power conduction speed adjustable circuit module, a self-locking low-power turn-off speed adjustable circuit module, and a controlled PMONS transistor Q3. The self-locking low-power conduction speed adjustable circuit module and the self-locking low-power turn-off speed adjustable circuit module act on the controlled PMONS transistor Q3 simultaneously. The existing DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port are respectively connected to the self-locking low-power conduction speed adjustable circuit module and the self-locking low-power turn-off speed adjustable circuit module. The present invention can select appropriate conduction drive speed and turn-off drive speed according to the actual application scenario. Moreover, the drive circuit itself has no additional power consumption, meeting the requirements of low-power application scenarios.

Description

Technical Field

[0001] The present invention relates to the field of BMS-AFE driving, and particularly to a driving device and method for converting a BMS-AFE low-side drive to a high-side drive. Background Art

[0002] A BMS (Battery Management System) is a system specifically developed for managing secondary batteries. It is not only used in automobiles but also applied in many fields using secondary batteries.

[0003] In existing rechargeable battery pack BMSs, AFE chips using a low-side drive scheme cannot be directly applied to high-side drive scenarios. If an existing AFE low-side drive scheme is needed to achieve high-side drive, a conversion circuit is required, such as Figure 1 shown: In the prior art, a driving conversion IC (such as TIBQ76200) for converting a low-side to a high-side drive of an NMOS with a charge pump is widely used. However, in application scenarios with relatively small currents, such as several amperes, the price difference between PMOS and NMOS of the same specification is already comparable to or even higher than the price of the charge pump driving conversion IC for converting a low-side to a high-side drive. Moreover, the charge pump circuit for driving the high-side NMOS itself consumes additional power. Therefore, in this scenario, converting a low-side to a high-side drive of a PMOS is more economical and practical. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a driving device and method for converting a low-side drive to a high-side drive with low cost and low power consumption.

[0005] To achieve the above object, the present invention provides the following technical solution: A device for converting a BMS-AFE low-side drive to a high-side drive, comprising a self-locking low-power conduction speed adjustable circuit module, a self-locking low-power turn-off speed adjustable circuit module, and a controlled PMOS transistor Q3; the self-locking low-power conduction speed adjustable circuit module and the self-locking low-power turn-off speed adjustable circuit module act on the controlled PMOS transistor Q3 simultaneously, and the existing DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port are respectively connected to the self-locking low-power conduction speed adjustable circuit module and the self-locking low-power turn-off speed adjustable circuit module.

[0006] Among them, the preferred solution is that the self-locking low-power conduction speed adjustable circuit module includes a first drive level inversion circuit, a conduction speed control circuit, a PMOS tube charging circuit, a conduction time control module, a first steady-state low-power circuit, and a self-locking shutdown circuit reset circuit. Among them, one end of the first drive level inversion circuit is grounded, the other end is connected to the conduction speed control circuit, and then connected to the PMOS tube charging circuit to act on the controlled PMOS tube Q3. The DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the conduction time control module, the conduction time control module is connected to the first steady-state low-power circuit, and the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port and the self-locking shutdown circuit reset circuit.

[0007] Among them, the preferred solutions are: the first and second drive level inversion circuits are relays, optocouplers, and BJT electronic switches.

[0008] Among them, the preferred solution is that the self-locking low-power conduction speed adjustable circuit module includes the K terminal of a zener diode ZD3 connected to the S terminal of the controlled PMOS tube Q3 of the CHG_EN port; the A terminal of the zener diode ZD3 is connected to the G port of the controlled PMOS tube Q3 after being connected in parallel with the sixth resistor R6; one end of the twentieth resistor R20 is connected to the G port of the controlled PMOS tube Q3, and the other end is connected to the E pole of the thirteenth triode Q13. One path of the base B of the thirteenth triode Q13 is connected to the E pole through the twenty-second resistor R22; the other path of the B pole of the thirteenth triode Q13 is connected to the D port of the tenth PMOS tube Q10 after being connected to the third capacitor C3; one path of the C pole of the thirteenth triode Q13 is connected to the E pole through the tenth resistor R10, and the other path of the C pole of the thirteenth triode Q13 is connected to the D port of the tenth PMOS tube Q10. The resistance value of the twentieth resistor R20 and the size of the third capacitor C3 are used to adjust the charging speed.

[0009] Among them, the preferred solution is that the self-locking low-power shutdown speed adjustable circuit module includes a second drive level inversion circuit, a shutdown speed control circuit, a PMOS tube discharging circuit, a shutdown time control circuit, a second steady-state low-power circuit, and a conduction reset circuit. Among them, one end of the second drive level inversion circuit is grounded, the other end is connected to the shutdown speed control circuit, and the shutdown speed control circuit and the PMOS tube discharging circuit act on the controlled PMOS tube Q3; the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the shutdown time control circuit, the shutdown time control circuit is connected to the second steady-state low-power circuit; the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the conduction reset circuit.

[0010] Among them, the preferred solution is that the self-locking low-power cut-off speed adjustable circuit module includes: the emitter E of the fifth triode Q5 is connected to the S port of the controlled PMOS transistor Q3, the collector C of the fifth triode Q5 is connected to the G port of the PMOS transistor Q3, the base B of the fifth triode Q5 is connected to the D port of the ninth PMOS transistor Q9 after being connected in series with the twelfth resistor R12, and one path of the G port of the ninth PMOS transistor Q9 is grounded through the series-connected eighteenth resistor R18; the other path of the G port of the ninth PMOS transistor Q9 is connected to the collector C of the seventh triode Q7 after being connected in series with the sixteenth resistor R16, and one path of the emitter E of the seventh triode Q7 is connected to the fourth capacitor C4 to ground; the other path of the emitter E of the seventh triode Q7 is connected to the second diode D2, connected in series with the eighth resistor R8 and connected to the base B of the seventh triode Q7, and connected to the CHG_EN port through the fourteenth resistor R14. The twelfth resistor R12 connected between the base B of the fifth triode Q5 and the D port of the ninth PMOS transistor Q9 adjusts the cut-off speed of the controlled PMOS transistor Q3.

[0011] The present invention also includes a method for converting a BMS-AFE low-side drive to a high-side drive, including:

[0012] Step 1: If the DSG-EN access port or the CHG-EN port or the PCHG-EN port or the PDSG-EN port pulls up the high level; the self-locking cut-off circuit reset circuit, the PMOS transistor charging circuit charges, the controlled PMOS transistor Q3 conducts, after the PMOS transistor charging circuit is fully charged and enters the steady state, the fast charging second steady-state low-power circuit (25) self-locks and cuts off, and the conduction maintaining circuit works;

[0013] Step 2: If the DSG-EN access port or the CHG-EN port or the PCHG-EN port or the PDSG-EN port pulls down the low level, the first drive level inversion circuit inverts, and the cut-off circuit reset circuit makes the first drive level inversion circuit conduct through the steady-state low-power self-locking circuit, and the PMOS transistor discharging circuit starts to discharge the controlled PMOS transistor Q3. After the discharge ends, the first steady-state low-power circuit, the first drive level inversion circuit, and the PMOS transistor discharging circuit cut off;

[0014] Step 3: According to the high / low level signal of the DSG-EN access port or the CHG-EN port or the PCHG-EN port or the PDSG-EN port, repeat Steps 1 and 2.

[0015] The method includes: Step 1: The DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port pulls up the level, the tenth PMOS transistor Q10 conducts, and the controlled PMOS transistor Q3, the twentieth resistor R20, the thirteenth triode Q13, and the third capacitor C3 charge the parasitic capacitance from the port G to S of the controlled PMOS transistor Q3 until reaching the regulated voltage value of the zener diode ZD3. At the same time, the fourth capacitor C4 is fully charged by CHG_EN, and the seventh triode Q7, the ninth PMOS transistor Q9, and the fifth triode Q5 are cut off; after the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port pulls down the level, it enters the process of turning off the controlled PMOS transistor Q3. The tenth PMOS transistor Q10 is cut off, the fourth capacitor C4 discharges through the saturation of the seventh triode Q7, the ninth PMOS transistor Q9 conducts, and after the ninth PMOS transistor Q9 conducts, the fifth triode Q5 starts to discharge the controlled PMOS transistor Q3. After the fourth capacitor C4 discharges to 0, the seventh triode Q7, the ninth PMOS transistor Q9, and the fifth triode Q5 are cut off simultaneously.

[0016] The beneficial effects of the present invention are:

[0017] 1. The BMS-AFE low-side drive to high-side drive device of the present invention can select appropriate on-drive speed and off-drive speed according to the actual application scenario.

[0018] 2. The drive circuit itself of the present invention should not have additional power consumption, meeting the requirements of low-power application scenarios. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is the schematic diagram of a BMS-AFE low-side drive to high-side drive device of the present invention;

[0021] Figure 2 It is the module schematic diagram of a BMS-AFE low-side drive to high-side drive device of the present invention.

[0022] Figure 3 It is the circuit schematic diagram of the first embodiment of the self-locking low-power on-speed adjustable circuit module (10) and the self-locking low-power off-speed adjustable circuit module 20 of the present invention.

[0023] Reference Signs:

[0024] 1……Low-side drive to high-side drive device

[0025] 100……BMS-AFE low-side drive to high-side drive circuit of the prior art

[0026] 10……Self-locking low-power conduction speed adjustable circuit module

[0027] 11……First drive level inversion circuit

[0028] 12……Conduction speed control circuit

[0029] 13……PMOS tube charging circuit

[0030] 14……Conduction time control module

[0031] 15……First steady-state low-power circuit

[0032] 16……Self-locking shutdown circuit reset circuit

[0033] 20……Self-locking low-power shutdown speed adjustable circuit module

[0034] 21……Second drive level inversion circuit

[0035] 22……Shutdown speed control circuit

[0036] 23……PMOS tube discharging circuit

[0037] 24……Shutdown time control circuit

[0038] 25……Second steady-state low-power circuit

[0039] 26……Conduction reset circuit

[0040] Q3……Controlled PMOS tube Detailed implementation manners

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] Figure 1 It is the schematic diagram of the device for BMS-AFE low-side drive to high-side drive of the present invention, as Figure 1As shown: At the DSG-EN access port, CHG-EN port, PCHG-EN port, and PDSG-EN port of the BMS-AFE low-side drive to high-side drive circuit 100 in the prior art, a BMS-AFE low-side drive to high-side drive device 1 is respectively connected. The BMS-AFE low-side drive to high-side drive device 1 includes a self-locking low-power conduction speed adjustable circuit module 10, a self-locking low-power turn-off speed adjustable circuit module 20, and a controlled PMOS transistor Q3; the self-locking low-power conduction speed adjustable circuit module 10 and the self-locking low-power turn-off speed adjustable circuit module 20 act on the controlled PMOS transistor Q3 simultaneously.

[0043] As Figure 2 shown: The self-locking low-power conduction speed adjustable circuit module 10 includes a first drive level inversion circuit 11, a conduction speed control circuit 12, a PMOS transistor charging circuit 13, a conduction time control module 14, a first steady-state low-power circuit 15, and a turn-off circuit reset circuit 16. Among them, one end of the first drive level inversion circuit 11 is grounded, and the other end is connected to the conduction time control module 14. The conduction PMOS transistor charging circuit 13 acts on the controlled PMOS transistor Q3. The DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the conduction time control module 14, the conduction time control module 14 is connected to the steady-state low-power self-locking circuit 15, and the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the turn-off circuit reset circuit 16.

[0044] The self-locking low-power turn-off speed adjustable circuit module 20 includes a second drive level inversion circuit 21, a turn-off speed control circuit 22, a PMOS transistor discharging circuit 23, a turn-off time control circuit 24, a second steady-state low-power circuit 25, and a conduction reset circuit 26. Among them, one end of the second drive level inversion circuit 21 is grounded, and the other end is connected to the turn-off speed control circuit 22. The turn-off speed control circuit 22 and the PMOS transistor discharging circuit 23 act on the controlled PMOS transistor Q3; any one of the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the turn-off time control circuit 24, the turn-off time control circuit 24 is connected to the second steady-state low-power circuit 25; the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the conduction reset circuit 26.

[0045] Figure 3This is the circuit schematic diagram of the first embodiment of the self-locking low-power conduction speed adjustable circuit module (10) and the self-locking low-power turn-off speed adjustable circuit module 20 of the present invention; in this embodiment, the self-locking low-power conduction speed adjustable circuit module 10 includes a connection between the S port of the controlled PMOS transistor Q3 of the CHG_EN port and the K terminal of the zener diode ZD3; the A terminal of the zener diode ZD3 is connected to the G port of the controlled PMOS transistor Q3 after being connected in parallel with the sixth resistor R6; one end of the twentieth resistor R20 is connected to the G port of the controlled PMOS transistor Q3, and the other end is connected to the E pole of the thirteenth triode Q13. One path of the B pole of the thirteenth triode Q13 is connected to the E pole through the twenty-second resistor R22; the other path of the B pole of the thirteenth triode Q13 is connected to the D port of the tenth PMOS transistor Q10 after connecting the third capacitor C3; one path of the C pole of the thirteenth triode Q13 is connected to the E pole through the tenth resistor R10, and the other path of the C pole of the thirteenth triode Q13 is connected to the D port of the tenth PMOS transistor Q10.

[0046] The working principle of the self-locking low-power conduction speed adjustable circuit module 10 is as follows: after CHG_EN pulls up the high level, it enters the conduction process of the controlled PMOS transistor Q3. At this time, the tenth PMOS transistor Q10 conducts, and the body diode of the PMOS transistor Q3 (or PACK+ through the body diode of Q4), as well as the twentieth resistor R20, the thirteenth triode Q13, and the third capacitor C3 charge the G port to the S end of the controlled PMOS transistor Q3. In this embodiment, when the charging reaches the conduction voltage value, that is, the voltage value of the third crystal diode ZD3. Among them, the voltage value in this embodiment is -15V. Among them, the charging speed depends on the conduction speed of the controlled PMOS transistor Q3 and can be adjusted by the resistance value of the twentieth resistor R20 and the size of the third capacitor C3. When the charging is completed and enters the steady state, the thirteenth triode Q13 is cut off, and the leakage current is determined by the tenth resistor R10 connected between the emitter E and the collector C of the thirteenth triode Q13. The tenth resistor R10 belongs to a relatively high resistance. In this way, the stable voltage value of the third crystal diode ZD3 and the tenth resistor R10 between the emitter E and the collector C of the thirteenth triode Q13 achieve low power consumption of the steady-state drive circuit; at the same time, during the conduction process of the controlled PMOS transistor Q3, the fourth capacitor C4 of the self-locking low-power turn-off speed adjustable circuit module 20 is filled (reset) by CHG_EN, and the seventh capacitor Q7, the ninth PMOS transistor Q9, and the fifth triode Q5 are always cut off. Therefore, the self-locking low-power turn-off speed adjustable circuit module 20 does not affect the self-locking low-power conduction speed adjustable circuit module 10.

[0047] The self-locking low-power turn-off speed adjustable circuit module 20 in this embodiment includes: the emitter E of the fifth triode Q5 is connected to the S port of the PMOS transistor Q3, the collector C of the fifth triode Q5 is connected to the G port of the PMOS transistor Q3, the base B of the fifth triode Q5 is connected to the D port of the ninth PMOS transistor Q9 after being connected in series with the twelfth resistor R12, and one path of the G port of the ninth PMOS transistor Q9 is grounded through the eighteenth resistor R18 connected in series; the other path of the G port of the ninth PMOS transistor Q9 is connected in series with the sixteenth resistor R16 and the collector C of the seventh triode Q7, and one path of the emitter E of the seventh triode Q7 is connected to the fourth capacitor C4 and grounded; the other path of the emitter E of the seventh triode Q7 is connected to the second diode D2, connected in series with the eighth resistor R8 and the base B of the seventh triode Q7, and connected to CHG_EN through the fourteenth resistor R14.

[0048] The working principle of the self-locking low-power turn-off speed adjustable circuit module 20 is as follows: after the CHG_EN port is pulled to a low level, during the turn-off process of the PMOS transistor Q3 in the self-locking low-power conduction speed adjustable circuit module 10, at this time, the tenth PMOS transistor Q10 is cut off, and the fourth capacitor C4 discharges through the emitter E and base B of the seventh triode Q7 and causes the seventh triode Q7 to be saturated and conduct, resulting in the charging and conduction of the G port to the S end of the ninth PMOS transistor Q9. After the ninth PMOS transistor Q9 conducts, the fifth triode Q5 starts to discharge the PMOS transistor Q3. This discharge speed (i.e., the turn-off speed of Q3) is mainly adjusted by the twelfth resistor R12 connected between the base B of the fifth triode Q5 and the D port of the ninth PMOS transistor Q9. After the fourth capacitor C4 finishes discharging, the seventh triode Q7, the PMOS transistor Q9, and the fifth triode Q5 are all cut off at the same time, and there is no steady-state power consumption in the entire drive circuit, realizing the low power consumption of the steady-state drive circuit. At the same time, during this process, the third capacitor C3 discharges (resets) through the twenty-second resistor R22 and the tenth resistor R10 to wait for the next conduction.

[0049] The beneficial effects of the present invention are:

[0050] The BMS-AFE low-side drive to high-side drive device 1 of the present invention adjusts the drive speed or turn-off drive speed through the conduction time control module 14 or the turn-off time control circuit 24, so that the appropriate conduction drive speed or turn-off drive speed can be selected according to the actual application scenario. The first steady-state low-power circuit 15 and the second steady-state low-power circuit 25 of the BMS-AFE low-side drive to high-side drive device 1 of the present invention have no additional power consumption, meeting the scenarios with low-power application requirements. The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A device for converting BMS-AFE low-side drive to high-side drive, characterized in that: It includes a self-locking low-power conduction speed adjustable circuit module (10), a self-locking low-power turn-off speed adjustable circuit module (20), and a controlled PMOS transistor Q3; the self-locking low-power conduction speed adjustable circuit module (10) and the self-locking low-power turn-off speed adjustable circuit module (20) act on the controlled PMOS transistor Q3 simultaneously. The existing DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port are respectively connected to the self-locking low-power conduction speed adjustable circuit module (10) and the self-locking low-power turn-off speed adjustable circuit module (20). The self-locking low-power conduction speed adjustable circuit module (10) includes a first drive level inversion circuit (11), a conduction speed control circuit (12), a PMOS transistor charging circuit (13), a conduction time control module (14), a first steady-state low-power circuit (15), and a self-locking turn-off circuit reset circuit (16). Among them, one end of the first drive level inversion circuit (11) is grounded, and the other end is connected to the conduction speed control circuit (12), and then connected to the PMOS transistor charging circuit (13) to act on the controlled PMOS transistor Q3. The DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port are connected to the conduction time control module (14), the conduction time control module (14) is connected to the first steady-state low-power circuit (15), and the DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port are connected to the self-locking turn-off circuit reset circuit (16).

2. The device for converting the low-side drive of the BMS-AFE to a high-side drive according to claim 1, wherein: The self-locking low-power conduction speed adjustable circuit module (10) includes that the K end of a voltage stabilizing diode ZD3 is connected to the S port of the controlled PMOS transistor Q3 of the CHG_EN port; the A end of the voltage stabilizing diode ZD3 is connected to the G port of the controlled PMOS transistor Q3 after being connected in parallel with a sixth resistor R6; one end of a twentieth resistor R20 is connected to the G port of the controlled PMOS transistor Q3, and the other end is connected to the E pole of a thirteenth triode Q13. One path of the B pole of the thirteenth triode Q13 is connected to the E pole through a twenty-second resistor R22; the other path of the B pole of the thirteenth triode Q13 is connected to the D port of a tenth PMOS transistor Q10 after being connected to a third capacitor C3; one path of the C pole of the thirteenth triode Q13 is connected to the E pole through a tenth resistor R10, and the other path of the C pole of the thirteenth triode Q13 is connected to the D port of the tenth PMOS transistor Q10.

3. The device for converting the low-side drive of the BMS-AFE to a high-side drive according to claim 2, wherein: The resistance value of the twentieth resistor R20 and the size of the third capacitor C3 are used to adjust the charging speed.

4. The device for converting the low-side drive of the BMS-AFE to a high-side drive according to claim 1, wherein: The self-locking low-power cut-off speed adjustable circuit module (20) includes a second drive level inversion circuit (21), a cut-off speed control circuit (22), a PMOS transistor discharge circuit (23), a cut-off time control circuit (24), a second steady-state low-power circuit (25), and a conduction reset circuit (26). Among them, one end of the second drive level inversion circuit (21) is grounded, and the other end is connected to the cut-off speed control circuit (22). The cut-off speed control circuit (22) and the PMOS transistor discharge circuit (23) act on the controlled PMOS transistor Q3. The DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the cut-off time control circuit (24), and the cut-off time control circuit (24) is connected to the second steady-state low-power circuit (25). The DSG-EN access port / CHG-EN port / PCHG-EN port / PDSG-EN port is connected to the conduction reset circuit (26).

5. The device for converting the BMS-AFE low-side drive to a high-side drive according to claim 4, wherein: The self-locking low-power cut-off speed adjustable circuit module (20) includes: the emitter E of the fifth triode Q5 is connected to the S port of the PMOS transistor Q3, the collector C of the fifth triode Q5 is connected to the G port of the PMOS transistor Q3, the base B of the fifth triode Q5 is connected to the D port of the ninth PMOS transistor Q9 after being connected in series with the twelfth resistor R12, and one path of the G port of the ninth PMOS transistor Q9 is connected to the ground through the eighteenth resistor R18; the other path of the G port of the ninth PMOS transistor Q9 is connected to the collector C of the seventh triode Q7 after being connected in series with the sixteenth resistor R16, and one path of the emitter E of the seventh triode Q7 is connected to the ground through the fourth capacitor C4; the other path of the emitter E of the seventh triode Q7 is connected to the second diode D2, connected in series with the eighth resistor R8 and the base B of the seventh triode Q7, and connected to CHG_EN through the fourteenth resistor R14.

6. The device for converting the low-side drive of the BMS-AFE to a high-side drive according to claim 5, wherein: The twelfth resistor R12 connected between the base B of the fifth triode Q5 and the D port of the PMOS transistor Q9 adjusts the cut-off speed of the controlled PMOS transistor Q3.

7. The device for converting the low-side drive of the BMS-AFE to a high-side drive according to claim 1 or 4, characterized in that: The first drive level inversion circuit (11) and the second drive level inversion circuit (21) are relays, optocouplers, and BJT electronic switches.

8. A method for converting a BMS-AFE low-side drive to a high-side drive, characterized in that: Including: Step 1: If the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port is pulled to a high level; the self-locking cut-off circuit reset circuit (16) is reset, the PMOS transistor charging circuit (13) charges, the controlled PMOS transistor Q3 conducts, and after the PMOS transistor charging circuit (13) is fully charged and enters the steady state, the second steady-state low-power circuit (25) is self-locked and cut off, and the conduction maintenance circuit works. Step 2: If the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port pulls down the level, the second drive level inversion circuit (21) inverts, and the shutdown circuit reset circuit (16) enables the first drive level inversion circuit (11) to conduct through the steady-state low-power self-locking circuit (15). The PMOS transistor discharge circuit (23) starts to discharge the controlled PMOS transistor Q3. After the discharge ends, the second steady-state low-power circuit (25), the second drive level inversion circuit (21), and the PMOS transistor discharge circuit (23) are cut off; Step 3: According to the high / low level signals of the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port, repeat Steps 1 and 2.

9. A method for converting a BMS-AFE low-side drive to a high-side drive; the characteristics include: Step 1: When the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port pulls up the level, the tenth PMOS transistor Q10 conducts, and the controlled PMOS transistor Q3, the twentieth resistor R20, the thirteenth triode Q13, and the third capacitor C3 charge the parasitic capacitance from the port G to S of the controlled PMOS transistor Q3 until the preset voltage stabilization value of the voltage stabilizing diode ZD3 is reached. At the same time, the fourth capacitor C4 is fully charged by CHG_EN, and the seventh triode Q7, the ninth PMOS transistor Q9, and the fifth triode Q5 are cut off; Step 2: After the DSG-EN access port or CHG-EN port or PCHG-EN port or PDSG-EN port pulls down the level, the controlled PMOS transistor Q3 enters the turn-off process. The tenth PMOS transistor Q10 is cut off. After the fourth capacitor C4 discharges through the saturation of the seventh triode Q7, the ninth PMOS transistor Q9 conducts, and the fifth triode Q5 starts to discharge the controlled PMOS transistor Q3. After the fourth capacitor C4 discharges to 0, the seventh triode Q7, the ninth PMOS transistor Q9, and the fifth triode Q5 are cut off simultaneously.

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