Drive buffer circuit and buffer without compensation capacitor

Abstract

The present application discloses a driving buffer circuit and a buffer without a compensation capacitor, including: an operational amplifier circuit, a first resistor, and a switching circuit, wherein: the operational amplifier circuit is of a two-stage structure, and Vp is input to the positive input terminal of the operational amplifier circuit; the negative input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit; the output terminal of the operational amplifier circuit is connected to the first resistor, and the second terminal is connected to the first input terminal of the switching circuit. The power input terminal of the switching circuit is connected to Vp, the control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor; when the control signal is at a low level, the output voltage of the switching circuit is made Vp, and at this time the circuit has a large driving ability and a high response speed. When the control signal is at a high level, the output voltage of the switching circuit is made 0, and the stability of the operational amplifier is ensured at this time. The circuit provided by the present application can achieve improving the stability of the operational amplifier of the driving buffer circuit while maintaining a high bandwidth.

Description

Technical Field

[0001] The present application relates to the technical field of drive buffer circuits, and particularly to a drive buffer circuit and a buffer without a compensation capacitor. Background Art

[0002] A buffer register, also known as a buffer, is mostly used on a bus and is a MOS transistor with a very large aspect ratio. A large aspect ratio means a large current, which is used to improve the clock driving ability and isolate the front and rear stages, so that the clock has good rising and falling edges. Therefore, how to ensure the operational amplifier stability of the drive buffer circuit has become an important research direction.

[0003] In the prior art, a compensation capacitor is usually added at the output end of the first-stage operational amplifier and the output end of the second-stage operational amplifier of the drive buffer circuit to ensure the operational amplifier stability of the drive buffer circuit, but this will reduce the overall bandwidth of the circuit; and when facing the circuit requirements with higher speed requirements, it is required to ensure that the circuit has a larger bandwidth. If the compensation capacitor is not added, the operational amplifier stability of the drive buffer circuit will face great challenges. Summary of the Invention

[0004] The purpose of the present application is to propose a drive buffer circuit and a buffer without a compensation capacitor to improve the operational amplifier stability of the drive buffer circuit while maintaining high bandwidth.

[0005] To achieve the above object, the present application provides the following technical solutions:

[0006] A drive buffer circuit without a compensation capacitor includes: an operational amplifier circuit, a first resistor R1, and a switching circuit, where:

[0007] The operational amplifier circuit is of a two-stage structure. The positive input terminal of the operational amplifier circuit inputs Vp, and Vp is a stable potential with driving ability; the negative input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit;

[0008] The output terminal of the operational amplifier circuit is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first input terminal of the switching circuit. The power input terminal of the switching circuit is connected to Vp. The control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor;

[0009] When the control signal is at a low level, the output voltage at the output terminal of the switching circuit is Vp. At this time, the circuit has a large driving ability and a high response speed. When the control signal is at a high level, the output voltage at the output terminal of the switching circuit is 0, and the stability of the operational amplifier is ensured at this time.

[0010] Preferably, the operational amplifier circuit includes an input pair of transistors and a second resistor R2. The input pair of transistors includes switching transistors NM1 and NM2, switching transistors PM1 and PM2, and a switching transistor NM3, which form a first-stage operational amplifier. Its output drives a switching transistor PM3. The sources of the switching transistors PM1, PM2, and PM3 are connected together and connected to a voltage source Vcc. The gates of the switching transistors PM1 and PM2 are connected together. The gate of the switching transistor PM3 is connected to the drain of the switching transistor PM2, and their common terminal is connected to the source of the switching transistor NM2. The drain of the switching transistor PM1 is connected to its gate, and their common terminal is connected to the source of the switching transistor NM1. The drains of the switching transistors NM1 and NM2 are connected together, and their common terminal is connected to the source of the switching transistor NM3. The gate of the switching transistor NM3 is connected to the source of the switching transistor NM1. The gate of the switching transistor NM1 serves as the negative input terminal of the operational amplifier circuit. The gate of the switching transistor NM2 serves as the positive input terminal of the operational amplifier circuit. The drain of the switching transistor PM3 is connected to the negative input terminal, and the second resistor R2 is connected to form a second-stage operational amplifier, and the other end of the second resistor R2 is grounded.

[0011] Preferably, the switching transistors NM1, NM2, and NM3 are NMOS transistors.

[0012] Preferably, the switching transistor NM3 is a tail current source and uses self-biasing.

[0013] Preferably, the switching transistors PM1, PM2, and PM3 are PMOS transistors.

[0014] Preferably, the switching circuit includes: switching transistors PM4 and PM5, switching transistors NM4 and NM5, and an inverter G, where:

[0015] The gate of the switching transistor PM4 is connected to the output terminal of the inverter G. The source of the switching transistor PM4 is connected to the Vp. The drain of the switching transistor PM4 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the source of the switching transistor PM5, and their common terminal serves as the input terminal of the switching circuit;

[0016] The input terminal of the inverter G is connected to the gates of the switching transistor PM5 and the switching transistor NM4, and their common terminal serves as the control terminal of the switching circuit; The drains of the switching transistor PM5 and the source of the switching transistor NM4 are connected together, and their common terminal is connected to the source of the switching transistor NM5. The drain of the switching transistor NM4 is grounded;

[0017] The gate of the switching transistor NM5 is connected to the voltage source Vcc, the drain of the switching transistor NM5 is connected to the first end of the load capacitor CL, and the common end serves as the output end of the switching circuit; the second end of the load capacitor CL is grounded.

[0018] Preferably, the switching transistors PM4 and PM5 are PMOS transistors.

[0019] Preferably, the switching transistors NM4 and NM5 are NMOS transistors.

[0020] A buffer includes the above-mentioned driving buffer circuit without a compensation capacitor.

[0021] Preferably, the buffer is a VCOM buffer in an LCD_Driver chip or a VREF_TP buffer in a touch chip or a VCG_TP buffer in a touch chip.

[0022] As can be seen from the above technical solutions, compared with the prior art, the present application discloses a driving buffer circuit and a buffer without a compensation capacitor, including: an operational amplifier circuit, a first resistor R1, and a switching circuit, where: the operational amplifier circuit is a two-stage structure, the positive input terminal of the operational amplifier circuit inputs Vp, and Vp is a stable potential and has driving ability; the negative input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit; the output terminal of the operational amplifier circuit is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first input terminal of the switching circuit, the power input terminal of the switching circuit is connected to Vp, the control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor; when the control signal is at a low level, the output voltage at the output terminal of the switching circuit is Vp, and at this time, the circuit has a large driving ability and a high response speed. When the control signal is at a high level, the output voltage at the output terminal of the switching circuit is 0, and the stability of the operational amplifier is ensured at this time. The driving buffer circuit without a compensation capacitor provided by the present application can improve the stability of the operational amplifier of the driving buffer circuit while maintaining a high bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0024] Figure 1 FIG. is a structural block diagram of a driving buffer circuit without a compensation capacitor provided by an embodiment of the present application;

[0025] Figure 2 This is a schematic diagram of the principle of a drive buffer circuit without a compensation capacitor provided by an embodiment of the present application. Specific embodiments

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0027] Please refer to the attached Figure 1 As shown, this is a structural block diagram of a drive buffer circuit without a compensation capacitor provided by an embodiment of the present application. As Figure 1 shown, an embodiment of the present application provides a drive buffer circuit without a compensation capacitor. The circuit includes: an operational amplifier circuit 11, a first resistor R1, and a switching circuit 12, where:

[0028] The operational amplifier circuit 11 has a two-stage structure. The positive input terminal of the operational amplifier circuit 11 inputs Vp, and Vp is a stable potential and has driving ability; the negative input terminal of the operational amplifier circuit 11 is connected to the output terminal of the operational amplifier circuit 11;

[0029] The output terminal of the operational amplifier circuit 11 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first input terminal of the switching circuit 12. The power input terminal of the switching circuit 12 is connected to Vp. The control terminal of the switching circuit 12 inputs a control signal, and the output terminal of the switching circuit 12 is connected to a load capacitor;

[0030] When the control signal is at a low level, the output voltage at the output terminal of the switching circuit 12 is Vp. At this time, the circuit has a large driving ability and a high response speed. When the control signal is at a high level, the output voltage at the output terminal of the switching circuit 12 is 0, and the stability of the operational amplifier is ensured at this time.

[0031] The embodiment of the present application is mainly divided into two parts. As Figure 1 shown, the first part is the operational amplifier circuit on the left, and the second part is the switching circuit and the load on the right. The drive buffer circuit without a compensation capacitor provided by the embodiment of the present application is used to output a stable voltage Vp when the control signal A is low and pull OUT to ground when the control signal A is high.

[0032] In the embodiment of the present application, as Figure 2As shown, the operational amplifier circuit 11 includes an input pair of transistors and a second resistor R2. The input pair of transistors includes a switching transistor NM1, a switching transistor NM2, a switching transistor PM1, a switching transistor PM2, and a switching transistor NM3, which form a first-stage operational amplifier. Its output drives a switching transistor PM3. The sources of the switching transistor PM1, the switching transistor PM2, and the switching transistor PM3 are connected together and connected to a voltage source Vcc. The gates of the switching transistor PM1 and the switching transistor PM2 are connected together. The gate of the switching transistor PM3 is connected to the drain of the switching transistor PM2, and their common terminal is connected to the source of the switching transistor NM2. The drain of the switching transistor PM1 is connected to its gate, and their common terminal is connected to the source of the switching transistor NM1. The drains of the switching transistor NM1 and the switching transistor NM2 are connected together, and their common terminal is connected to the source of the switching transistor NM3. The gate of the switching transistor NM3 is connected to the source of the switching transistor NM1. The gate of the switching transistor NM1 serves as the negative input terminal of the operational amplifier circuit, and the gate of the switching transistor NM2 serves as the positive input terminal of the operational amplifier circuit. The drain of the switching transistor PM3 is connected to the negative input terminal, and the second resistor R2 is connected to form a second-stage operational amplifier, and the other end of the second resistor R2 is grounded.

[0033] It should be noted that the switching transistor NM1, the switching transistor NM2, and the switching transistor NM3 are NMOS transistors.

[0034] It should be noted that the switching transistor PM1, the switching transistor PM2, and the switching transistor PM3 are PMOS transistors.

[0035] In the embodiment of the present application, as Figure 2 shown, the switching circuit includes: a switching transistor PM4, a switching transistor PM5, a switching transistor NM4, a switching transistor NM5, and an inverter G, where:

[0036] The gate of the switching transistor PM4 is connected to the output terminal of the inverter G. The source of the switching transistor PM4 is connected to the Vp. The drain of the switching transistor PM4 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the source of the switching transistor PM5, and their common terminal serves as the input terminal of the switching circuit;

[0037] The input terminal of the inverter G is connected to the gate of the switching transistor PM5 and the gate of the switching transistor NM4, and their common terminal serves as the control terminal of the switching circuit; the drain of the switching transistor PM5 and the source of the switching transistor NM4 are connected together, and their common terminal is connected to the source of the switching transistor NM5. The drain of the switching transistor NM4 is grounded;

[0038] The gate of the switching transistor NM5 is connected to the voltage source Vcc, the drain of the switching transistor NM5 is connected to the first end of the load capacitor CL, and the common end serves as the output end of the switching circuit; the second end of the load capacitor CL is grounded.

[0039] It should be noted that the switching transistors PM4 and PM5 are PMOS transistors.

[0040] It should be noted that the switching transistors NM4 and NM5 are NMOS transistors.

[0041] The embodiment of this application is mainly divided into two parts, as Figure 2 shown. The first part is the operational amplifier circuit on the left, and the second part is the switching circuit and load on the right.

[0042] The driving buffer circuit without a compensation capacitor provided by the embodiment of this application is used to output a stable voltage Vp when the control signal A is low, and pull OUT to ground when the control signal A is high.

[0043] It should be noted that in the operational amplifier circuit, the switching transistors NM1 and NM2 are the input differential pair transistors of the operational amplifier. The positive input is Vp, and Vp is a stable potential obtained by stepping down the power supply and has driving ability. Vp also serves as the power supply for the switching transistor PM4.

[0044] The switching transistor NM3 is a tail current source and is self-biased. VCC - Vgs(PM1) is used to provide bias for the switching transistor NM3. The output ① of the first-stage operational amplifier drives the switching transistor PM3, and is connected to the second resistor R2 to form a second-stage operational amplifier. Point ② in the figure is the output of the second-stage operational amplifier, and this point is connected to the negative input terminal of the operational amplifier to form a buffer circuit.

[0045] As Figure 2 shown, the output of the above driving buffer circuit is connected to several switches. A is the control signal of these switches. When A is low, the switching transistor PM5 is turned on, and the switching transistors NM4 and PM4 are turned off. The buffer circuit charges the load capacitor CL. CL is the parasitic capacitance of the PAD, with a relatively large capacitance value, and is connected in series with the on-resistance of the switching transistor NM5, introducing a zero point, which plays a role in compensating the stability of the operational amplifier. When A is high, the switching transistor PM5 is turned off, and the switching transistors NM4 and PM4 are turned on. The charge on the load capacitor CL is discharged to ground through the switching transistor NM4. The output of the buffer circuit is connected to Vp through the second resistor R2. Among them, the resistance value of the first resistor R1 is small and is not directly connected to the load capacitor CL at this time, and the stability will be very poor. However, by connecting the small first resistor R1 in series, the gain of the operational amplifier is reduced, so the circuit can still be kept stable.

[0046] The driving buffer circuit without a compensating capacitor disclosed in the embodiments of the present application includes: an operational amplifier circuit, a first resistor R1, and a switching circuit, where: the operational amplifier circuit is a two-stage structure, the positive terminal input of the operational amplifier circuit inputs Vp, and Vp is a stable potential and has driving ability; the negative terminal input of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit; the output terminal of the operational amplifier circuit is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first input terminal of the switching circuit, the power input terminal of the switching circuit is connected to Vp, the control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor; when the control signal is at a low level, the output voltage at the output terminal of the switching circuit is Vp, at this time the circuit has a large driving ability and a high response speed, when the control signal is at a high level, the output voltage at the output terminal of the switching circuit is 0, and the stability of the operational amplifier is ensured at this time. The driving buffer circuit without a compensating capacitor provided by the embodiments of the present application can achieve improving the operational amplifier stability of the driving buffer circuit while maintaining a high bandwidth.

[0047] The embodiments of the present application also disclose a buffer, and this buffer includes the driving buffer circuit without a compensating capacitor described above.

[0048] In a specific embodiment, the above-mentioned buffer is a VCOM buffer in an LCD_Driver chip or a VREF_TP buffer in a touch chip or a VCG_TP buffer in a touch chip.

[0049] In summary, the embodiments of the present application disclose a driving buffer circuit without a compensating capacitor and a buffer, including: an operational amplifier circuit, a first resistor R1, and a switching circuit, where: the operational amplifier circuit is a two-stage structure, the positive terminal input of the operational amplifier circuit inputs Vp, and Vp is a stable potential and has driving ability; the negative terminal input of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit; the output terminal of the operational amplifier circuit is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first input terminal of the switching circuit, the power input terminal of the switching circuit is connected to Vp, the control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor; when the control signal is at a low level, the output voltage at the output terminal of the switching circuit is Vp, at this time the circuit has a large driving ability and a high response speed, when the control signal is at a high level, the output voltage at the output terminal of the switching circuit is 0, and the stability of the operational amplifier is ensured at this time. The driving buffer circuit without a compensating capacitor provided by the embodiments of the present application can achieve improving the operational amplifier stability of the driving buffer circuit while maintaining a high bandwidth.

[0050] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above element.

[0051] It should be noted that the above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving buffer circuit without a compensating capacitor, characterized in that Comprising: an operational amplifier circuit, a first resistor R1, and a switching circuit, wherein: the operational amplifier circuit is of a two-stage structure, the positive input terminal of the operational amplifier circuit inputs Vp, and Vp is a stable potential and has driving ability; the negative input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit; the output terminal of the operational amplifier circuit is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first input terminal of the switching circuit, the power input terminal of the switching circuit is connected to Vp, the control terminal of the switching circuit inputs a control signal, and the output terminal of the switching circuit is connected to a load capacitor; when the control signal is at a low level, the output voltage at the output terminal of the switching circuit is made to be Vp, at this time the circuit has a large driving ability and a high response speed, when the control signal is at a high level, the output voltage at the output terminal of the switching circuit is made to be 0, and the stability of the operational amplifier is ensured at this time; wherein, the switching circuit includes: a switching transistor PM4, a switching transistor PM5, a switching transistor NM4, a switching transistor NM5, and an inverter G, wherein: the gate of the switching transistor PM4 is connected to the output terminal of the inverter G, the source of the switching transistor PM4 is connected to Vp, the drain of the switching transistor PM4 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the source of the switching transistor PM5, and their common end serves as the input terminal of the switching circuit; the input terminal of the inverter G is connected to the gate of the switching transistor PM5 and the gate of the switching transistor NM4, and their common end serves as the control terminal of the switching circuit; the drain of the switching transistor PM5 and the source of the switching transistor NM4 are connected, and their common end is connected to the source of the switching transistor NM5, and the drain of the switching transistor NM4 is grounded; the gate of the switching transistor NM5 is connected to a voltage source Vcc, the drain of the switching transistor NM5 is connected to the first end of the load capacitor CL, and their common end serves as the output terminal of the switching circuit; the second end of the load capacitor CL is grounded.

2. The circuit according to claim 1, wherein The operational amplifier circuit includes an input pair of transistors and a second resistor R2. The input pair of transistors includes a switching transistor NM1, a switching transistor NM2, a switching transistor PM1, a switching transistor PM2, and a switching transistor NM3 to form a first-stage operational amplifier, whose output drives a switching transistor PM3. The sources of the switching transistor PM1, the switching transistor PM2, and the switching transistor PM3 are connected together and connected to a voltage source Vcc. The gates of the switching transistor PM1 and the switching transistor PM2 are connected together. The gate of the switching transistor PM3 is connected to the drain of the switching transistor PM2, and their common terminal is connected to the source of the switching transistor NM2. The drain of the switching transistor PM1 is connected to its gate, and their common terminal is connected to the source of the switching transistor NM1. The drains of the switching transistor NM1 and the switching transistor NM2 are connected together, and their common terminal is connected to the source of the switching transistor NM3. The gate of the switching transistor NM3 is connected to the source of the switching transistor NM1. The gate of the switching transistor NM1 serves as the negative terminal input of the operational amplifier circuit, and the gate of the switching transistor NM2 serves as the positive terminal input of the operational amplifier circuit. The drain of the switching transistor PM3 is connected to the negative terminal input, and connecting the second resistor R2 forms a second-stage operational amplifier, and the other end of the second resistor R2 is grounded.

3. The circuit according to claim 1, wherein The switching transistor NM1, the switching transistor NM2, and the switching transistor NM3 are NMOS transistors.

4. The circuit according to claim 3, characterized in that, The switching transistor NM3 is a tail current source and adopts self-biasing.

5. The circuit according to claim 1, wherein The switching transistor PM1, the switching transistor PM2, and the switching transistor PM3 are PMOS transistors.

6. The circuit according to claim 1, characterized in that, The switching transistor PM4 and the switching transistor PM5 are PMOS transistors.

7. The circuit according to claim 1, characterized in that, The switching transistor NM4 and the switching transistor NM5 are NMOS transistors.

8. A buffer, characterized in that, It includes the drive buffer circuit without a compensation capacitor according to any one of claims 1-7.

9. The buffer according to claim 8, wherein The buffer is a VCOM buffer in an LCD_Driver chip or a VREF_TP buffer in a touch chip or a VCG_TP buffer in a touch chip.

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