Internal electrode defect detection structure of chip resistor and screening method for defective resistors

Abstract

The present invention discloses an internal electrode defect detection structure for a chip resistor and a screening method for defective resistors. The internal electrode defect detection structure includes a receiving groove and a conductive structure disposed in the receiving groove. The receiving groove is provided on a protective layer outside the chip resistor, and the receiving groove sequentially penetrates through several protective layers of the chip resistor to the resistor layer. Both internal electrodes are exposed in the receiving groove, and the conductive structure is respectively connected to the two internal electrodes. By providing a receiving groove on the chip resistor with defective internal electrodes and filling the receiving groove with a conductive material to make the two internal electrodes conduct, the appearance and resistance value of the chip resistor with defects are changed, facilitating the later screening of the chip resistor with defective internal electrodes through appearance detection or resistance value measurement; it avoids manual waste and the risk of missed rejection caused by manual rejection, improves product quality, and also avoids the yield loss and resource waste caused by the method of rejecting an entire sheet or an entire strip, saving production costs.

Description

Technical Field

[0001] The present invention relates to the technical field of chip resistors, and in particular, to an internal electrode defect detection structure for a chip resistor with auxiliary electrodes and a screening method for defective resistors. Background Art

[0002] For a chip resistor with auxiliary electrodes, such as the anti-sulfuration chip resistor disclosed in patent CN211788403U, it is composed of a substrate 1, a back electrode 2, an internal electrode 3 (front electrode), a resistance layer 4, a first protective layer 5, a second protective layer 6, an auxiliary electrode 7, a vacuum coating layer 8, and a plating layer 9, as Figure 1 shown. When preparing it, multiple chip resistors need to be fabricated on a substrate, and then single-chip resistors are obtained after strip folding and grain folding. The specific preparation process mainly includes printing the back electrode 2, printing the internal electrode 3, printing the resistance layer 4, printing the first protective layer 5, trimming the resistance value, printing the second protective layer 6, printing the auxiliary electrode 7, printing the character code, strip folding, preparing the side vacuum coating layer 8, grain folding, and electroplating and depositing a nickel-tin layer. Due to the coverage of the auxiliary electrode 7, it is impossible to effectively identify defects in the internal electrode 3 before the strip station. Generally, pre-detection is required. For example, after printing the internal electrode 3, manual or detection equipment is used to detect the internal electrodes 3 of each chip resistor on the chip resistor plate, and the entire chip resistor plate or the entire chip resistor strip with defective internal electrodes 3 is screened and removed. This way of removing an entire sheet or an entire strip will result in a large loss of yield, cause waste, is not conducive to controlling production costs, and will also cause waste of labor and there are risks such as missed removal due to human errors, affecting product quality.

[0003] Therefore, in combination with the above existing technical problems, it is necessary to propose a new technical solution. Summary of the Invention

[0004] The purpose of the present invention is to provide an internal electrode defect detection structure for a chip resistor and a screening method for defective resistors. By setting a receiving groove on the chip resistor with a defective internal electrode and filling a conductive material in the receiving groove to make the two internal electrodes conduct, thereby changing the appearance and resistance value of the chip resistor with defects, it is convenient to screen out the chip resistor with a defective internal electrode through appearance detection or resistance measurement in the later stage.

[0005] To achieve the object of the invention, the present invention provides an internal electrode defect detection structure for a chip resistor. The chip resistor includes a substrate, two internal electrodes spaced on one side of the substrate, a resistor layer and a plurality of protective layers sequentially stacked and covering between the two internal electrodes, and an auxiliary electrode provided on the side of the internal electrode away from the substrate. The internal electrode defect detection structure includes a receiving groove and a conductive structure provided in the receiving groove. The receiving groove is provided on the outer protective layer, and the receiving groove sequentially penetrates through a plurality of the protective layers to the resistor layer. Both of the two internal electrodes are exposed in the receiving groove, and the conductive structure is respectively connected to the two internal electrodes.

[0006] Further, the receiving groove is strip-shaped, one end in the length direction of the receiving groove extends to one of the internal electrodes, and the other end in the length direction of the receiving groove extends to the other internal electrode.

[0007] Further, the length direction of the receiving groove is the same as the distribution direction of the internal electrodes; or there is a set angle between the length direction of the receiving groove and the distribution direction of the internal electrodes.

[0008] Further, the receiving groove is a curved strip, a broken line strip, a straight strip or a combination of two or more of the foregoing shapes.

[0009] Further, the conductive structure includes a nickel layer and a tin layer.

[0010] The present invention also provides a method for screening defective resistors, which includes the following steps:

[0011] Automatically optically inspect the chip resistor plate with the protective layer printed, and detect whether there are defects in the internal electrodes of each chip resistor on the chip resistor plate; set the above-mentioned defect detection structure on the chip resistor with defects; perform appearance inspection or resistance value measurement on all chip resistors, and screen out the chip resistors with defective internal electrodes provided with the defect detection structure.

[0012] Further, when setting the defect detection structure on the chip resistor, first cut a receiving groove on the defective chip resistor with the protective layer printed on the chip resistor plate, so that the two internal electrodes on the defective chip resistor are exposed in the receiving groove; then when electroplating and depositing a nickel layer and a tin layer on the folded chip resistor, deposit a conductive structure in the receiving groove, and the conductive structure is respectively connected to the two internal electrodes.

[0013] Compared with the prior art, the internal electrode defect detection structure of the chip resistor and the method for screening defective resistors of the present application have at least one or more of the following beneficial effects:

[0014] The internal electrode defect detection structure of the chip resistor of the present application and the screening method of defective resistors. By setting a receiving groove on the chip resistor with defective internal electrodes and filling the receiving groove with a conductive material to make the two internal electrodes conduct, the appearance and resistance value of the defective chip resistor are changed, becoming defective products in appearance and resistance value. Furthermore, the chip resistors with defective internal electrodes can be safely and reliably screened out through appearance detection or resistance measurement; it realizes the destruction and elimination of the chip resistors with defective internal electrodes one by one by the equipment without damaging the adjacent chip resistors, avoiding manual waste and the risk of missed elimination caused by manual elimination, improving product quality. At the same time, it also avoids the yield loss and resource waste caused by the elimination method of a whole piece or a whole strip, saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. is a schematic structural diagram of a chip resistor with auxiliary electrodes provided by an embodiment of the present application;

[0016] Figure 2 FIG. is a schematic structural diagram of a chip resistor with auxiliary electrodes provided by an embodiment of the present application and provided with a defect detection structure;

[0017] Figure 3 FIG. is a partial structural diagram of a chip resistor plate provided by an embodiment of the present application and cut with a receiving groove.

[0018] Wherein, 1 - substrate, 2 - back electrode, 3 - internal electrode, 4 - resistance layer, 5 - first protective layer, 6 - second protective layer, 7 - auxiliary electrode, 8 - vacuum coating layer, 9 - electroplating layer, 10 - receiving groove, 11 - conductive structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following combines the drawings and preferred embodiments to elaborate in detail on the specific implementation manners, structures, features, and effects according to the present invention.

[0020] Embodiment

[0021] Take as Figure 1Taking the chip resistor with auxiliary electrodes shown as an example, it is composed of a substrate 1, a back electrode 2, inner electrodes 3 (front electrodes), a resistance layer 4, a first protective layer 5, a second protective layer 6, auxiliary electrodes 7, a vacuum coating layer 8, and a plating layer 9. There are two back electrodes 2, which are arranged at intervals on one side of the substrate 1; there are two inner electrodes 3, which are arranged at intervals on the other side of the substrate 1; the resistance layer 4 is arranged between the two inner electrodes 3, and the edges of the resistance layer 4 are respectively lapped on the two inner electrodes 3; the first protective layer 5 covers the side of the resistance layer 4 away from the substrate 1, and the edges of the first protective layer 5 are respectively lapped on the two inner electrodes 3; the second protective layer 6 covers the side of the first protective layer 5 away from the substrate 1, and the edges of the second protective layer 6 are respectively lapped on the two inner electrodes 3; the auxiliary electrodes 7 are arranged on the side of the inner electrodes 3 away from the substrate 1, and the auxiliary electrodes 7 are overlapped and connected with the second protective layer 6; the vacuum coating layer 8 is symmetrically arranged at both ends of the substrate 1, and one end of the vacuum coating layer 8 extends to the side of the auxiliary electrode 7 away from the inner electrode 3, and the other end extends to the side of the back electrode 2 away from the substrate 1, and the vacuum coating layer 8 covers the end sides of the substrate 1; the plating layer 9 covers the outside of the back electrode 2, the vacuum coating layer 8, and the inner electrodes 3.

[0022] The preparation process of the above-mentioned chip resistor mainly protects the following steps:

[0023] First, print the back electrode 2 on the substrate 1. The substrate 1 is, for example, a ceramic substrate, which is a large substrate 1, and multiple chip resistors can be prepared at one time, as Figure 3 shown. Using screen printing technology, print the back electrode paste on one side of the substrate 1, and then form the back electrode 2 through drying. The back electrode paste can be, for example, a paste material containing silver, silver target, or copper, etc.

[0024] After that, print the inner electrodes 3 on the substrate 1. Using screen printing technology, print the inner electrode paste on the other side of the substrate 1, and then form the inner electrodes 3 through drying. The inner electrode paste can be, for example, a paste material containing silver, silver target, or copper, etc.

[0025] After that, perform high-temperature sintering on the substrate plate printed with the back electrode 2 and the inner electrodes 3.

[0026] After that, print the resistance layer 4 on the substrate 1. Using screen printing technology, print the resistance paste on the substrate 1 between the two inner electrodes 3, and make the edge of the resistance paste extend to the inner electrodes 3; then perform high-temperature sintering on the substrate plate printed with the resistance paste. The resistance paste can be a resistance paste material such as ruthenium oxide.

[0027] Subsequently, a first protective layer 5 is printed on the resistance layer 4. Using screen printing technology, glass paste is printed and covered on the resistance layer 4, and the edge of the glass paste layer extends onto the inner electrode 3. Then, the substrate plate printed with the glass paste is subjected to high-temperature sintering.

[0028] Subsequently, the resistance value is trimmed. The resistance value of the resistance layer 4 is trimmed by laser cutting, and the discrete resistance values are adjusted to within the range of the target resistance value.

[0029] Subsequently, a second protective layer 6 is printed on the first protective layer 5. Using screen printing technology, a resin insulating material is printed and covered on the first protective layer 5, and the edge of the resin insulating material layer extends onto the inner electrode 3. Define the substrate plate on which the protective layer is printed at this time as the chip resistor plate.

[0030] Subsequently, an auxiliary electrode 7 is printed on the inner electrode 3. Using screen printing technology, a resin-based conductive material, such as silver material, etc., is covered on the area of the inner electrode 3 that is not covered by the resistance layer 4 and the protective layer. It forms a protection for the inner electrode 3. After electroplating, the surface of the auxiliary electrode 7 will be covered with nickel and tin, forming a protection for the auxiliary material and meeting the size requirements of the front terminal at the same time.

[0031] Subsequently, a marking material is printed on the surface of the second protective layer 6. The marking material is preferably a white material for marking the resistance value.

[0032] Subsequently, the second protective layer 6, the auxiliary electrode 7, and the marking material printed on the substrate plate are cured to form a firm structure, meeting the requirements of wear resistance and weather resistance.

[0033] Subsequently, the cured chip resistor plate is folded into strip-shaped chip resistor strips by mechanical force and neatly arranged in a jig.

[0034] Subsequently, a vacuum coating layer 8 is prepared. The chip resistor strips arranged in the jig are coated with nickel-chromium alloy or a similar series of conductive materials or alloy materials under vacuum conditions to form a side terminal, enabling communication between the inner electrode 3 and the back electrode 2.

[0035] Subsequently, the chip resistor strips coated with nickel-chromium alloy are folded into granular units by mechanical force to obtain chip resistor particles, that is, single-chip resistors.

[0036] Subsequently, an electroplated layer 9 is prepared. Nickel and tin are electroplated and deposited on the auxiliary electrode 7, the vacuum coating layer 8, and the back electrode 2.

[0037] To facilitate the screening of chip resistors with defective inner electrodes, this embodiment provides an inner electrode defect detection structure, which includes a receiving groove 10 and a conductive structure 11 disposed in the receiving groove 10. AsFigure 2 As shown, the accommodation groove 10 is provided on the outermost protective layer, that is, the second protective layer 6. The accommodation groove 10 sequentially penetrates through several protective layers to the resistance layer 4, and both of the inner electrodes 3 are exposed in the accommodation groove 10. The conductive structure 11 is respectively connected to both of the inner electrodes 3. The accommodation groove 10 is elongated, and one end of the accommodation groove 10 in the length direction extends to one of the inner electrodes 3, and the other end of the accommodation groove 10 in the length direction extends to the other inner electrode 3. Preferably, the accommodation groove 10 is a straight elongated shape, as Figure 3 shown, its length direction is consistent with the length direction of the chip resistor, that is, consistent with the distribution direction of both of the inner electrodes 3, wherein, Figure 3The dotted lines arranged horizontally and vertically shown are reference lines, only indicating the positions of the folding strips or folding grains. Of course, there may also be a set angle between the length direction of the accommodating groove 10 and the distribution direction of the inner electrode 3. The accommodating groove 10 may also be a long strip of other shapes, such as a curved long strip, a broken line long strip, or a combination of two or more of the foregoing shapes. For example, a part of the accommodating groove 10 is a straight long strip, and another part is a curved long strip or a broken line long strip, etc., as long as both ends of the accommodating groove 10 can extend to two inner electrodes 3 respectively so that both inner electrodes 3 are exposed in the accommodating groove 10. The accommodating groove 10 can be realized by laser cutting. Before printing the auxiliary electrode 7, an automatic optical inspection (AOI) is performed on the wafer resistor plate after the protective layer is printed to detect the wafer resistor with defective inner electrodes 3. Then, the wafer resistor with defective inner electrodes 3 is cut by laser on the outermost protective layer to form the accommodating groove 10. Then, when preparing the plating layer 9, a nickel layer and / or a tin layer will be electroplated and deposited in the accommodating groove 10, thereby forming a conductive structure 11 to conduct between the two inner electrodes 3. When cutting the accommodating groove 10, the cutting power can be controlled to reduce the cutting heat radiation area and the amount of cutting dust. The cutting depth of the laser, that is, the depth of the accommodating groove 10, should be controlled to damage several years of protective layers covering the resistor layer 4 so that the resistor layer 4 is exposed in the accommodating groove 10. And the substrate 1 should not be damaged during cutting to avoid unstable resistor residue. Once the resistor residue is unstable due to cutting the substrate 1, the deposition of the nickel layer and the tin layer during the preparation of the plating layer 9 will be unstable, which will lead to poor short-circuit resistance effect. In this way, if only impedance is relied on to screen out the wafer resistor with defective inner electrodes 3, the risk of misflow of defective products will be relatively large. At the same time, when cutting the accommodating groove 10, the cutting length must be greater than the effective resistor length, that is, the cut accommodating groove 10 should extend to the two inner electrodes 3 so that the inner electrodes 3 covered by the protective layer are exposed in the accommodating groove 10. During cutting, the maximum cutting length, that is, the maximum length of the accommodating groove 10, is the maximum length at which the cutting heat radiation area and the dust deposition area do not affect the inner electrodes 3 of adjacent wafer resistors; and the cutting width, that is, the width of the accommodating groove 10, should be wide enough to expose a wide enough resistor layer 4, but the maximum width cannot make the cutting heat radiation area affect adjacent wafer resistors.

[0038] By cutting the accommodating groove 10 on the wafer resistor with defective inner electrodes 3 before printing the auxiliary electrode 7, a nickel layer and a tin layer will be synchronously deposited in the accommodating groove 10 when preparing the plating layer 9 later, so that the wafer resistor with defective inner electrodes 3 becomes a defective product with poor appearance and resistance value after preparation. Thus, it can be realized that in the follow-up, the wafer resistor with defective inner electrodes 3 can be screened out by any one of the appearance inspection methods of AOI or CCD, or it can also be selected to be screened out by measuring the resistance value, which is safe and reliable.

[0039] Based on the above structure and the manufacturing process of the chip resistor, this embodiment provides a method for screening defective resistors, which mainly includes the following steps:

[0040] Automatically optically inspect the chip resistor plate with the protective layer printed thereon to detect whether there are defects in the inner electrodes 3 of each chip resistor on the chip resistor plate;

[0041] If there are defects, cut a receiving groove 10 in the chip resistor with defects, so that the two inner electrodes 3 on the defective chip resistor are exposed in the receiving groove 10; when electroplating and depositing to form a nickel layer and a tin layer on the folded chip resistor, a conductive structure 11 will be deposited and formed in the receiving groove 10, and the conductive structure 11 is respectively connected to the two inner electrodes 3;

[0042] After the plating layer 9 is prepared and the finished chip resistors are obtained, the appearance of all the chip resistors is inspected by any one of the AOI or CCD appearance inspection methods or the resistance values of all the chip resistors are measured, and the chip resistors with defective appearances or abnormal resistance values are screened out, that is, the chip resistors provided with the defect detection structure, and then the chip resistors with defective inner electrodes 3 are removed.

[0043] Compared with the prior art, the inner electrode defect detection structure of the chip resistor and the method for screening defective resistors of the present application have at least one or more of the following beneficial effects:

[0044] The inner electrode defect detection structure of the chip resistor and the method for screening defective resistors of the present application set a receiving groove on the chip resistor with defective inner electrodes, and fill the receiving groove with a conductive material to make the two inner electrodes conduct, so that the appearance and resistance value of the defective chip resistor are both changed, becoming defective products in appearance and resistance value, and then the chip resistors with defective inner electrodes can be safely and reliably screened out through appearance inspection or resistance measurement; it realizes the destruction and removal of the chip resistors with defective inner electrodes one by one by the equipment without damaging the adjacent chip resistors, avoids the waste of labor and the risk of missed removal caused by manual removal, improves the product quality, and at the same time avoids the yield loss and resource waste caused by the whole-piece or whole-strip removal method, and saves the production cost.

[0045] In this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, including not only those elements listed, but also other elements not expressly listed.

[0046] In this document, the orientation terms such as front, rear, upper, and lower are defined based on the positions of the components in the drawings and their relative positions to each other, solely for the clarity and convenience of expressing the technical solution. It should be understood that the use of these orientation terms should not limit the scope of protection claimed in this application.

[0047] In the case of no conflict, the above-mentioned embodiments and the features in the embodiments in this document may be combined with each other.

[0048] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. An internal electrode defect detection structure for a chip resistor, the chip resistor comprising a substrate (1), two internal electrodes (3) spaced apart on one side of the substrate (1), a resistor layer (4) and a plurality of protective layers sequentially stacked and covering between the two internal electrodes (3), and an auxiliary electrode (7) disposed on the side of the internal electrode (3) away from the substrate (1), characterized in that, The internal electrode defect detection structure includes a receiving groove (10) and a conductive structure (11) disposed in the receiving groove (10). The receiving groove (10) is provided on the outer protective layer, and the receiving groove (10) sequentially penetrates through a plurality of the protective layers to the resistance layer (4). Both of the two internal electrodes (3) are exposed in the receiving groove (10), and the conductive structure (11) is respectively connected to the two internal electrodes (3). The receiving groove (10) is elongated. One end of the receiving groove (10) in the length direction extends to one of the internal electrodes (3), and the other end of the receiving groove (10) in the length direction extends to the other internal electrode (3). The conductive structure (11) includes a nickel layer and a tin layer.

2. The inner electrode defect detection structure of the chip resistor according to claim 1, characterized in that The length direction of the receiving groove (10) is consistent with the distribution direction of the internal electrodes (3); or There is a set angle between the length direction of the receiving groove (10) and the distribution direction of the internal electrodes (3).

3. The internal electrode defect detection structure of the chip resistor according to claim 1, characterized in that The receiving groove (10) is a curved elongated shape, a folded elongated shape, a straight elongated shape, or a combination of two or more of the foregoing shapes.

4. A screening method for defective resistance, characterized in that It includes the following steps: Automatically optically inspect the wafer resistor plate with the protective layer printed thereon to detect whether there are defects in the internal electrodes (3) of each wafer resistor on the wafer resistor plate; Set the defect detection structure as described in any one of claims 1-3 on the wafer resistor with defects; Conduct an appearance inspection or a resistance value measurement on all wafer resistors, and screen out the wafer resistors in which the internal electrodes (3) provided with the defect detection structure have defects.

5. The screening method for defective resistors according to claim 4, characterized in that, When setting the defect detection structure on the wafer resistor, first cut the receiving groove (10) on the defective wafer resistor with the protective layer printed on the wafer resistor plate, so that the two internal electrodes (3) on the defective wafer resistor are exposed in the receiving groove (10); Then, when electroplating and depositing to form a nickel layer and a tin layer on the folded wafer resistor, deposit a conductive structure (11) in the receiving groove (10), and the conductive structure (11) is respectively connected to the two internal electrodes (3).

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