Data circuitry for low-swing data bus

Abstract

This application relates to data circuitry for a low-swing data bus. A device may include a data bus that transmits data at a first voltage different from a second voltage associated with one or more components of a memory array. A transistor coupled to the data bus may receive the second voltage and transmit a third voltage. A first-in-first-out (FIFO) coupled to the transistor may receive the third voltage from the transistor. The FIFO circuitry may include one or more pre-charge components that drive the input voltage of the FIFO circuitry to the second voltage associated with the one or more components of the memory array based on the received third voltage.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 214,016, filed March 26, 2021, entitled “DATA CIRCUIT FOR A LOW SWING DATA BUS,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to data circuitry for low-swing data buses. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] An apparatus is described. The apparatus includes: a data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of a memory array; a transistor coupled to the data bus and configured to receive the first voltage from the data bus and transmit a third voltage; and a first-in, first-out (FIFO) circuit coupled to the transistor and configured to receive the third voltage from the transistor, the FIFO circuit including one or more pre-charge components configured to drive an input voltage of the FIFO circuit to the second voltage associated with the one or more components of the memory array, at least in part based on the received third voltage.

[0007] A method is described. The method includes: pre-charging a first-in-first-out (FIFO) circuit to a first voltage; receiving at the FIFO a second voltage associated with one or more components of a memory array and associated with a first logical state of memory cells in the memory array transmitted via a data bus based at least in part on pre-charging the FIFO to the first voltage; adjusting the FIFO circuit to the second voltage based at least in part on receiving the second voltage; after adjusting the FIFO circuit to the second voltage, pre-charging the FIFO to the first voltage; and receiving at the FIFO a third voltage associated with the one or more components of the memory array and associated with a second logical state of the memory cells transmitted via the data bus, wherein the third voltage is lower than the voltage associated with the second logical state.

[0008] An apparatus is described. The apparatus includes: a data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of a memory array; an nMOS transistor configured to receive the first voltage via the data bus and pull the first voltage down to a third voltage; and a first-in, first-out (FIFO) circuit coupled to the nMOS transistor and configured to receive the third voltage from the nMOS transistor, the FIFO including one or more pre-charge components configured to drive an input voltage of the FIFO to the second voltage associated with the one or more components of the memory array, at least in part based on the received third voltage. Attached Figure Description

[0009] Figure 1 Examples of systems supporting data circuitry for low-swing data buses are shown, based on the examples disclosed herein.

[0010] Figure 2 Examples of memory dies supporting data circuitry for low-swing data buses are shown, based on the examples disclosed herein.

[0011] Figure 3 Examples of circuits supporting data circuitry for low-swing data buses are shown, based on the examples disclosed herein.

[0012] Figure 4 Examples of timing diagrams supporting data circuitry for low-swing data buses are shown, based on the examples disclosed herein.

[0013] Figure 5 A block diagram is shown that supports a memory device for a low-swing data bus, according to an example disclosed herein.

[0014] Figure 6 The flowcharts shown illustrate one or more methods supporting data circuitry for low-swing data buses, based on the examples disclosed herein. Detailed Implementation

[0015] The system may include a memory device and a host device coupled to the memory device. In some instances, the host device may initiate an access operation (e.g., a read operation, a write operation) at the memory device. In such instances, the memory device may transfer data from a first location to a second location in response to receiving an access operation, and the memory device may transfer data via a bus. In some instances, the memory device may be a high-frequency bus system (e.g., a graphics system, such as a graphics dual data rate system). In some cases, when transferring data via the bus, the memory device may utilize a finite-swing signal to reduce current consumption. That is, the memory device may transfer data at a voltage lower than the voltage (e.g., full swing or full voltage) associated with one or more components of the memory array in the memory device, such as CMOS circuitry or peripheral components that process the data or perform digital computations. In such instances, the memory device may have to restore the finite swing on the bus to operate the CMOS circuitry, which may require relatively more power. For example, the memory device may transfer data from a first location to data circuitry, such as a first-in-first-out (FIFO) circuit, at the finite swing on the bus. In such instances, the memory device may need to return to its full swing voltage to process (e.g., perform) digital calculations on the received data at the FIFO. In some instances, returning a finite swing to its full swing may be difficult, such as in high-frequency bus systems. For example, returning a finite swing may require additional complex CMOS circuitry, and the memory device may consume more power and require more current to return to the finite swing than a memory device could achieve with a finite swing bus; for example, the additional CMOS circuitry may utilize relatively high power and current quantities. Improved swing operation of the data circuitry (e.g., the FIFO circuitry) is required.

[0016] As described herein, memory devices can utilize FIFO circuits with simple cell inputs (e.g., n-type metal-oxide-semiconductor transistors) and precharge the FIFO circuits to full swing voltage before receiving data. For example, in high-frequency systems (e.g., graphics systems, such as graphics dual data rate systems) that connect different regions of a chip (e.g., a memory device) over a distance (e.g., millimeter-scale distance), the memory device can utilize FIFO circuits to securely transmit data. Memory devices can also utilize FIFO circuits to correct propagation delays caused by locally different voltages and corresponding delays. For example, the FIFO can receive data from a first location having a first voltage and a first delay (e.g., a time scale or time domain) and from a second location having a second voltage and a second delay, and generate a propagation delay-corrected output. The FIFO circuit can receive data from a finite-swing bus. By utilizing simple cell inputs and precharging the FIFO described in this disclosure, the FIFO circuit can recover a full swing voltage (e.g., the voltage associated with one or more components of a memory array or VPERI) to process data. For example, the FIFO circuit can include one or more precharge components. Before the FIFO receives data, the memory system can precharge the FIFO circuit to its full swing voltage using a signal, and the finite swing in the FIFO circuit can be automatically restored. In such instances, the memory device can save current by using a finite swing bus while still processing data at the FIFO, among other benefits.

[0017] The features of this disclosure are initially referenced in the reference Figure 1 and 2 The system and bare die described herein are described in the context of the present disclosure. Features of this disclosure are described in the references. Figure 3 and 4 The circuitry and timing diagrams described herein are presented in the context of the circuitry and timing diagrams. These and other features of this disclosure are further illustrated by reference to... Figure 5 and 6 The device diagrams and flowcharts related to the data circuitry used for the low-swing data bus are described and referenced in the description.

[0018] Figure 1 An example of a system 100 supporting data circuitry for a low-swing data bus, as disclosed herein, is shown. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0019] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may represent aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0020] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet connection device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0021] Memory device 110 may be a separate device or component that can provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 may be used to store data for components of host device 105. In some instances, memory device 110 may act as a slave or dependent device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0023] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0024] Processor 125 may be used to provide control or other functions for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0025] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0026] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160a, memory die 160b, memory die 160N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one data bit. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0027] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0028] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components that can be used to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 capable of performing the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers that may be used to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0029] External memory controller 120 can be used to enable one or more of the following to be communicated between system 100 or a component of host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0030] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to act as part of a channel.

[0031] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0032] In some instances, memory device 110 may use a high-frequency bus system (e.g., a graphics system, such as a graphics dual data rate system, a system with a clock cycle of 500 picoseconds or less). In such instances, memory device 110 may utilize a FIFO to securely transfer data from a first area of ​​memory device 110 to a second area of ​​memory device 110, for example, from memory die 160-a to the FIFO. In some instances, memory device 110 may also utilize a finite-swing bus to transfer data; for example, memory device 110 may use a voltage lower than the voltage associated with other components of memory device 110 (e.g., full-swing voltage) to save power and current consumption. In some instances, memory device 110 may have to restore the finite swing to full swing to process the data and perform digital computations at the FIFO circuitry. In some cases, restoration may be difficult; for example, adding additional CMOS circuitry to restore the finite swing may consume more power and current.

[0033] As described herein, memory device 110 can utilize a simple cell FIFO circuit with pre-charge components. For example, the FIFO circuit may include one or more transistors (e.g., nMOS transistors) as inputs and one or more pre-charge components. Memory device 110 can pre-charge the FIFO to a full-swing voltage by transmitting signals to one or more pre-charge components. The FIFO can then receive, process, and store data; for example, based on pre-charging the FIFO circuit using one or more pre-charge devices, the finite-swing voltage can automatically recover to a full-swing voltage. In such examples, memory device 110 can utilize a finite-swing bus to reduce power and current consumption while still being able to process data at full swing at the FIFO, among other advantages.

[0034] Figure 2 An example of a memory die 200 supporting data circuitry for a low-swing data bus, as disclosed herein, is shown. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, memory cell 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference needed]. Figure 1The memory array 170 is described.

[0035] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be, for example, a cell board reference voltage Vpl, or ground, for example, Vss.

[0036] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern, such as a grid pattern. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0037] Read and write operations can be performed on memory cell 205 by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection by biasing word line 210 and digital line 215 (e.g., by applying a voltage to word line 210 or digital line 215). The intersection of word line 210 and digital line 215, arranged in a two-dimensional or three-dimensional configuration, can be referred to as the address of memory cell 205.

[0038] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital line 215 based on the received column addresses.

[0039] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and can be coupled to digital line 215 when switch assembly 235 is activated.

[0040] Sensing component 245 can be used to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or additionally convert the signal generated by accessing memory cell 205. Sensing component 245 can compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., provided to input / output component 255) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0041] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1 Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing components 245 may be located in the same location as local memory controller 260. Local memory controller 260 may be used to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of said one or more operations. Local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. Local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary, and may differ for the various operations discussed in the operational memory die 200.

[0042] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 260 in response to various access commands (e.g., from the host device 105) or otherwise coordinated. The local memory controller 260 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0043] FIFO 265 (e.g., FIFO cells 265-a and FIFO cells 265-b may be collectively referred to as FIFO 265) is configured to receive data from sensing component 245. It should be noted that the two FIFO cells shown (e.g., FIFO cells 265-a and FIFO cells 265-b) are for illustrative purposes only. That is, FIFO 265 may contain more than two FIFO cells (e.g., three, four, five, six, seven, eight, nine, or more FIFO cells). In some instances, FIFO 265 may be located within I / O 255. FIFO 265 is configured to receive data from one or more memory cells 205 in memory array 200. FIFO 265 can be used to correct for propagation delays associated with receiving data from different locations. For example, FIFO 265 may receive data from a first memory cell 205 having a first voltage and a first time delay, and from a second memory cell 205 having a second voltage and a second time delay. FIFO 265 can be configured to correct for propagation delays associated with receiving data from the first and second memory cells and outputting a data stream containing data from both the first and second memory cells. In some instances, a single FIFO cell (e.g., FIFO cell 265-a) can be selected to receive data based on the receipt of an input signal. For example, when an input signal is received at FIFO cell 265-a, data bus 280 can transmit data to FIFO cell 265-a at a limited-swing signaling or voltage (e.g., below the voltage used by FIFO cell 265-a to process data associated with logic state '1'). In some instances, a limited-swing voltage allows data bus 280 to transmit data at a voltage below the voltage used by the components of memory array 200 to process data (e.g., a full-swing voltage). For example, components of memory array 200 can use approximately 1.1 volts to process data associated with logic state '1'. In examples of finite-swing signaling, data bus 280 can transmit data associated with logic '1' at approximately 0.5 volts (e.g., at a finite-swing voltage below the full-swing voltage). Therefore, data bus 280 can transmit data in memory array 200 at voltages below the full-swing voltage to conserve current. In such examples, FIFO cell 265-a may need to recover the finite-swing voltage received from data bus 280 to the full-swing voltage used by FIFO cell 265-a to process data. In some examples, FIFO 265 can also output data on bus 290 to input / output 255; for example, FIFO cell 265-a can be selected based on a received output signal, and data can be output to bus 290. In some examples, bus 290 can also be a finite-swing bus.

[0044] As described herein, the local memory controller 260 may be configured to transmit a signal to FIFO unit 265-a or FIFO unit 265-b to activate one or more precharge components 270 before the respective FIFO unit 265 receives data. In such instances, one or more precharge components 270 may precharge the respective FIFO unit 265 to its full swing voltage (e.g., the voltage at which the respective FIFO unit 265 processes data). For example, FIFO unit 265-a may be precharged to its full swing voltage via precharge component 270-a. That is, precharging may refer to precharging one or more FIFO units 265 to their full voltage before receiving data at input 275. Furthermore, FIFO 265 may also include input 275 and output 285. In some instances, input 275 or output 285 may be located outside of FIFO 265; for example, input 275-a or output 285-a may be considered different from FIFO unit 265-a. In some instances, input 275-a can be an nMOS transistor, for example, a transistor that can pull down the received voltage instead of pulling it up. In such instances, FIFO cell 265-a can receive data from sensing component 245 from data bus 280 with a limited swing. Transistor input 275-a prevents voltage and power leakage from FIFO cell 265-a to data bus 280. In some instances, the gate of the nMOS transistor can be coupled to the input signal and select FIFO cell 265-a based on the received input signal. Alternatively, FIFO cell 265-a can be used to process data with a full swing based on pre-charge. If FIFO cell 265-a determines that the processed data is associated with logic '1', FIFO cell 265-a can maintain a high swing voltage. If FIFO cell 265-a determines that the processed data is associated with logic '0', FIFO cell 265-a can discharge to ground.

[0045] In some instances, FIFO 265 may also be configured to correct for propagation delays between data received from the first memory cell and data received from the second memory cell, and output the data to the local memory controller 260. In some instances, FIFO 265 may be associated with reading data. In other instances, FIFO 265 may be associated with writing data. For example, memory controller 260 may send data to input / output 255 and send data to sensing component 245 and memory cell 205 via FIFO 265.

[0046] Figure 3 An example of circuit 300 supporting data circuitry for a low-swing data bus, according to the examples disclosed herein, is shown. Circuit 300 may be as described in the reference. Figure 2An example of a described FIFO unit 265 (e.g., FIFO unit 265-a). Circuit 300 may include input 310 (e.g., as referenced). Figure 2 The input 275 is described. In some instances, input 310 may include transistor 315. Circuit 300 may include precharge components 320-a and 320-b (e.g., as referenced). Figure 2 The pre-charge component 270 is described. Circuit 300 may include logic 330-a and output 340 (e.g., as referenced). Figure 2 The output 285 is described. In some instances, circuit 300 can be drawn from a memory array (e.g., reference 285). Figure 2 The described memory array 200) or memory device (e.g., reference) Figure 1 The described memory device 110 receives data 305 at one or more locations. Circuit 300 can be connected to a high-frequency bus (e.g., as described in reference 110). Figure 2 The data bus 280 or data bus 290 described is coupled. In some instances, the bus can be as shown in the reference. Figure 1 and 2 The described finite swing bus.

[0047] Input 310 can be configured to receive data 305. In some instances, input 310 can receive data from a data bus coupled to input 310 (e.g., as referenced). Figure 1 The described data bus 280 receives data. In some instances, the data bus can operate at a low-swing voltage (e.g., at a first voltage below a second voltage (e.g., a full-swing voltage) associated with one or more components of the memory array). For example, the data bus can use a finite-swing voltage when transmitting data associated with a logic state (e.g., a value) '1'. In other instances, the data bus can be configured to transmit data at a third voltage when data is associated with a logic state '0' (e.g., a VSS voltage at or near ground). In some instances, input 310 can be configured to receive either a first voltage (e.g., a finite voltage) or a third voltage (e.g., a voltage at or near ground). In some instances, input 310 may include an nMOS transistor 315, and other options or combinations of components. In such instances, the nMOS transistor 315 can be configured to pull down the voltage associated with data 305; for example, the nMOS transistor 315 may not send a pull-up voltage (e.g., a full-swing voltage). In some instances, the nMOS transistor 315 can output a voltage that is the difference between the input voltage and the threshold voltage of the nMOS transistor 315. (See reference...) Figure 2 As described, each FIFO unit (e.g., each FIFO unit 265) can have 310 inputs. For example, as Figure 2As shown, one or more (e.g., several) additional parallel inputs 310 of other FIFO units can be connected in parallel with the input 310 of circuit 300. In such instances, each input 310 can be coupled to a different input signal, for example, as shown in the reference. Figure 2 The different input signals described. For example, input 310 of circuit 300 can be coupled to a first input signal (input 0), input 310 of a second FIFO unit can be coupled to a second input (input 1), and third input 310 of a third FIFO unit can be coupled to a third input (input 2). To select a corresponding input 310, circuit 300 can use an input pointer 350. For example, the gate of each nMOS transistor 315 can be coupled to the input pointer 350 configured to receive the corresponding input signal, and circuit 300 can apply a voltage to the input pointer 350 to activate the corresponding input 310 based on the selected FIFO unit, for example, when selecting circuit 300 (e.g., FIFO unit 265-a) in such a way... Figure 3 When the first input signal is received at the input pointer 350 shown, input 310 is activated.

[0048] Precharge components 320-a and 320-b may be configured to precharge circuit 300 to a second voltage (e.g., a full-swing voltage) based on received signal 325. In some instances, circuit 300 may be configured to process data associated with a corresponding logic state (e.g., logic state '1') at the second voltage. In such instances, circuit 300 may be configured to recover from a first voltage to a second voltage to process data. Therefore, circuit 300 may receive signal 325 (e.g., a precharge signal) at one or more precharge components (e.g., precharge components 320-a and 320-b). In some instances, circuit 300 may receive signal 325 before receiving data 305; for example, circuit 300 may precharge to the second voltage before receiving data 305. In one instance, precharge component 320-a may be a p-channel metal-oxide-semiconductor (e.g., pMOS) transistor. In such examples, precharge component 320-a may have a source coupled to the output of input 310 and a drain coupled to logic 330-b. The gate of precharge component 320-a may also receive a precharge signal 325. In one example, precharge component 320-b may be an nMOS transistor. In such examples, precharge component 320-b may have a source coupled to logic 330-b and a drain coupled to ground voltage (e.g., VSS). The gate of precharge component 320-b may receive a precharge signal 325. In other examples, precharge component 320-a or precharge component 320-b may be different types of transistors (e.g., p-type or n-type transistors) or other components, and coupled at different locations; for example, precharge component 320 may be any component that drives circuit 300 to a second voltage.

[0049] Logic 330-a and logic 330-b can be configured to store data 305, process data 305, or otherwise perform digital calculations on data 305. Output signals 345-a and 345-b are used to output data from circuit 300 (e.g., FIFO unit 265-a) at a controlled timing (e.g., a new timing different from the input timing) without any delay difference. In such instances, circuit 300 can store data at logic 330-a or logic 330-b until the data is transmitted to output 340. In some instances, logic 330-a and logic 330-b can process data 305 associated with logic state '1' at a second voltage and data 305 associated with logic state '0' at a third voltage; for example, logic 330-a or logic 330-b can store data associated with logic state '0' at or near ground (e.g., VSS). That is, as referenced... Figure 4 As described, circuit 300 can discharge the second voltage to the third voltage based on receiving data associated with logic state '0'.

[0050] Output 340 can be configured to output data 305. In some instances, such as the reference... Figure 2 As described, multiple outputs 340 may exist in parallel with circuit 300, for example, multiple outputs 340 for parallel connection of FIFO unit 265. To select a corresponding output 340, circuit 300 can use output pointers 345-a and 345-b. For example, circuit 300 can apply voltages to output pointers 345-a and 345-b to activate the corresponding output 340 based on the selected FIFO unit, for example, activation based on the selection of a first FIFO unit (e.g., FIFO unit 265-a). Figure 3 The output shown is 340.

[0051] In some instances, circuit 300 may include a pMOS transistor 315 at input 310 instead of an nMOS transistor. In such instances, the system can transmit data 305 via a data bus at both finite and full swing. For example, the data bus can transmit data 305 associated with logic '0' at a finite swing voltage and data 305 associated with logic '1' at full swing. In such instances, the bus can save power by reducing current consumption from half-swing to full swing compared to no swing (e.g., ground). Therefore, input 310 can receive a second voltage (e.g., the voltage associated with transmitting logic state '0'). The pMOS transistor 315 can pull up the second voltage instead of pulling down as described with reference to the nMOS transistor 315. Additionally, when circuit 300 utilizes the pMOS transistor 315, the pre-charge component 320 can instead discharge the component. That is, circuit 300 can process data 305 at a voltage (e.g., a third voltage) lower than the voltage associated with data 305 (e.g., the second voltage). Therefore, circuit 300 can discharge from the second voltage to the third voltage to process and / or store data 305 associated with logic '0'.

[0052] By utilizing input 310 and pre-charge component 320, circuit 300 can recover from a finite swing to a full swing to process data (e.g., from a first voltage to a second voltage) without requiring additional complex CMOS circuitry. In such instances, a system (e.g., system 100) can process and manipulate data 305 with power efficiency and concurrency by transmitting data via the data bus under finite swing signaling and recovering to a full swing. That is, nMOS transistor 315 prevents the voltage of circuit 300 (e.g., FIFO voltage) from leaking back to the data bus, thereby enabling the system to transmit data via the data bus under finite swing voltage and recover the full swing voltage of circuit 300 to process data.

[0053] Figure 4 An example of timing diagram 400 supporting data circuitry for a low-swing data bus, according to the examples disclosed herein, is shown. For example, timing diagram 400 may be shown as referenced... Figure 3 The circuit 300 and its components are described, and their operation is performed over a period of time. Timing diagram 400 shows circuit 300 receiving input pointer signal 405 (e.g., as shown in reference). Figure 3 The input signal at input pointer 350 is described), and the received data 420 (e.g., as referenced) Figure 3 The described data 305) and the received output signal 425 (e.g., as referenced) Figure 3 An example of the output signal 345 described. Timing diagram 400 may also show circuit 300 receiving precharge signal 410 (e.g., as shown in reference). Figure 3The precharge signal 325 is described. The timing diagram 400 may also show the voltage of the FIFO 415 (e.g., circuit 300) compared to the received data 420.

[0054] In some instances, circuit 300 can receive input pointer signal 405, such as Figure 4 As shown in the reference. Figure 3 As described, the corresponding FIFO unit (e.g., as referenced) Figure 2 The described FIFO cell 265-a) can be selected to receive data based on the input pointer signal 405 being in a high state. For example, when the nMOS transistor at the input of the FIFO cell (e.g., as referenced) Figure 3 When the input pointer signal 405-a is received at the gate of the nMOS transistor 315 (described input 310), the circuit 300 can be selected.

[0055] In some instances, circuit 300 can receive precharge signal 410 before receiving the corresponding input pointer signal 405. That is, as referenced Figure 3 As described, circuit 300 can receive data associated with logic state '1' from the data bus at a finite swing voltage (e.g., bus level 420-b voltage). In such instances, circuit 300 may need to recover from the finite swing to the full swing voltage (e.g., the voltage associated with processing data associated with logic state '1' of the FIFO circuit). That is, circuit 300 can utilize pre-charge to compensate the data bus with a finite swing voltage.

[0056] For example, circuit 300 may receive precharge signal 410 at time 425 (e.g., before receiving input pointer signal 405-b). Precharge signal 410 may activate one or more precharge components (e.g., as referenced). Figure 3The pre-charge component 320 described drives the voltage of circuit 300 to a first voltage (e.g., the FIFO 415 voltage can change from ground to a full-swing voltage). After pre-charging, circuit 300 can receive an input pointer signal 405-b. In some instances, after receiving the input pointer signal 405-b, circuit 300 can receive data 420-a. In some instances, data 420-a can be associated with logic state '0'. That is, the data bus (e.g., data bus 280) can transmit data 420-a at or near ground voltage (e.g., a second voltage). In such instances, circuit 300 can discharge the first voltage and adjust it to the second voltage (e.g., ground voltage VSS). Circuit 300 can process data 420-a at the second voltage and receive output 425-a and output data 420-a from circuit 300, for example, circuit 300 can read the first logic state '0' at least in part based on the pre-charging and discharging of the FIFO circuit.

[0057] Before receiving the input pointer signal 405-c and after receiving the output signal 425-a, circuit 300 may receive a second precharge signal 410. In some instances, in response to the second precharge signal 410, circuit 300 may activate one or more components and drive circuit 300 to a first voltage. After precharging, circuit 300 may receive the input pointer signal 405-c based on circuit 300 being selected to receive data. In some instances, circuit 300 may receive data 420-b after receiving the input pointer signal 405-c. For example, circuit 300 may receive data 420-b associated with logic state '1'. That is, the data bus may transmit data 420-b at a third voltage (e.g., a finite swing voltage) associated with transmitting data associated with logic '1'. In such instances, circuit 300 may maintain the first voltage; for example, the FIFO 415 voltage may be kept high at the first voltage. See reference... Figure 3 As described, circuit 300 may be based on an nMOS transistor at the input (e.g., input 310) of circuit 300 (e.g., as referenced). Figure 3 The described nMOS transistor 315 prevents current leakage from the first voltage to the data bus 280. In some instances, circuit 300 can maintain the first voltage to store data 420-b. Circuit 300 can process data 420-b under the first voltage and receive an output signal 425-b. For example, circuit 300 can read the first logic state '1' at least in part based on precharging and maintaining the first voltage at the FIFO circuit, and output data 420-b based on receiving the output signal 425-b.

[0058] In some instances, timing diagram 400 may show additional voltages on the bus and circuit 300 based on the receipt of additional input pointer signal 405. For example, the circuit may receive a precharge signal 410 before receiving input pointer signal 405-d. In some instances, for example, the circuit 300 may already be at a first voltage based on receiving and processing data 420-b. In such instances, FIFO 415 may remain at the first voltage based on the receipt of precharge signal 410. Based on the bus remaining at a third voltage, data 420-b may be associated with logic state '1'. Circuit 300 may discharge after receiving input signal pointer 405-e based on the receipt of data 420-c; for example, data 420-c received after input pointer signal 405-e may be associated with logic state '0' based on a second voltage (e.g., ground voltage) transmitted on the data bus. Then, circuit 300 may receive another precharge signal 410, precharging circuit 300 to a first voltage (e.g., FIFO 415 may be variable high), and not discharging based on the association of data 420-d with logic state '1' after receiving input pointer signal 405-f; for example, the data bus may transmit a third voltage. By precharging the FIFO circuit before each data reception, the memory device can utilize a finite swing voltage on the data bus and restore the finite swing voltage to the full swing at the FIFO circuit to process the data, for example, by discharging or maintaining the precharge voltage after receiving data 420.

[0059] Figure 5 A block diagram 500 illustrates a memory device 520 supporting data circuitry for a low-swing data bus, according to an example disclosed herein. The memory device 520 may be a reference... Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of components for performing various aspects of the data circuitry for a low-swing data bus as described herein. For example, memory device 520 may include a precharge component 525, a receiving component 530, a voltage regulation component 535, an operating component 540, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0060] The precharge component 525 may be configured or otherwise support components for precharging a first-in-first-out (FIFO) circuit to a first voltage. In some cases, the precharge component 525 may be configured or otherwise support components for precharging the FIFO to the first voltage after adjusting the FIFO circuit to a second voltage. In some cases, the precharge component 525 may be configured or otherwise support components for receiving a precharge signal, wherein precharging the FIFO circuit is at least partially based on receiving the precharge signal. In some instances, the precharge component 525 may be configured or otherwise support components for activating a first transistor coupled to the input of the FIFO to precharge the FIFO to the first voltage, at least partially based on receiving the precharge signal.

[0061] The receiving component 530 may be configured or otherwise support a component for receiving at the FIFO a second voltage associated with one or more components of the memory array and associated with a first logical state of memory cells in the memory array transmitted via a data bus based at least in part on precharging the FIFO to a first voltage. In some instances, the receiving component 530 may be configured or otherwise support a component for receiving at the FIFO a third voltage associated with one or more components of the memory array and associated with a second logical state of memory cells transmitted via a data bus, wherein the third voltage is lower than the voltage associated with the second logical state. In some cases, the receiving component 530 may be configured or otherwise support a component for receiving the voltage of the first logical state as the second voltage.

[0062] Voltage adjustment component 535 may be configured or otherwise support components for adjusting the FIFO circuit to a second voltage based at least in part on the receipt of a second voltage. In some cases, voltage adjustment component 535 may be configured or otherwise support components for maintaining a first voltage at the FIFO based at least in part on the receipt of a third voltage associated with a second logic state of the transfer memory cell, wherein maintaining the first voltage is associated with the second logic state of the storage memory cell.

[0063] In some cases, the operating component 540 may be configured or otherwise support the read of a first logical state received at least in part based on a precharge of the FIFO. In some instances, the operating component 540 may be configured or otherwise support the read of a second logical state received at least in part based on a precharge of the FIFO.

[0064] Figure 6The flowchart shown illustrates a method 600 for supporting data circuitry for a low-swing data bus, based on examples disclosed herein. Operation of method 600 can be implemented by a memory device or its components described herein. For example, it can be implemented by, as referenced... Figures 1 to 5 The described memory device performs the operations of method 600. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0065] At 605, the method may include pre-charging the FIFO cells of the First-In-First-Out (FIFO) circuit to a first voltage. That is, the method may include pre-charging the FIFO cells of the FIFO circuit (e.g., FIFO cell 265-a) to a first voltage. Operation of 605 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 605 may be described in reference to... Figure 5 The pre-charge component 525 described is implemented.

[0066] At 610, the method may include receiving at the FIFO a second voltage associated with one or more components of the memory array and associated with transmitting a first logic state of memory cells in the memory array via a data bus, at least in part based on pre-charging the FIFO to a first voltage. Operation of 610 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 610 may be described by reference to... Figure 5 The described receiving component 530 is executed.

[0067] In 615, the method may include adjusting the FIFO circuit to a second voltage based at least in part on the receipt of the second voltage. The operation of 615 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 615 may be described by reference. Figure 5 The voltage regulation component 535 described is implemented.

[0068] In 620, the method may include pre-charging the FIFO to the first voltage after adjusting the FIFO circuit to the second voltage. The operation of 620 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 620 may be described in reference to... Figure 5 The pre-charge component 525 described is implemented.

[0069] At 625, the method may include receiving at the FIFO a third voltage associated with one or more components of the memory array and associated with a second logic state of the memory cells transmitted via a data bus, wherein the third voltage is lower than the voltage associated with the second logic state. Operation of 625 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 625 may be described by reference to... Figure 5The described receiving component 530 is executed.

[0070] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: pre-charging a first-in-first-out (FIFO) circuitry to a first voltage; receiving at the FIFO a second voltage associated with one or more components of a memory array and associated with a first logical state of memory cells in the memory array transmitted via a data bus based at least in part on pre-charging the FIFO to the first voltage; adjusting the FIFO circuitry to the second voltage based at least in part on receiving the second voltage; pre-charging the FIFO to the first voltage after adjusting the FIFO circuitry to the second voltage; and receiving at the FIFO a third voltage associated with one or more components of the memory array and associated with the second logical state of memory cells transmitted via a data bus, wherein the third voltage is lower than the voltage associated with the second logical state.

[0071] Method 600 and some examples of the device described herein may further include operations, features, circuits, logic, components, or instructions for maintaining a first voltage at the FIFO, at least in part, based on receiving a third voltage associated with a second logic state of the transfer memory cell, wherein maintaining the first voltage may be associated with the second logic state of the storage memory cell.

[0072] Method 600 and some aspects of the device described herein may further include operations, features, circuits, logic, components, or instructions for receiving a precharge signal, wherein precharging of the FIFO circuitry may be based at least in part on receiving the precharge signal.

[0073] Method 600 and some examples of the devices described herein may further include operations, features, circuits, logic, components, or instructions for: activating a first transistor coupled to the input of the FIFO to precharge the FIFO to a first voltage, at least in part based on receiving a precharge signal.

[0074] Method 600 and some aspects of the device described herein may further include operations, features, circuits, logic, components, or instructions for: reading a first logic state received at least in part based on a precharge of the FIFO; and reading a second logic state received at least in part based on a precharge of the FIFO.

[0075] In some examples of method 600 and the device described herein, the voltage of the first logic state may be a second voltage.

[0076] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0077] An apparatus is described. The apparatus may include: a data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of a memory array; a transistor coupled to the data bus and configured to receive the first voltage from the data bus and transmit a third voltage; and a first-in, first-out (FIFO) circuit coupled to the transistor and configured to receive the third voltage from the transistor, the FIFO circuit including one or more pre-charge components configured to drive the input voltage of the FIFO circuit to the second voltage associated with one or more components of the memory array, at least in part based on the received third voltage.

[0078] In some cases, the device may include adjusting the second voltage to a fourth voltage associated with ground, at least in part, based on driving the input voltage to the second voltage.

[0079] In some cases, the device may include: receiving a precharge signal; and driving the input voltage of the FIFO circuit to a second voltage based at least in part on receiving the precharge signal.

[0080] In some instances, the device may include maintaining a second voltage associated with the logic state, at least in part, based on storing the logic state of the memory cell at a FIFO circuit.

[0081] In some cases of the device, the pre-charge component includes: a second transistor coupled to the transistor and a first voltage source, the second transistor being configured to drive the input voltage of the FIFO circuit based at least in part on a third voltage received from the transistor; and a third transistor coupled to the first voltage source.

[0082] In some cases of the device, the transistor may be an nMOS transistor and the first voltage may be lower than the second voltage.

[0083] In some cases of the device, the third voltage may be the difference between the first voltage and the threshold voltage of the nMOS transistor.

[0084] In some instances of the device, the transistor is a pMOS transistor and the first voltage may be higher than the second voltage.

[0085] In some examples, the device may include reducing the third voltage to the second voltage.

[0086] In some cases of the device, a second voltage associated with one or more components of the memory array may be associated with the logical state of a memory cell in the memory array.

[0087] Another device is described. The device may include: a data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of a memory array; an nMOS transistor configured to receive the first voltage via the data bus and pull the first voltage down to a third voltage; and a first-in-first-out (FIFO) circuit coupled to the nMOS transistor and configured to receive the third voltage from the nMOS transistor, the FIFO including one or more pre-charge components configured to drive the input voltage of the FIFO to the second voltage associated with one or more components of the memory array, at least in part based on the received third voltage.

[0088] In some instances, the device may include adjusting the second voltage to a fourth voltage associated with ground, at least in part, based on driving the input voltage to the second voltage.

[0089] In some instances of the device, the data bus may be further configured to transmit second data at a fourth voltage associated with one or more components of the memory array; the nMOS transistor may be configured to receive and transmit the fourth voltage via the data bus; and the FIFO circuit may be configured to adjust the second voltage to the fourth voltage at least in part based on the receipt of the fourth voltage.

[0090] In some cases of the device, one or more pre-charge components further include: a second transistor coupled to an nMOS transistor and a first voltage source, the second transistor being configured to drive the input voltage of the FIFO circuit based at least in part on a third voltage received from the nMOS transistor; and a third transistor coupled to the first voltage source.

[0091] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, which may have various bit widths.

[0092] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0093] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0094] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0095] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0096] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage higher than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage lower than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0097] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0098] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0099] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0100] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0101] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0102] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0103] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of the memory array, the first voltage being at least partially based on the logical state of the memory cells of the memory array; A transistor coupled to the data bus and configured to receive the data at the first voltage from the data bus and transmit the data at the third voltage; as well as A first-in-first-out (FIFO) circuit, coupled to the transistor and including one or more pre-charge components, the FIFO circuit being configured to: Receive the data at the third voltage from the transistor; Based at least in part on the data received at the third voltage, the input voltage of the FIFO circuit is driven to the second voltage associated with the one or more components of the memory array using the one or more pre-charge components; as well as The data is processed at least in part based on the logic state of the memory cell and the input voltage of the FIFO circuit is driven to the second voltage, at the second voltage or at a fourth voltage different from the second voltage.

2. The device according to claim 1, wherein the FIFO circuit is further configured to: At least in part, this is based on driving the input voltage to the second voltage and adjusting the second voltage to the fourth voltage, wherein the fourth voltage is associated with ground.

3. The device according to claim 1, wherein the FIFO circuit is further configured to: Receive precharge signal; and The input voltage of the FIFO circuit is driven to the second voltage, at least in part based on the receipt of the pre-charge signal.

4. The device according to claim 1, wherein the FIFO circuit is further configured to: The second voltage is maintained in association with the logic state by storing the logic state of the memory cells of the memory array at the FIFO circuit, at least in part.

5. The device according to claim 1, wherein the one or more pre-charging components comprise: A second transistor coupled to the transistor and a first voltage source, the second transistor being configured to drive the input voltage of the FIFO circuit based at least in part on the data received from the transistor at the third voltage; as well as The third transistor is coupled to the first voltage source.

6. The device of claim 1, wherein the transistor is an nMOS transistor and the first voltage is lower than the second voltage.

7. The device of claim 6, wherein the third voltage is the difference between the first voltage and the threshold voltage of the nMOS transistor.

8. The device of claim 1, wherein the transistor is a pMOS transistor and the first voltage is higher than the second voltage.

9. The device of claim 8, wherein, in order to drive the input voltage of the FIFO circuit, the one or more pre-charge components are configured to: The third voltage is reduced to the second voltage.

10. The device of claim 1, wherein the second voltage associated with one or more components of the memory array is associated with a second logic state of the memory cell of the memory array.

11. A method comprising: Precharge the first-in-first-out (FIFO) circuit to the first voltage; The FIFO circuit receives a second voltage associated with one or more components of the memory array and associated with transmitting a first logic state of the memory cells in the memory array via a data bus based at least in part on precharging the FIFO circuit to the first voltage. The FIFO circuit is adjusted to the second voltage, at least in part, based on the receipt of the second voltage; After adjusting the FIFO circuit to the second voltage, the FIFO circuit is pre-charged to the first voltage; and A third voltage is received at the FIFO circuit, which is associated with one or more components of the memory array and with a second logic state of the memory cell transmitted via the data bus, wherein the third voltage is lower than the voltage associated with the second logic state.

12. The method of claim 11, further comprising: The first voltage at the FIFO circuit is maintained at least in part based on the receipt of the third voltage associated with the transmission of the second logic state of the memory cell, wherein maintaining the first voltage is associated with storing the second logic state of the memory cell.

13. The method of claim 11, further comprising: A pre-charge signal is received, wherein the pre-charging of the FIFO circuit is at least partially based on the receipt of the pre-charge signal.

14. The method of claim 13, further comprising: At least in part based on receiving the precharge signal, a first transistor coupled to the input of the FIFO circuit is activated to precharge the FIFO circuit to the first voltage.

15. The method of claim 11, further comprising: Read the first logic state received at least in part based on the pre-charging of the FIFO circuit; as well as The second logic state is read based at least in part on the pre-charge of the FIFO circuit.

16. The method of claim 11, wherein the voltage of the first logic state is the second voltage.

17. An apparatus comprising: A data bus configured to transmit data at a first voltage different from a second voltage associated with one or more components of the memory array, the first voltage being at least partially based on the logical state of the memory cells of the memory array; An nMOS transistor is configured to receive the data at the first voltage via the data bus and pull the first voltage down to a third voltage; as well as A first-in-first-out (FIFO) circuit, coupled to the nMOS transistor and including one or more pre-charge components, the FIFO circuit being configured to: Receive the data at the third voltage from the nMOS transistor; The input voltage of the FIFO circuit is driven to the second voltage associated with one or more components of the memory array, at least in part based on the data received at the third voltage; as well as The data is processed at least in part based on the logic state of the memory cell, either at the second voltage or at a fourth voltage associated with ground.

18. The device of claim 17, wherein the FIFO circuit is further configured to: At least in part, this is based on driving the input voltage to the second voltage and adjusting the second voltage to the fourth voltage associated with the ground.

19. The apparatus according to claim 17, wherein: The data bus is further configured to transmit second data at a fourth voltage associated with one or more components of the memory array; The nMOS transistor is configured to receive and transmit the fourth voltage via the data bus; and The FIFO circuit is configured to adjust the second voltage to the fourth voltage based at least in part on the receipt of the fourth voltage.

20. The device of claim 17, wherein the one or more pre-charging components further comprise: A second transistor coupled to the nMOS transistor and a first voltage source, the second transistor being configured to drive the input voltage of the FIFO circuit based at least in part on the data received from the nMOS transistor at the third voltage; as well as The third transistor is coupled to the first voltage source.

Images