Potential read disturbance mitigation in memory devices

Abstract

A trigger condition associated with potential read disturbance mitigation in a memory device is detected. In response to detecting the trigger condition associated with potential read disturbance, one or more blocks of the memory device affected by the trigger condition are placed in a stable state to mitigate potential read disturbance in the one or more blocks.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to mitigating potential read interference in memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory components may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] This disclosure relates to a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: detecting a triggering condition associated with potential read interference in one or more blocks of the memory device; and, in response to detecting the triggering condition, placing one or more blocks of the memory device affected by the triggering condition into a stable state to mitigate potential read interference in the one or more blocks.

[0004] Another aspect of this disclosure relates to a method comprising: detecting, by means of a processing device, a triggering condition associated with potential read interference in one or more blocks of a memory device; and, in response to detecting the triggering condition, placing one or more blocks of the memory device affected by the triggering condition into a stable state by means of the processing device to mitigate potential read interference in one or more blocks.

[0005] Another aspect of this disclosure relates to a computer-readable storage medium including instructions that, when executed by a processing means, configure the processing means to perform operations including: detecting a triggering condition associated with potential read interference in one or more blocks of a memory means; and, in response to detecting the triggering condition, placing one or more blocks of the memory means affected by the triggering condition into a stable state to mitigate potential read interference in one or more blocks. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a data flow diagram illustrating the interactions between components of a memory subsystem when mitigating potential read interference mechanisms in a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 A flowchart illustrating an example method for mitigating potential read interference mechanisms in a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0011] Various aspects of this disclosure relate to mitigating potential read interference in a memory device within a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more components, such as memory devices for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0012] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. Data operations can be performed by the memory subsystem. Data operations can be initiated by the host. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on the memory device at the memory subsystem and to read data from the memory device at the memory subsystem.

[0013] Some memory devices (e.g., NAND memory devices) include arrays of memory cells (e.g., flash cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor based on the cell's logic value (e.g., 0 or 1). During a read operation, a read reference voltage is applied to the transistor, and if the read reference voltage is higher than the cell's threshold voltage, the transistor is programmed and identified by the memory subsystem as a binary value of 0. Memory cells in these devices can be grouped into pages that refer to logical cells of the memory device used for storing data. For some types of memory devices (e.g., NAND), pages are grouped to form blocks (also referred to herein as "memory blocks").

[0014] Background scan operations can run in the background of the memory subsystem (e.g., during an idle period when the memory subsystem is performing other operations and is not responding to a host start command). A memory device background scan can be initiated by reading a segment of the memory device (e.g., a codeword, block, or portion of a block). The background scan can track the number of bit corrections required to determine the quality of the memory segment. The background scan can also determine whether a segment is uncorrectable. The memory segment can be analyzed to determine metrics (e.g., the amount or type of error correction required, the estimated remaining lifetime, the number of cells operating below a threshold level, the segment being uncorrectable by the ECC engine, etc.). If the metric is above the threshold, the background scan can proceed to the next memory segment. If the metric is below the threshold, the background scan can attempt correction measures, for example, by performing a refresh relocation event on the memory segment or the memory portion associated with the memory segment. For example, if a portion of a block is read and determined to have a metric below the threshold, a refresh relocation event can be performed on the block containing the read portion.

[0015] NAND structures exhibit a unique inherent cell reliability degradation mechanism where reading NAND flash memory can cause neighboring cells within the same block to change over time. This is known as read disturbance. Latent Read Disturbance (LRD) is a read disturbance mechanism caused when there is a delay (e.g., around 10 seconds) between reads on the device. LRD is caused by the interaction between the floating body and the word line during the final stage of a multi-stage read operation in the memory device. After each read operation, the word line voltage slopes down to a specified voltage level (e.g., ground → 0V), and then the floating NAND channel couples down with the word line (0V → -4V), reaching a negative potential. The word line and floating NAND channel potentials follow, unless the floating channel discharges through the pillar junction, which can take several minutes depending on the NAND temperature. Therefore, the delay between two consecutive read operations will cause a low positive gate voltage to be applied to the NAND cell for an excessively long period, causing degradation of the NAND structure. For example, over several days, NAND cells may experience significant charge loss and charge gain due to this LRD mechanism.

[0016] Various aspects of this disclosure mitigate LRD in a memory device by placing a block into a stable state under certain conditions. No LRD occurs when a block is in a stable state. An LRD mitigation component of the memory subsystem monitors trigger conditions associated with the memory device, and when the LRD mitigation component detects a trigger condition associated with a block, it causes the block to transition to a stable state by providing a command to the memory device. The trigger condition indicates that the block is unlikely to be accessed (e.g., read) in the short term. As an example, detecting a trigger condition may include detecting a background scan being performed on the block (e.g., a background scan performing on a portion of the block, such as a page, or the entire block), detecting an impending power failure on the block, or detecting a power state transition of the block (e.g., if the device enters a low-power state with an expected long idle delay). Therefore, the LRD mitigation component may place the block into a stable state based on the LRD mitigation component detecting a background scan being performed on the block (e.g., a portion of the block, such as a page, or the entire block), based on the LRD mitigation component detecting an impending power failure affecting the block, or based on the LRD mitigation component detecting a power state transition of the block. In the example where the LRD mitigation component places a block into a stable state based on the detection of a background scan in progress, the LRD mitigation component places the block into a stable state before the background scan moves to another block.

[0017] By transitioning blocks to a steady state based on background scans, power-down events, and power state transitions, the LRD mitigation component alleviates the LRD effect caused by background scans. It also assists memory devices (e.g., mobile or client solid-state drives) that are regularly powered on only for a limited number of reads and are powered off or in a low-power state. This LRD mitigation technique also allows the memory subsystem the flexibility to choose between fast page scans and fast block scans.

[0018] Figure 1 This describes an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0023] Host system 120 may be coupled to memory subsystem 110 via a host interface. Examples of host interfaces include, but are not limited to, SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, DIMM interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional (3D) crosspoint memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0026] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] While non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include ROM for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and ECC, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0032] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0033] The memory subsystem 110 also includes a background scan component 114 responsible for managing and performing background scans on memory devices 130 and 140. During a background scan, the background scan component 114 reads data from a portion (e.g., a page, block, or portion of a block) of one of the memory devices 130 or 140 to determine metrics (e.g., the amount or type of error correction required, the estimated remaining lifetime, the number of cells operating below a threshold level, and the segment being uncorrectable by the ECC engine), and if the metric is below the threshold, performs a correction action via the memory subsystem controller 115, such as by performing a refresh relocation event on the portion of the memory device from which data is read. When performing a background scan, the background scan component 114 may scan a single block or a portion thereof, or may move from one block to another while scanning portions of each block. That is, consistent with some embodiments, a background scan may include scanning the first page in the first block before scanning the second page in the second block, and so on.

[0034] The memory subsystem further includes a Potential Read Disturbance (LRD) mitigation component 113 to mitigate LRD mechanisms caused by system workloads and background scans performed by the background scan component 114 at memory devices 130 and 140. To reduce the impact of LRD mechanisms, the LRD mitigation component 113 can transition a block in one of the memory devices 130 or 140 to a steady state under certain conditions. No LRD occurs when the block is in a steady state. The LRD mitigation component 113 can transition a block to a steady state at any time when it is unlikely that the block will be read soon. For example, the LRD mitigation component 113 can place the block in a steady state in response to the detection of triggering conditions, such as a background scan being performed on the block, a power state transition of the block, or the detection of an impending power outage event.

[0035] In some embodiments, the memory subsystem controller 115 includes at least a portion of the LRD mitigation component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the LRD mitigation component 113 is part of a host system 120, an application, or an operating system. In some embodiments, the local media controller 135 includes at least a portion of the LRD mitigation component 113.

[0036] Figure 2 This is a data flow diagram illustrating the interactions between components of a memory subsystem during adaptive background scanning, according to some embodiments of the present disclosure. Figure 2 In the example described herein, memory device 130 is a NAND memory device comprising multiple memory blocks.

[0037] As shown, NAND block 200 comprises an array (2D or 3D) of pages (rows) and strings (columns). Each NAND cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor based on the cell's logic value (e.g., 0 or 1). Strings are connected within NAND block 200 to allow data to be stored and retrieved from selected cells. NAND cells in the same column are connected in series to form a bit line (BL). All cells in a bit line are connected to a common ground at one end and to a common sense amplifier at the other end for reading the threshold voltage of one of the cells when decoding data. NAND cells are horizontally connected to word lines (WL) at their control gates to form pages. A page is a collection of connected cells sharing the same word line and is the smallest unit of programming.

[0038] At 202, the LRD mitigation component 113 detects a trigger condition for transitioning block 200 to a stable state. Detecting the trigger condition may include detecting a background scan being performed on block 200 or detecting an impending power outage on block 200. Therefore, the LRD mitigation component 113 may detect the trigger condition based on a signal received from memory device 130 indicating an impending power outage event or power state transition, or based on an identifier of a block to which a background scan has been performed, received from background scan component 114. In some examples, detecting a background scan being performed on block 200 includes detecting a background scan being performed on pages of block 200.

[0039] In response to the detection of a trigger condition, LRD mitigation component 113 (at 204) places block 200 in a stable state in which no LRD occurs. To place block 200 in a stable state, LRD mitigation component 113 issues one or more commands to memory device 130 causing block 200 to transition to a stable state. For example, LRD mitigation component 113 may send a reset command (e.g., a body reset command) to memory device 130, causing memory device 130 to transition block 200 to a stable state by grounding word lines in block 200 rather than grounding or floating them. In the example where LRD mitigation component 113 places block 200 in a stable state based on the detection of a background scan being performed on a page of block 200, LRD mitigation component 113 places block 200 in a stable state before the background scan moves to another page in another block.

[0040] Figure 3This is a flowchart illustrating an example method 300 for mitigating potential read interference mechanisms in a memory device (e.g., memory subsystem 110) according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The LRD mitigation component 113 is executed. Although the processes are shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0041] At operation 305, the processing device detects a trigger condition. In some examples, the trigger condition may indicate that one or more programmed blocks in the memory device are unlikely to be accessed within a prolonged time period. For example, as shown, detecting the trigger condition may include: detecting a background scan being performed on one or more programmed blocks (305A), detecting an impending power failure on one or more programmed blocks (305B), or detecting a power state transition on one or more programmed blocks (e.g., when one or more programmed blocks are placed in a low power state). To detect a background scan, the processing device may monitor the background scan performed by the background scan component, for example, by routinely accessing error event data generated by the background scan component to indicate the result of the background scan. Detection of a background scan being performed may include detecting a background scan being performed on a portion of a block, such as a background scan being performed on a page of the block. The processing device may detect an impending power failure or power state transition based on a signal received from the memory device indicating that a power failure event is imminent or a power state transition has occurred.

[0042] At operation 310, the processing device places one or more blocks into a stable state based on the detection of a trigger condition. To place one or more blocks into a stable state, the processing device sends a command. For example, the processing device may send a main reset command to the memory device. The command provided by the processing device causes the memory device to transition one or more blocks to a stable state by grounding (rather than floating) the word lines of one or more blocks. The processing device places one or more blocks into a stable state to mitigate potential read interference within one or more blocks. In the example where the processing device places a block into a stable state based on the detection of a background scan being performed on a page within the block, the processing device places the block into a stable state before the background scan moves to another block.

[0043] In the process of bringing one or more blocks to a stable state, the processing device may bring a subset of the programmed blocks in the memory device (e.g., a subset of the programmed blocks for which a background scan is performed) to a stable state, or the processing device may bring the entire set of programmed blocks in the memory device to a stable state (e.g., based on the detection of an impending power outage affecting the entire set of blocks in the memory device).

[0044] Implementations of the described subject matter may include one or more of the features described herein, either individually or in combination.

[0045] Example 1 is a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: detecting a trigger condition associated with potential read interference in the memory device; and, in response to detecting the trigger condition, placing one or more blocks of the memory device affected by the trigger condition into a stable state to mitigate potential read interference in the one or more blocks.

[0046] Example 2 includes the system according to Example 1, wherein the detection of the triggering condition includes detecting a background scan being performed on the one or more blocks.

[0047] Example 3 includes a system according to any one or more of Examples 1 or 2, wherein detecting the background scan being performed on the one or more blocks includes detecting the background scan being performed on a page in one of the one or more blocks.

[0048] Example 4 includes a system according to any one or more of Examples 1 to 3, wherein the detection of the triggering condition includes detecting an impending power failure event at the memory device.

[0049] Example 5 includes a system according to any one or more of Examples 1 to 4, wherein the detection of the triggering condition includes detecting a power state transition of the one or more blocks.

[0050] Example 6 includes a system according to any one or more of Examples 1 to 5, wherein placing the one or more blocks of the memory device into the stable state includes sending a command to the memory device to ground the word lines in the one or more blocks.

[0051] Example 7 includes a system according to any one or more of Examples 1 to 6, wherein: the memory device includes a set of blocks; and placing the one or more blocks of the memory device into the stable state includes placing the set of blocks into the stable state based on detecting the trigger condition.

[0052] Example 8 is a method comprising: detecting, by means of a processing device, a triggering condition associated with potential read interference in a memory device; and, in response to detecting the triggering condition, placing one or more blocks of the memory device affected by the triggering condition into a stable state by means of the processing device to mitigate potential read interference in the one or more blocks.

[0053] Example 9 includes the method according to Example 8, wherein the detection of the triggering condition includes detecting a background scan being performed on the one or more blocks.

[0054] Example 10 includes the method according to any one or more of Examples 8 or 9, wherein the detection of the triggering condition includes one of the following: detecting an impending power failure event at the memory device; and detecting a power state transition of the one or more blocks.

[0055] Example 11 includes the method according to any one or more of Examples 8 to 10, wherein placing the one or more blocks of the memory device into the stable state includes sending a command to the memory device.

[0056] Example 12 includes the method according to any one or more of Examples 8 to 11, wherein the command causes the memory device to ground the word lines in the one or more blocks.

[0057] Example 13 includes the method according to any one or more of Examples 8 to 12, wherein: the memory device includes a set of blocks; and placing the one or more blocks of the memory device into the stable state includes placing the set of blocks into the stable state based on detecting the trigger condition.

[0058] Example 14 includes the method according to any one or more of Examples 8 to 13, wherein: the memory device includes a set of blocks; and placing the one or more blocks of the memory device into the stable state includes placing a subset of blocks from the set of blocks into the stable state based on detecting the triggering condition.

[0059] Example 15 is a computer-readable storage medium including instructions that, when executed by a processing device, configure the processing device to perform operations including: detecting a trigger condition associated with potential read interference in the memory device; and, in response to detecting the trigger condition, placing one or more blocks of the memory device affected by the trigger condition into a stable state to mitigate potential read interference in the one or more blocks.

[0060] Example 16 includes a computer-readable medium according to Example 15, wherein the detection of the triggering condition includes detecting a background scan being performed on the one or more blocks.

[0061] Example 17 includes a computer-readable medium according to any one or more of Examples 15 or 16, wherein the detection of the triggering condition includes detecting an impending power-off event at the memory device.

[0062] Example 18 includes a computer-readable medium according to any one or more of Examples 15 to 17, wherein placing the one or more blocks of the memory device into the stable state includes sending a command to the memory device.

[0063] Example 19 includes a computer-readable medium according to any one or more of Examples 15 to 18, wherein the command causes the memory device to ground word lines in the one or more blocks.

[0064] Example 20 includes a computer-readable medium according to any one or more of Examples 15 to 19, wherein: the memory device includes a set of blocks; and placing the one or more blocks of the memory device into the stable state includes placing the set of blocks into the stable state based on detecting the triggering condition.

[0065] Figure 4 This describes an instance machine in the form of a computer system 400, within which an instruction set can be executed such that the machine performs any or more of the methods discussed herein. Figure 4 This describes an example machine of computer system 400, within which an executable instruction set is provided to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to execute commands corresponding to...). Figure 1 (Operation of LRD mitigation component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0066] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0067] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM), a static memory 406 (e.g., flash memory, static random access memory (SRAM) such as SRAM), and a data storage system 418, which communicate with each other via a bus 430.

[0068] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 402 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include network interface device 408 for communication on network 420.

[0069] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) storing one or more instruction sets 426 or software embodying any or more of the methods or functions described herein. Instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution by computer system 400, the main memory 404 and processing device 402 also constituting machine-readable storage medium. Machine-readable storage medium 424, data storage system 418 and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0070] In one embodiment, instruction 426 includes instructions for implementing a data destruction component (e.g., Figure 1The LRD mitigation component 113) contains functional instructions. Although the machine-readable storage medium 424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0071] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm here is, and generally is, considered a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0072] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0073] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), ROM, RAM, EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to execute the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0075] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes, for example, ROM, RAM, disk storage media, optical storage media, flash memory components, and other machine-readable (e.g., computer-readable) storage media.

[0076] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: a memory device; and a processing device operably coupled with the memory device to perform operations comprising: detecting, by the processing device, a power state transition of a block of the memory device based on receiving a signal from the memory device, the signal indicating that the block is in a low power state based on an anticipated idle of the block; and in response to detecting the power state transition of the block, placing the block of the memory device in a stabilization state to mitigate potential read disturbance in the block, placing the block in the stabilization state comprising sending a command to the memory device that causes the memory device to ground a word line in the block.

2. The system of claim 1, wherein: the block is a first block; and the operations further comprise: detecting that a background scan is being performed on a second block; and in response to detecting that the background scan is being performed on the second block, placing the second block in a stabilization state.

3. The system of claim 2, wherein detecting that the background scan is being performed on the second block comprises detecting that a background scan is being performed on a page in the second block.

4. The system of claim 1, wherein: the block is a first block; and the operations further comprise: detecting an impending power down event at the memory device; and in response to detecting the impending power down event, placing a second block in a stabilization state.

5. The system of claim 4, wherein: the signal is a first signal; detecting the impending power down event is based on receiving a second signal indicating that a power down of the memory device is impending.

6. The system of claim 1, wherein the word line in the block is floating prior to being grounded.

7. The system of claim 1, wherein: the memory device comprises a set of blocks; and the placing the block of the memory device in the stabilization state comprises placing the set of blocks in the stabilization state based on detecting the power state transition.

8. A method comprising: detecting, by a processing device, a power state transition of a block of a memory device based on receiving a signal from the memory device, the signal indicating that the block is in a low power state based on an anticipated idle of the block; and in response to detecting the power state transition of the block, placing the block of the memory device in a stabilization state by the processing device to mitigate potential read disturbance in the block, placing the block in the stabilization state comprising sending a command to the memory device that causes the memory device to ground a word line in the block.

9. The method of claim 8, wherein: the block is a first block; and the method further comprises: detecting that a background scan is being performed on a second block; and in response to detecting that the background scan is being performed on the second block, placing the second block in a stabilization state.

10. The method of claim 9, wherein detecting that the background scan is being performed on the second block comprises accessing error event data. ​ ​ ​ 11. The method of claim 8, wherein the word lines in the block are floating prior to being grounded.

12. The method of claim 8, wherein the memory device grounds the word lines in the block in response to the command.

13. The method of claim 8, wherein: the memory device comprises a set of blocks; and the placing the block of the memory device in the stable state comprises placing the set of blocks in the stable state.

14. The method of claim 8, wherein: the memory device comprises a set of blocks; and the placing the block of the memory device in the stable state comprises placing a subset of blocks from the set of blocks in the stable state.

15. A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: detecting a power state transition of a block of a memory device based on receiving a signal from the memory device, the signal indicating that the block is in a low power state based on an expected idle of the block; and in response to detecting the power state transition of the block, placing the block in a stable state to mitigate potential read disturbance in the block, the placing the block in the stable state comprising sending a command to the memory device that causes the memory device to ground word lines in the block.

16. The computer-readable storage medium of claim 15, wherein: the block is a first block; and the operations further comprise: detecting that a background scan is being performed on a second block; and in response to detecting that the background scan is being performed on the second block, placing the second block in a stable state.

17. The computer-readable storage medium of claim 16, wherein detecting that the background scan is being performed on the second block comprises accessing error event data.

18. The computer-readable storage medium of claim 15, wherein the word lines in the block are floating prior to being grounded.

19. The computer-readable storage medium of claim 15, wherein: the memory device comprises a set of blocks; and the placing the block of the memory device in the stable state comprises placing the set of blocks in the stable state.

20. The computer-readable storage medium of claim 15, wherein: the memory device comprises a set of blocks; and the placing the block of the memory device in the stable state comprises placing a subset of blocks from the set of blocks in the stable state. ​

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