Method for controlling in-furnace uniformity of polysilicon layer

Abstract

The application discloses a method for controlling the uniformity of a polysilicon layer in a furnace, comprising the following steps: placing a plurality of substrates in a polysilicon deposition furnace, and at least distributing the substrates at the furnace mouth and the furnace tail; adjusting the conditions in the polysilicon deposition furnace to polysilicon deposition conditions, introducing a gaseous polysilicon precursor into the polysilicon deposition furnace in a way that the gaseous polysilicon precursor is introduced from both ends of the furnace mouth and the furnace tail at the same time to react and deposit, and forming a polysilicon layer on the surface of the P+ channel and the connecting region; at least measuring the thickness of the polysilicon layer formed at the furnace mouth and the furnace tail and obtaining a uniformity value in the furnace, and when the uniformity value of the polysilicon layer thickness in the furnace is greater than a predetermined value T, performing a temperature rising treatment on the furnace tail or a temperature falling treatment on the furnace mouth. The control method can obviously improve the performance stability of the polysilicon field plate in the mass production process, thereby improving the yield, the yield rate and reducing the cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor power devices, and particularly relates to a furnace uniformity control method for a polysilicon layer. BACKGROUND

[0002] Fast Recovery Diode (FRD) is a new type of power device in recent years, and is one of the most used power semiconductor devices in power electronic devices. Due to its good switching performance, short reverse recovery time, large forward current, small size, simple installation and other advantages, it is often used in parallel with three-terminal power switching devices (such as IGBT) in power electronic circuits, as a high-frequency, large-current freewheeling diode or rectifier tube, and has great development prospects and market demand. The continuous development of power electronic technology and consumer electronics technology has opened up a wide range of application fields for semiconductor power devices, and the controllable characteristics of semiconductor power devices determine the efficiency, size and weight of power electronic and consumer electronic systems. With the rapid growth of power electronics and consumer electronics, people's demand for cost reduction is becoming higher and higher.

[0003] Polysilicon field plate is one of the important devices of semiconductor power devices including fast recovery diode, and has an important influence on the performance of semiconductor power devices including fast recovery diode. For example, the polysilicon functional layer (POLY layer) contained in the existing polysilicon field plate is generally a non-doped polysilicon (UPOLY) structure. After the polysilicon film layer is deposited, phosphorus element doping + high-temperature annealing of impurities is performed through POCI3 pre-expansion to improve the conductive properties of the film layer.

[0004] In actual application, it is found that the non-doped polysilicon (UPOLY) structure is used as the polysilicon functional layer, although the surface concentration can be improved by POCI3 pre-expansion to improve the conductive properties of the film layer, but since the polysilicon film layer is relatively thick, about 5000A, the doped impurities cannot actually penetrate to the bottom of the film layer, and only a very thin conductive modified layer is formed on the surface or surface layer, thereby resulting in low conductive properties. This directly leads to the fact that the electric field effect of the existing polysilicon field plate is not ideal.

[0005] In addition, in the actual production process, the furnace uniformity of the polysilicon layer thickness in mass production of the polysilicon field plate often fails to meet the requirements, so that the stability of the mass-produced polysilicon field plate is difficult to guarantee. This becomes one of the important factors restricting the mass production of the polysilicon field plate, and also increases the difficulty of cost control. SUMMARY

[0006] The purpose of the embodiments of the present application is to overcome the above-mentioned deficiencies of the prior art, provide a furnace uniformity control method for a polysilicon layer, which can effectively ensure that the furnace uniformity of the polysilicon layer thickness of a polysilicon field plate in the mass production process meets the mass production requirements, thereby effectively solving the technical problem of the instability of the polysilicon field plate in the mass production process.

[0007] In order to achieve the above-mentioned application purposes, the present application provides a furnace uniformity control method for a polysilicon layer. The furnace uniformity control method for a polysilicon layer of the present application comprises the following steps:

[0008] A plurality of substrates are placed in a polysilicon deposition furnace, and at least are distributed at the furnace mouth and the furnace tail in the furnace; wherein the substrate is provided with a connection area and a P+ ring area, the P+ ring area comprises a plurality of isolation islands, each isolation island is in a frame type and is combined on the surface of the substrate, a plurality of the isolation islands are distributed at intervals, and sequentially enclose the connection area; a frame type P+ channel is formed between two adjacent isolation islands;

[0009] The conditions in the polysilicon deposition furnace are adjusted to polysilicon deposition conditions, and a gaseous polysilicon precursor is introduced into the polysilicon deposition furnace in a way of simultaneously gasifying from both ends of the furnace mouth and the furnace tail to react and deposit, thereby forming a polysilicon layer on the surface including the P+ channel and the connection area;

[0010] At least the thickness of the polysilicon layer formed at the furnace mouth and the furnace tail is measured to obtain a furnace uniformity value, and when the furnace uniformity value of the polysilicon layer thickness is greater than a predetermined value T, the furnace tail is subjected to a temperature rising treatment or the furnace mouth is subjected to a temperature dropping treatment.

[0011] Compared with the prior art, the present application has the following technical effects:

[0012] The furnace uniformity control method for a polysilicon layer of the present application can ensure that the polysilicon layer grown in situ on each substrate is uniform and high in thickness, that is, the furnace uniformity value of each polysilicon layer thickness is small, thereby significantly improving the performance stability of the polysilicon field plate in the mass production process, thereby improving the yield rate of the polysilicon field plate, effectively improving the yield of the polysilicon field plate and reducing the cost of the polysilicon field plate. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0014] Figure 1 A top view structural schematic diagram of a polysilicon field plate structure of an embodiment of the present application;

[0015] Figure 2 A top view structural schematic diagram of a polysilicon field plate structure of an embodiment of the present application; Figure 1 A structural schematic diagram of a cross section along AA' in the embodiment;

[0016] Figure 3 A top view structural schematic diagram of a polysilicon field plate structure of an embodiment of the present application; Figure 1 A top view structural schematic diagram of a polysilicon field plate structure of an embodiment of the present application; Figure 2 A structural schematic diagram of a cross section along AA' in the embodiment; A structural schematic diagram of a cross section along AA' in the embodiment;

[0017] A structural schematic diagram of a cross section along AA' in the embodiment; Figure 4 A structural schematic diagram of a cross section along AA' in the embodiment; A structural schematic diagram of a cross section along AA' in the embodiment;

[0018] A structural schematic diagram of a cross section along AA' in the embodiment; Figure 5 A process flow schematic diagram of a polysilicon field plate preparation method of an embodiment of the present application. A process flow schematic diagram of a polysilicon field plate preparation method of an embodiment of the present application.

[0019] A process flow schematic diagram of a polysilicon field plate preparation method of an embodiment of the present application. Figure 6 A process flow schematic diagram of a polysilicon field plate preparation method of an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved in the present application more clear and understandable, the present application will be further described in detail below in combination with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0021] In the present application, the term "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects.

[0022] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of single item or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can mean a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0023] It should be understood that in various embodiments of the present application, the size of the sequence number of the above processes does not mean the order of execution, and part or all of the steps can be executed in parallel or in sequence, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0024] The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the description of the embodiments of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] The weight of the related components mentioned in the embodiments of the present application can not only refer to the specific content of each component, but also represent the proportional relationship between the weights of each component. Therefore, as long as the content of the related components in the embodiments of the present application is proportionally enlarged or reduced, it is within the scope disclosed in the embodiments of the present application. Specifically, the mass mentioned in the embodiments of the present application can be μg, mg, g, kg, and other mass units commonly known in the chemical industry.

[0026] The terms "first", "second", "third" and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily described in a chronological manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are not to be construed as specific to any particular embodiments of the application. For example, a first item discussed below could be termed a second item; likewise, a second item could be termed a first item without departing from the scope of the present application. As such, the terms "first", "second", "third", and the like are used herein, merely for purposes of nomenclature.

[0027] In the process of mass production, the thickness of the deposited polysilicon layer of the existing polysilicon field plate is difficult to control in the furnace, resulting in that the thickness of the polysilicon layer is not uniform in the furnace, so that the corresponding performance of the polysilicon field plate produced in the same furnace, such as the electric field effect, is unstable, thereby resulting in that the yield of the mass production of the polysilicon field plate is not high, and the cost is increased. Therefore, the embodiments of the present application propose the following scheme.

[0028] The following explanations of related professional terms are given:

[0029] Furnace uniformity: In the process of mass production of the thickness of the polysilicon layer, the same furnace contains a plurality of substrates to be deposited and grown with polysilicon layers, and the plurality of substrates are synchronously deposited with polysilicon. The uniformity of the thickness of the polysilicon layer contained in each substrate is also called inter-wafer uniformity, which is relative to the intra-wafer uniformity.

[0030] Polysilicon field plate: The polysilicon field plate of the present application can be an existing polysilicon field plate, that is, a polysilicon field plate containing a single undoped polysilicon layer, or a polysilicon field plate containing a composite polysilicon layer as shown in the embodiments and Figures 1 to 5 Figure 3 The composite polysilicon layer includes a doped polysilicon layer / undoped polysilicon layer / conductive modification layer which are sequentially stacked and combined as shown in the embodiments.

[0031] ​The embodiment of the present application provides a furnace uniformity control method of a polysilicon layer. The furnace uniformity control method of the polysilicon layer comprises the following steps as shown in the figure Figure 6 .

[0032] (1) Placing a plurality of substrates in a polysilicon deposition furnace, and at least distributing at the furnace mouth and the furnace tail; wherein, the substrate is provided with a connection area and a P+ ring area, the P+ ring area comprises a plurality of isolated islands, each isolated island is in a frame type and is combined on the surface of the substrate, the plurality of isolated islands are distributed at intervals and sequentially enclose the connection area; a frame type P+ channel is formed between the adjacent two isolated islands;

[0033] (2) Adjusting the condition in the polysilicon deposition furnace to a polysilicon deposition condition, introducing a gaseous polysilicon precursor into the polysilicon deposition furnace in a way of simultaneously gasifying from both ends of the furnace mouth and the furnace tail to react and deposit, and forming a polysilicon layer on the surface including the P+ channel and the connection area;

[0034] (3) Measuring the thickness of the polysilicon layer formed at least at the furnace mouth and the furnace tail and obtaining a furnace uniformity value, when the furnace uniformity value of the polysilicon layer thickness is greater than a predetermined value T, performing a temperature rising treatment on the furnace tail or a temperature falling treatment on the furnace mouth.

[0035] Wherein, the substrate in step (1) is a substrate to be formed with a polysilicon layer in a polysilicon field plate process, therefore, the connection area and the P+ ring area provided on the substrate are as shown in the polysilicon field plate of each embodiment and Figures 1 to 5 as shown below. Figure 1 Figure 2 Figure 3 and Figure 2 , wherein, the functional layer structure contained in the connection area 3 is as shown in Figure 4 , comprising a functional layer 31, a P+ layer 32 and an N+ layer 33 connected in sequence. The polysilicon field plate of the embodiment of the present application and the substrate in step (1) are as shown below, and the polysilicon field plate and the substrate in step (1) are not described here to save space.

[0036] In step (2), the polysilicon deposition furnace can be an existing polysilicon deposition furnace, which is different from the existing one in that the polysilicon deposition furnace should have an air inlet for air inletting at both ends of the furnace mouth and the furnace tail, such as a polysilicon deposition furnace provided with a diffusion tube, so as to realize air inletting in a way of air inletting at both ends, thereby improving the uniformity of the thickness of the polysilicon layer contained in different substrates and reducing the size of the furnace uniformity value of the thickness of the polysilicon layer.

[0037] ​​The polycrystalline silicon deposition furnace in step (2) is adjusted to polycrystalline silicon deposition conditions, which can be the first reaction conditions for depositing a doped polycrystalline silicon layer in step S02 below. It can also be the second reaction conditions for depositing a non-doped polycrystalline silicon layer in step S03.

[0038] The polycrystalline silicon layer is deposited in step (2) to serve as a sample for testing the furnace uniformity value in step (3) to obtain furnace uniformity value data.

[0039] In the embodiment, the polycrystalline silicon deposition conditions in step (2) further include a temperature gradient zone in the polycrystalline silicon deposition furnace. By setting the temperature gradient zone, the uniformity of the thickness of the polycrystalline silicon layer deposited on each substrate is improved.

[0040] The temperature gradient zone can include a furnace mouth temperature zone, a furnace middle temperature zone, and a furnace tail temperature zone, and the temperature of the furnace mouth temperature zone can be controlled to be higher than the temperature of the furnace tail temperature zone, and the temperature of the furnace tail temperature zone can be controlled to be higher than the temperature of the furnace middle temperature zone. The temperature in the temperature gradient zone is set to include three temperature zones to improve the uniformity of the thickness of the deposited polycrystalline silicon layer, including the uniformity of the thickness between wafers and the uniformity of the thickness within a wafer.

[0041] In the embodiment, the method of introducing gaseous polycrystalline silicon precursor into the polycrystalline silicon deposition furnace in step (2) from both ends of the furnace mouth and the furnace tail at the same time can be realized by a diffusion pipe provided in the polycrystalline silicon deposition furnace, that is, the polycrystalline silicon precursor is introduced into the polycrystalline silicon deposition furnace from both ends of the diffusion pipe.

[0042] In addition, the type of gaseous polycrystalline silicon precursor introduced in step (2) determines the type of polycrystalline silicon layer deposited, such as when the introduced gaseous polycrystalline silicon precursor is a non-doped polycrystalline silicon precursor, then the deposited polycrystalline silicon layer is a non-doped polycrystalline silicon; when the introduced gaseous polycrystalline silicon precursor includes a dopant element precursor and a polycrystalline silicon precursor, then the deposited polycrystalline silicon layer is a doped polycrystalline silicon; when the doped polycrystalline silicon layer is first introduced, and then a non-doped polycrystalline silicon precursor is introduced, then the deposited polycrystalline silicon layer is a composite polycrystalline silicon layer, such as the composite polycrystalline silicon layer shown in Figure 3

[0043] When the polycrystalline silicon layer formed in step (2) includes a doped polycrystalline silicon layer and a non-doped polycrystalline silicon layer stacked and combined with the doped polycrystalline silicon layer, that is, a composite polycrystalline silicon layer including a doped polycrystalline silicon layer / non-doped polycrystalline silicon layer, the method of introducing gaseous polycrystalline silicon precursor into the polycrystalline silicon deposition furnace for reaction in step (2) includes the following steps:

[0044] ​a: The gaseous doped element precursor and the first polycrystalline silicon precursor are simultaneously introduced into the polycrystalline silicon deposition furnace from both ends of the furnace mouth and furnace tail to form a mixed gas and carry out the first chemical reaction and deposition, forming a doped polycrystalline silicon layer on the surface including the P+ channel and the connection region.

[0045] b: After vacuuming and N2 purging in the polysilicon deposition furnace, the gaseous second polysilicon precursor is introduced into the polysilicon deposition furnace for a second chemical reaction and deposition, forming an undoped polysilicon layer on the surface of the doped polysilicon layer.

[0046] The doped polycrystalline silicon layer formed in step a can be referred to in the following text. Figure 5 The preparation method of the crystalline silicon field plate shown in step S02 is carried out, and the conditions can also be set and adjusted according to the conditions in step S02 below.

[0047] The undoped polysilicon layer formed in step b can be referred to in the following text. Figure 5 The preparation method of the crystalline silicon field plate shown in step S03 is carried out, and the conditions can also be set and adjusted according to the conditions in step S03 below.

[0048] In step (3), the polysilicon layer thickness can be measured according to industry standard methods. Due to the characteristics of polysilicon deposition furnaces, special gases are generally introduced from the furnace opening, and the furnace is evacuated. Therefore, in actual polysilicon layer deposition, there are often differences in the uniformity of the deposited film thickness within the furnace (between wafers). Therefore, when sampling substrate samples from inside the furnace, the substrate samples should at least include the substrates at the furnace opening and the furnace tail after polysilicon deposition. This ensures the rationality and representativeness of the test samples, thereby improving the reference value of the furnace uniformity value of the polysilicon layer thickness. The furnace uniformity value of the polysilicon layer thickness can be calculated or tested according to the existing furnace uniformity value calculation method for film thickness.

[0049] Because the polysilicon deposition furnace operates by continuously drawing a vacuum pump from the furnace tail, there is a certain degree of loss of gas atmosphere at the furnace tail. Therefore, the measured furnace uniformity value for the polysilicon layer thickness is often higher than the predetermined value T. Thus, when the measured furnace uniformity value for the polysilicon layer thickness is greater than the predetermined value T, it indicates that there are differences in the inter-wafer thickness of the polysilicon layers deposited on each substrate. This directly leads to unstable performance, such as electric field effects, in polysilicon field panels produced in the same furnace, resulting in a low yield. In this case, the embodiments of this application employ either heating the furnace tail to compensate for the temperature at the furnace tail, or cooling the furnace opening to indirectly compensate for the temperature at the furnace tail, thereby improving the uniformity of the inter-wafer thickness of the polysilicon layers deposited on each substrate and reducing the furnace uniformity value. The predetermined value T can be set according to the quality requirements of mass production; for example, in this embodiment, the furnace uniformity value is set to 5%.

[0050] In the embodiment, the temperature adjustment in step (3) can be performed at a ramping rate until the furnace uniformity value of the polysilicon layer thickness is less than or equal to a predetermined value T:

[0051] Specifically, the temperature adjustment of 0.5-2°C, particularly 1°C, can be performed twice to form a polysilicon layer and to measure the polysilicon layer thickness formed by the polysilicon layer forming process and to obtain a second furnace uniformity value. The polysilicon layer forming process and the furnace uniformity value obtaining process are repeated until the last obtained furnace uniformity value is less than or equal to the predetermined value T.

[0052] In a further embodiment, when the temperature difference between the temperature at the furnace tail and the temperature at the furnace mouth reaches 10-20°C, particularly up to 20°C, specifically, the temperature at the furnace tail is higher than the temperature at the furnace mouth by 10-20°C, particularly up to 20°C, the temperature adjustment in step (3) is stopped and the flow rate of the polysilicon precursor introduced is adjusted.

[0053] The stop of the temperature adjustment in step (3) and the adjustment of the flow rate of the polysilicon precursor introduced are performed according to a method comprising the following steps:

[0054] c: comparing the polysilicon layer thickness at the furnace mouth and the furnace tail;

[0055] d: increasing the flow rate of the polysilicon precursor introduced at the place where the polysilicon layer thickness is relatively small until the furnace uniformity value of the polysilicon layer thickness is less than or equal to the predetermined value T.

[0056] The polysilicon layer thickness at the furnace mouth and the furnace tail in step c refers to the polysilicon layer thickness formed last when the temperature difference between the temperature at the furnace tail and the temperature at the furnace mouth reaches 10-20°C.

[0057] The increase of the flow rate of the polysilicon precursor introduced at the place where the polysilicon layer thickness is relatively small in step d refers to: when the polysilicon layer thickness formed at the furnace mouth is less than the polysilicon layer thickness formed at the furnace tail, increasing the flow rate of the polysilicon precursor introduced at the furnace mouth; when the polysilicon layer thickness formed at the furnace mouth is higher than the polysilicon layer thickness formed at the furnace tail, increasing the flow rate of the polysilicon precursor introduced at the furnace tail.

[0058] The adjustment of the flow rate of the polysilicon precursor introduced is performed by a repair scheme for the temperature adjustment of the polysilicon layer deposition at the furnace mouth and the furnace tail.

[0059] Therefore, the in-furnace uniformity control method of the polycrystalline silicon layer can ensure that the thickness uniformity between polycrystalline silicon wafers can be effectively adjusted when the polycrystalline silicon layer is in-situ grown on a plurality of substrates in batches, and the in-furnace uniformity value of the thickness of each polycrystalline silicon layer is small, and is not higher than 5%. The thickness uniformity between polycrystalline silicon wafers is high, and the in-wafer thickness uniformity of a single polycrystalline silicon layer is higher, and the in-wafer uniformity value of the thickness of each polycrystalline silicon layer is smaller, such as not higher than 3%. Therefore, the in-furnace uniformity control method of the polycrystalline silicon layer can obviously improve the performance stability of the polycrystalline silicon field plate in the mass production process, thereby improving the yield rate of the polycrystalline silicon field plate, effectively improving the yield of the polycrystalline silicon field plate, and reducing the cost of the polycrystalline silicon field plate.

[0060] The polycrystalline silicon field plate in the in-furnace uniformity control method of the polycrystalline silicon layer can specifically include a substrate, and the substrate is provided with a connection region and a P+ ring region.

[0061] The P+ ring region surrounds the connection region, and specifically includes a plurality of isolation islands. Each isolation island is in a frame type and is combined on the surface of the substrate. The plurality of isolation islands are distributed at intervals and surround the connection region in sequence. A frame type P+ channel is formed between adjacent two isolation islands, and the frame type P+ channel is filled with a polycrystalline silicon layer. Figure 1 and Figure 2 As shown in the structure of the polycrystalline silicon field plate in the embodiment of the present application, the substrate 1 is provided with the P+ ring region 2 and the connection region 3. The P+ ring region 2 is arranged to surround the connection region 3. The P+ ring region 2 specifically includes a plurality of isolation islands 21, such as isolation island 211, isolation island 212, isolation island 213 and isolation island 214. Each isolation island is in a frame type and is combined on the surface of the substrate 1. The plurality of isolation islands 21, such as isolation island 211, isolation island 212, isolation island 213 and isolation island 214, are distributed at intervals and surround the connection region 3 in sequence. A frame type P+ channel 22 is formed between adjacent two isolation islands 21, such as a frame type P+ channel 221 formed between isolation island 211 and isolation island 212, a frame type P+ channel 222 formed between isolation island 212 and isolation island 213, and a frame type P+ channel 223 formed between isolation island 213 and isolation island 214. Each P+ channel 22, such as P+ channel 221, P+ channel 222 and P+ channel 223, is filled with a polycrystalline silicon layer 23. Since each P+ channel 22 is in a frame type, the polycrystalline silicon layer 23 filled in each frame type P+ channel 22 is also in a frame type corresponding to the appearance of each P+ channel 22, and each polycrystalline silicon layer 23 is arranged on the surface of the substrate 1 to surround the connection region 3 in sequence, like each isolation island 21, such as isolation island 211, isolation island 212, isolation island 213 and isolation island 214.

[0062] Figure 1 and Figure 2The polycrystalline silicon field plate shown is merely one example of a polycrystalline silicon field plate in the embodiments of this application. Of course, the polycrystalline silicon field plate in the embodiments of this application can also be... Figure 1 and Figure 2 The structure shown may be a variation or other structure. Regardless of the structure of the polysilicon field plate in the embodiments of this application, as an embodiment of this application, the polysilicon layer filled in the P+ channel is a composite polysilicon layer. That is, the polysilicon contained in the polysilicon field plate mentioned above is ideally a composite polysilicon layer relative to a single layer of polysilicon, as specifically as follows: Figure 1 and Figure 2 The polysilicon layers 23 filling each P+ channel 22, specifically those filling P+ channels 221, 222, and 223, are composite polysilicon layers. The structure of this composite polysilicon layer is as follows: Figure 3 As shown, it includes a doped polysilicon layer 231 and an undoped polysilicon layer 232 stacked and bonded to the doped polysilicon layer 231, and a conductive modification layer 233 bonded to the surface of the undoped polysilicon layer 232 away from the doped polysilicon layer 231. That is, the composite polysilicon layer includes a doped polysilicon layer 231, an undoped polysilicon layer 232, and a conductive modification layer 233 stacked sequentially. The doped polysilicon layer 231 is bonded to the bottom of the P+ channel 21, specifically, the doped polysilicon layer 231 is bonded to the surface of the bottom substrate 1 of the P+ channel 21. The polysilicon layer 23 in the polysilicon field plate of this application embodiment includes a doped polysilicon layer 231 and an undoped polysilicon layer 232 stacked together, and together with the conductive modification layer 233, forms a composite polysilicon layer structure. Each layer can play a role in enhancing conductivity, thereby significantly improving the conductivity of the polysilicon layer 23. In this way, the polysilicon field plate of this application embodiment is endowed with a high electric field effect, and the electric field effect of the polysilicon field plate of this application embodiment is broadened.

[0063] In the embodiment, the thickness of the doped polysilicon layer 231 contained in the composite polysilicon layer 23 can be controlled to be 2000-2500 A, and specifically can be 2500 A; the doping amount of the doping element contained in the doped polysilicon layer 231 can be the doping amount formed by introducing the doping element precursor and the polysilicon precursor into the deposition cavity at a rate ratio of 10-20:(100-200) sccm. In a specific embodiment, the doping element contained in the doped polysilicon layer includes at least one of P, B, and As. By controlling and adjusting the thickness of the doped polysilicon layer 231, the type and content of the doping element, the conductive performance of the doped polysilicon layer 231 can be improved, thereby improving the conductive synergistic effect between the doped polysilicon layer 231 and the undoped polysilicon layer 232 and the conductive modification layer 233, and improving the conductive performance of the composite polysilicon layer. The thickness of the doped polysilicon layer 231 can be theoretically increased, but for the consideration of the preparation process efficiency and cost, the thickness is relatively ideal in the above range. In the embodiment, the doping element contained in the doped polysilicon layer 231 is distributed in the surface layer and the interior of the doped polysilicon layer 231, that is, uniformly doped and distributed in the doped polysilicon layer 231. The uniform doping can be formed by in-situ doping and deposition of the doping element and silicon as described below.

[0064] In the embodiment, the thickness of the undoped polysilicon layer 232 can be 2000-3000 A, and specifically can be 2000 A. Due to the presence of the doped polysilicon layer 231, the thickness of the undoped polysilicon layer 232 can be significantly reduced compared with the thickness (5000 A) of the conventional single-layer polysilicon layer, and the thickness controlled in the range can improve the conductive synergistic effect between the layers contained in the composite polysilicon layer.

[0065] In the embodiment, the surface sheet resistance of the conductive modification layer 233 can be 11±3 Ω / □. The conductive modification layer 233 can be formed by depositing POCl3 on the surface of the undoped polysilicon layer and then annealing. Specifically, the conductive modification layer 233 can be formed according to the existing method of forming a single-layer polysilicon layer doped and modified by POCl3.

[0066] In addition, the width of the polysilicon layer 23, that is, the composite polysilicon layer, filled in each P+ channel 22, such as the P+ channel 221, the P+ channel 222, and the P+ channel 223, is 3.0-4.0 μm, that is, the width of each P+ channel is 3.0-4.0 μm. Therefore, the composite polysilicon layer is fully laid and filled according to the width of each P+ channel 22.

[0067] In the polysilicon field plate of each of the above embodiments, a connecting layer is further combined on the surface of each polysilicon layer, and an electrode is further arranged on the connecting layer, and the electrode combined on the connecting layer is in contact with each isolation island, specifically as Figure 4As shown, a connecting layer 25 is also combined with the surface of each polysilicon layer 23, and an electrode 4 is also arranged on the connecting layer 25, and the electrode 4 combined with the connecting layer 25 is in contact with each isolation island 21. The connecting layer 25 and the electrode 4 can be the connecting layer and the electrode contained in the existing polysilicon field plate, for example, the connecting layer 25 can be formed by doping B element and Pt element, and is arranged to enhance the connectivity between the electrode and the polysilicon layer 23, such as to enhance the conductivity of the connection between the two. The electrode 4 can be aluminum metal.

[0068] The width of each P+ channel 22, such as P+ channel 221, P+ channel 222, and P+ channel 223, contained in the P+ ring region 2 contained in each of the above-mentioned embodiments of the polysilicon field plate is consistent with the width of the above-mentioned polysilicon layer 23 filled therein. The height of each isolation island 21, such as isolation island 211, isolation island 212, isolation island 213, and isolation island 214, can be 2.0-2.5 μm, and the width can be 20-35 μm. In the embodiments, the width of each isolation island 21 is different, for example, the width difference of any two of the isolation islands 21 is 4.0-5.0 μm, and in specific embodiments, the width of the isolation island 211, the isolation island 212, and the isolation island 213 is 20 μm, 28 μm, and 32 μm, respectively. By arranging the width of each isolation island 21, the spacing of the polysilicon layer filled in each P+ channel 21 is indirectly controlled, so as to adjust and improve the performance of the electric field effect of the polysilicon field plate. In specific embodiments, the material of the isolation island 21 can be SiO2.

[0069] The substrate 1 contained in each of the above-mentioned embodiments of the polysilicon field plate can be a silicon substrate. In the substrate 1, and in the region opposite to each P+ channel 22, such as P+ channel 221, P+ channel 222, and P+ channel 223, a first P+ layer 24, such as the first P+ layer 241 and the first P+ layer 242, is also arranged. Figure 2 and Figure 4 Since the first P+ layer 24 is arranged in the region opposite to each P+ channel 22, such as P+ channel 221, P+ channel 222, and P+ channel 223, the first P+ layer 24 is formed by a plurality of intervals, and the number is equal to the number of P+ channels 22.

[0070] The connecting region contained in the polysilicon field plate of the embodiments of the present application is surrounded by the P+ ring region in each of the above-mentioned embodiments, and can include, for example, Figure 2 and Figure 4The structure shown is as follows: the connection region 3 is surrounded by the P+ ring region 2 in the above embodiments, and includes a connection functional layer 31 stacked on the surface of the substrate 1. From the connection functional layer 31 towards the interior of the substrate 1, it also includes P+ layers 32 and N+ layers 33 distributed sequentially. The P+ layers 32 and N+ layers 33 are distributed inside the substrate 1. The connection functional layer 31 enhances the connectivity between the electrode 4 and the connection region 3, such as enhancing the conductivity of the connection. The thickness and material of the connection functional layer 31 can be the same as the thickness and material of the connection layer 25 in the P+ ring region 2. The P+ layer 32 can be formed using a boron-doped substrate 1, and it can be at the same depth in the substrate 1 as the first P+ layer 24. The N+ layer 33 can be formed using a p-doped substrate 1. Of course, the connection region included in the polycrystalline silicon field plate of this application embodiment can be an existing polycrystalline silicon field plate connection region, or it can be an improved structure based on the functional layers included in the existing polycrystalline silicon field plate connection region.

[0071] in addition, Figure 2 and Figure 4 As shown, the surface of the connection region is covered with an electrode 4, that is, the electrode 4 contained in the polycrystalline silicon field plate of this application embodiment is simultaneously covered on the surface of the P+ ring region 2 and the connection region 3.

[0072] Furthermore, for the polycrystalline silicon field plate of this application embodiment, before its application in a semiconductor power device, a protective layer (not shown) is also covered on the outer surface of the electrode 4. This protective layer protects the electrode 4 and other components from oxidation or contamination by other impurities during storage, transportation, etc.

[0073] Based on the structure of the polycrystalline silicon field plate in the above embodiments, by setting the polycrystalline silicon layer contained therein as a composite polycrystalline silicon layer, specifically by setting it as a composite layer consisting of doped polycrystalline silicon layers and undoped polycrystalline silicon layers stacked together, each layer plays a role in enhancing conductivity, significantly improving the conductivity of the composite polycrystalline silicon layer, giving it good conductivity, thereby improving and broadening the electric field effect of the polycrystalline silicon field plate.

[0074] The above text contains Figure 3 Taking the composite polycrystalline silicon layer shown above as an example, the process flow diagram of the polycrystalline silicon field plate preparation method containing the composite polycrystalline silicon layer is as follows: Figure 5 As shown, combined with Figures 1 to 4 The method for preparing a polycrystalline silicon field plate containing a composite polycrystalline silicon layer according to embodiments of this application includes the following steps:

[0075] S01: A substrate 1 containing isolation islands is provided. A connection region 3 and a P+ ring region 2 are provided on the substrate. The P+ ring region 2 includes a plurality of isolation islands 21. Each isolation island 21 is frame-shaped and bonded to the surface of the substrate 1. The plurality of isolation islands 21 are distributed at intervals and sequentially surround the connection region 3. A frame-shaped P+ channel 22 is formed between two adjacent isolation islands 21.

[0076] S02: forming a doped polysilicon layer on the surface of the P+ channel 22 and the connecting region 3;

[0077] S03: forming an undoped polysilicon layer on the surface of the doped polysilicon layer 231 away from the substrate 1;

[0078] S04: forming a conductive modification layer on the outer surface of the undoped polysilicon layer;

[0079] S05: retaining the doped polysilicon layer, the undoped polysilicon layer and the conductive modification layer formed in the P+ channel, and removing the doped polysilicon layer, the undoped polysilicon layer and the conductive modification layer formed in the remaining region.

[0080] In the step S01, the substrate of the isolation island is the single substrate in step (1) of the furnace uniformity control method of the polysilicon layer described above.

[0081] In the single substrate, the substrate and the connecting region and the P+ ring region provided on the substrate are the same as the substrate, the connecting region and the P+ ring region contained in the polysilicon field plate of the embodiment of the application described above, and are specifically the substrate 1, the connecting region 3 and the P+ ring region 2 in Figure 1 、 Figure 2 and Figure 4 , wherein the functional layer structure contained in the connecting region 3 is also as shown in Figure 2 and Figure 4 , which comprises the functional layer 31, the P+ layer 32 and the N+ layer 33 connected in sequence.

[0082] The single substrate in S01 can be prepared according to the process steps shown in Figure 5 a figure to j figure. In the process step shown in b figure, the epitaxial wafer shown in a figure is subjected to oxidation treatment to form a SiO2 layer on its surface; in the process step shown in d figure, the SiO2 layer is subjected to etching treatment to form the P+ ring region 2 and the epitaxial wafer substrate region for forming the connecting region 3. Among them, the P+ ring region 2 contains a plurality of isolation islands 21 spaced from each other and a P+ channel 22 formed by two adjacent isolation islands 21; in the process step shown in f figure, the exposed epitaxial wafer substrate region for forming the connecting region 3 is subjected to N injection, which can specifically use P injection; in the process step shown in h figure, the N injection is subjected to push joint to form the N+ layer 33; in the process step shown in j figure, the B injection is subjected to push joint to form the P+ layer 32. Figure 5 The process conditions and the like in a figure to j figure in

[0083] In S02, the doped polysilicon layer formed in the P+ channel 22 can be formed according to the method of forming a doped polysilicon layer in steps (2) and (3) of the above furnace uniformity control method of a polysilicon layer, specifically, forming a doped polysilicon layer 231 as in Figure 3

[0084] Since the overall area of a general polysilicon field plate is small, the area of a single P+ channel 22 contained therein is even smaller. Therefore, in S02, the doped polysilicon layer is integrally formed on the overall surface of the substrate in S01 to improve the efficiency of forming the doped polysilicon layer. In step (1) of the above furnace uniformity control method of a polysilicon layer, a plurality of substrates are placed in the polysilicon deposition furnace at the same time. In this step S02, the doped polysilicon layer is formed on a single substrate, and is also formed on a plurality of substrates at the same time. In order to achieve the inter-wafer thickness uniformity of the polysilicon layer to meet the requirements of mass production, the above requirement that the furnace uniformity value of the thickness of the polysilicon layer is not higher than a predetermined value T, specifically, not higher than 5%, is achieved by using the above furnace uniformity control method of a polysilicon layer to control the deposition method of the doped polysilicon layer, so that the furnace uniformity value of the thickness of the polysilicon layer in mass production meets the requirement that it is not higher than a predetermined value T, specifically, not higher than 5%.

[0085] In the embodiment, the method of forming a doped polysilicon layer on the surface of the P+ channel 22 and the connection region includes the following steps:

[0086] The gaseous doped element precursor and the first polysilicon precursor are introduced into the deposition cavity to form a mixed gas and undergo a first chemical reaction, thereby in-situ depositing and forming a doped polysilicon layer on the surface of the P+ channel 22 and the connection region.

[0087] In the method, the gaseous doped element precursor and the first polysilicon precursor are introduced into the deposition cavity to form a mixed gas, which can make the doped precursor and the first polysilicon precursor form a uniform mixed gas, so that they react together, thereby realizing in-situ doping and synchronous deposition of the doped element, and enabling the doped element to be uniformly distributed in the interior and surface layer of the doped polysilicon layer.

[0088] ​In the embodiment, the doped element precursor and the first polysilicon precursor are continuously introduced into the deposition cavity in the form of gas flow to perform the first chemical reaction. The continuous introduction of the two precursors into the deposition cavity can effectively ensure the concentration of the two precursors in the deposition cavity, thereby ensuring the efficiency of the first chemical reaction and improving the deposition efficiency of the doped polysilicon layer. At the same time, the concentration ratio of the two precursors can be effectively ensured, and the doped element can be uniformly distributed in the doped polysilicon layer to improve the performance of the doped polysilicon layer. In the embodiment, the doped element precursor and the first polysilicon precursor can be introduced into the deposition cavity at a rate ratio of 10-20 sccm: 100-200 sccm, specifically 20 sccm: 200 sccm. The rate ratio can effectively maintain the concentration and ratio of the two precursors in the deposition cavity, thereby effectively improving the deposition rate of the doped polysilicon layer and the uniformity of the doped element doping. In order to further improve the uniformity of the mixing and dispersion of the doped element precursor and the first polysilicon precursor in the deposition cavity and the uniformity of the film thickness between the wafers in the mass production process, the doped element precursor and the first polysilicon precursor are introduced in the form of two-end gas, such as through a diffuser.

[0089] The conditions of the first chemical reaction should at least enable the doped element precursor and the first polysilicon precursor to react to generate a doped impurity and silicon, respectively. In the embodiment, the temperature of the first chemical reaction can be 600-650°C, and the time can be 1-4 hours; the vacuum pressure value in the deposition cavity can be 200-300 MT. By controlling and optimizing the conditions of the first chemical reaction, the efficiency of depositing the doped polysilicon layer can be adjusted, and the thickness of the doped polysilicon layer can be adjusted. For example, the thickness of the doped polysilicon layer can be controlled within the thickness range of the doped polysilicon layer 231.

[0090] In a specific embodiment, the doped element precursor can include at least one of PH3, B2H6, and AsH3, and the first polysilicon precursor can include SiH4 or a mixed gas of SiH4 and N2. When the doped element precursor is PH3 and the first polysilicon precursor is SiH4, the two react under the conditions of the first chemical reaction described above, in which SiH4 is thermally decomposed into polysilicon at high temperature and is deposited; at the same time, PH3 is decomposed into phosphorus and hydrogen: 2PH3=2P+3H2, and the phosphorus in-situ dopes the polysilicon while the polysilicon is deposited, generating a phosphorus-doped doped polysilicon layer.

[0091] In a specific embodiment, the above chemical deposition method is adopted and the conditions of the first chemical reaction are controlled as follows: PH3 is used as the doping element precursor, SiH4 is used as the first polysilicon precursor, the first chemical reaction is carried out in the reaction furnace through the diffusion pipe to introduce the reaction furnace, and the entire surface of the substrate in step S01 is integrally in-situ doped and deposited to form a doped polysilicon layer. The following embodiments 1 to 5 are specifically designed, and 9 parallel samples are prepared, wherein embodiments 1 to 4 are doped polysilicon layers formed by depositing under the conditions of step (2) of the furnace uniformity control method of the polysilicon layer of the present application. Embodiment 5 is a doped polysilicon layer formed by depositing under the conditions set after the temperature reduction treatment of the furnace port in step (3) of the furnace uniformity control method of the polysilicon layer of the present application. The doped polysilicon layers formed in each of embodiments 1 to 5 are used as samples to measure and obtain the furnace uniformity value according to the method of step (3) of the furnace uniformity control method of the polysilicon layer of the present application. The thickness values of each polysilicon layer and the within-wafer and wafer-to-wafer uniformity values are shown in Table 1 as follows:

[0092] Table 1

[0093]

[0094]

[0095] As can be seen from Table 1, at the same position in the furnace, such as the selected position in the furnace, compared with embodiments 1 to 5, the deposition rate of the in-situ doped polysilicon layer in embodiment 1 is relatively slow. In embodiment 2, the deposition time is appropriately shortened, and it is found that the deposition rate of the doped polysilicon layer increases. In embodiment 3, the other process conditions remain unchanged, and when the deposition time is continuously shortened to about 1H, the deposition rate slightly increases. It can be found that the deposition rate of the polysilicon deposited by the low-pressure in-situ doping method is relatively fast in the early stage, and the deposition rate of the doped polysilicon layer gradually slows down with the increase of the film thickness in the later stage due to the saturation of the gas atmosphere in the furnace. In embodiment 4, under the premise that the other process conditions remain unchanged, the deposition rate of the doped polysilicon layer has no obvious change when the low-pressure deposition + N2purging + re-deposition method is used to reduce the gas atmosphere in the furnace. In embodiment 5, under the premise that the other process conditions remain unchanged, the vacuum pressure in the cavity has little effect on the deposition rate, and the deposition rate of the doped polysilicon layer has no obvious change.

[0096] Based on the data in Table 1, the deposition rate of the doped polysilicon layer gradually slows down as the production film layer increases. When the doped polysilicon layer is grown to about 2500A by low-pressure in-situ doping, the gas atmosphere in the furnace tube has reached a relatively saturated state, and the growth rate of the doped polysilicon layer has become extremely slow. Simply extending the process time is not suitable for the economic and mass production needs. Therefore, it is relatively advantageous for mass production to control the growth thickness of the doped polysilicon layer to about 2500A.

[0097] At the same time, as can be seen from Table 1, the film layer thickness in the wafer is uniform during the deposition of the in-situ doped polysilicon layer, and the uniformity can be controlled to be less than 3%. In mass production to form a doped polysilicon layer, the position of each substrate in the furnace is different, and the thickness of the doped polysilicon layer formed by each substrate is different. For example, the thickness of the doped polysilicon layer formed at the furnace mouth, in the furnace, and at the furnace tail is different. The uniformity of the film layer thickness between wafers (in the furnace) can be controlled to be less than 5% by adjusting the process conditions according to the method for controlling the uniformity of the polysilicon layer in the furnace.

[0098] In S03, an undoped polysilicon layer is formed on the entire surface of the doped polysilicon layer formed in S02 to improve the efficiency of forming the undoped polysilicon layer. The undoped polysilicon layer formed in this step S03 can also be formed according to the method for forming the doped polysilicon layer in steps (2) and (3) of the method for controlling the uniformity of the polysilicon layer in the furnace. Specifically, the doped polysilicon layer 231 in Figure 3 is formed.

[0099] In the embodiment, the method for forming an undoped polysilicon layer on the surface of the doped polysilicon layer including the P+ channel 22 and the connection region layer stack includes the following steps:

[0100] introducing a gaseous second polysilicon precursor into the deposition cavity to perform a second chemical reaction to deposit and form an undoped polysilicon layer on the surface of the doped polysilicon layer in-situ;

[0101] In the embodiment, the second polysilicon precursor is also continuously introduced into the deposition cavity in the form of a gas stream to perform the second chemical reaction. In this way, the concentration of the second polysilicon precursor in the deposition cavity can be effectively maintained, and the efficiency of the second chemical reaction can be ensured, thereby improving the deposition efficiency of the undoped polysilicon layer. In the embodiment, the second polysilicon precursor can be introduced into the deposition cavity at a rate of 100-200 sccm. This rate can effectively maintain the concentration of the second polysilicon precursor in the deposition cavity, thereby effectively improving the deposition rate of the undoped polysilicon layer. In order to further improve the uniformity of the dispersion of the second polysilicon precursor in the deposition cavity and the uniformity of the film layer thickness between wafers during mass production, the second polysilicon precursor can also be introduced in the form of two-end gas introduction, such as through a diffuser.

[0102] The conditions of the second chemical reaction should at least enable the second polysilicon precursor to react to form silicon. In embodiments, the second chemical reaction can have a temperature of 600-650°C and a time of 1-4 hours; and the vacuum pressure in the deposition chamber can be 200-300 mT. By controlling and optimizing the conditions of the second chemical reaction, the efficiency of depositing the undoped polysilicon layer and the thickness of the undoped polysilicon layer can be adjusted. For example, the thickness of the undoped polysilicon layer can be controlled to be within the range of the thickness of the undoped polysilicon layer 232 described above. The second polysilicon precursor can be the same as the first polysilicon precursor, such as a mixture of SiH4or SiH4and N2.

[0103] In addition, as shown in Table 2 below, regardless of the POCl3deposition process, only the steps S02 and S03 described above, the polysilicon field plate preparation method of embodiments of the present application divides the process of forming the polysilicon layer into two parts. The first part of the process is the low-pressure in-situ doping method in step S02, which can directly form a doped polysilicon layer with a thickness of about 2500 A. In the process of step S03 that follows, the furnace tube and the pipeline are purged with N2to blow out the special gas in the furnace tube, and the furnace is cooled and silane is introduced. The silane is thermally decomposed again at low pressure to deposit on the bottom doped polysilicon layer to form a top undoped polysilicon layer, and the thickness of the top undoped polysilicon layer can be controlled to be 2000 A. Thus, the total thickness of the actual complete doped polysilicon layer + undoped polysilicon layer can be controlled to be 2500 A + 2000 A = 4500 A.

[0104] Further, as shown in Tables 1 and 2, the method of forming the polysilicon layer in two steps of steps S02 and S03 can effectively ensure the in-wafer uniformity of the thickness of each doped polysilicon layer / undoped polysilicon layer. For example, as shown in Table 2, the in-wafer thickness uniformity of the doped polysilicon layer / undoped polysilicon layer is as high as 2.61%, which is less than 3%.

[0105] Meanwhile, from Table 1 and Table 2, in the actual two-step method of forming the polysilicon layer and in mass production, the thickness uniformity between the two steps of forming the doped polysilicon layer and the undoped polysilicon layer is reduced. As mentioned above, this is probably due to the continuous vacuum operation of the vacuum pump connected to the furnace tail, resulting in a certain degree of loss of the gas atmosphere at the furnace tail position. The test results show poor uniformity between the wafers. The furnace tail position needs to be compensated for temperature to control the uniformity between the wafers within 5%. By adjusting the deposition process, such as appropriately increasing the temperature of the furnace tail or decreasing the temperature of the furnace mouth according to the deposition rate of the test furnace, or further setting a temperature gradient zone in the polysilicon deposition furnace and adjusting the temperature of the temperature gradient zone, etc., the test furnace is again tested until the uniformity between the wafers is controlled within 5%, so that the deposition film thickness data of the doped polysilicon layer and the undoped polysilicon layer meet the process requirement of 4500±400A, and the in-wafer uniformity value of the thickness is <3%, and the in-furnace (between-wafer) uniformity value of the thickness is <5%.

[0106] In S04, the entire surface of the undoped polysilicon layer formed in S03 is integrally formed with a conductive modification layer to improve the efficiency of forming the conductive modification layer.

[0107] After the conductive modification layer is formed on the outer surface of the undoped polysilicon layer, the doped polysilicon layer / undoped polysilicon layer / conductive modification layer sequentially stacked and combined in the P+ channel 22 constitutes the composite polysilicon layer contained in the polysilicon field plate of the embodiment of the present application, which is specifically shown in Figure 3 The composite polysilicon layer includes a doped polysilicon layer 231 / undoped polysilicon layer 232 / conductive modification layer 233 sequentially stacked and combined. The conditions for forming the conductive modification layer can be controlled so that the surface sheet resistance of the formed conductive modification layer is 11±3 Ω / □.

[0108] In the embodiment, the method for forming the conductive modification layer on the outer surface of the undoped polysilicon layer includes the following steps:

[0109] POCl3 is introduced into the deposition cavity to perform a third chemical reaction, and the conductive modification layer is formed in situ on the surface of the undoped polysilicon layer, followed by annealing and acid treatment.

[0110] POCl3 is introduced into the deposition cavity to perform a third chemical reaction, and the conductive modification layer is formed in situ on the surface of the undoped polysilicon layer, followed by annealing and acid treatment.

[0111] In a specific embodiment, based on the in-situ doping to form a doped polycrystalline silicon layer (denoted as DPOLY) in step S02 and the in-situ formation of an undoped polycrystalline silicon layer (denoted as UPOLY) in step S03, POCl3 deposition, acid bleaching, and annealing are performed on the surface of the undoped polycrystalline silicon layer to form the composite polycrystalline silicon layer contained in the polycrystalline silicon field plate of the above-described embodiment. The POCl3 deposition process conditions are controlled as follows: 980℃ depo for 30 min + 980℃ annealing for 30 min, with LN2 and LO2 flow rates adjusted according to the surface concentration and oxide layer thickness. The post-deposition acid bleaching treatment can be: 1:50 DHF for 3-5 min to remove the grown oxide layer and residual phosphorus impurities. Based on these conditions, Examples 6 to 8 were specifically designed, and five parallel samples were prepared. The thickness of the composite polycrystalline silicon layer formed by the POCl3 deposition process, the thickness of the composite polycrystalline silicon layer after annealing, and the sheet resistance of the conductive modification layer (i.e., its surface) were measured. Among them, Examples 6 to 7 were composite polycrystalline silicon layers deposited under the conditions of step (2) of the furnace uniformity control method for polycrystalline silicon layers in the above-mentioned application. Example 8 was a composite polycrystalline silicon layer deposited under the conditions of heating the furnace tail and setting the deposition conditions in step (3) of the furnace uniformity control method for polycrystalline silicon layers in the above-mentioned application. Using the composite polycrystalline silicon layers deposited in Examples 6 to 8 as samples, the uniformity values ​​within the wafer and within the furnace were measured and obtained according to the method of step (3) of the furnace uniformity control method for polycrystalline silicon layers in the above-mentioned application. The specific test results of the thickness values ​​of each composite polycrystalline silicon layer and its uniformity values ​​within and between wafers are shown in Table 2 below:

[0112] Table 2

[0113]

[0114] As shown in Table 2, by combining the polycrystalline deposition process in steps S02 and S03 with the POCl3 deposition process in step S04, the uniformity of the thickness of the composite polycrystalline silicon layer formed by each doped polycrystalline silicon layer / undoped polycrystalline silicon layer / conductive modification layer within the wafer can be effectively guaranteed. In particular, the intra-wafer uniformity value of the composite polycrystalline silicon layer thickness in Table 2 is the highest at 2.61%, which is less than 3%, indicating high intra-wafer thickness uniformity.

[0115] Meanwhile, the thickness of the composite polycrystalline silicon layer after POCl3 deposition and annealing in the comparative example was reduced to a certain extent after actual annealing, which may be due to the recrystallization of the polycrystalline silicon layer after annealing.

[0116] In addition, the above-mentioned process steps S02 and S04 are as follows: Figure 5 The process steps are shown in Figure K.

[0117] In S05, the doped polysilicon layer, the undoped polysilicon layer and the conductive modification layer formed on the surface of the rest regions such as the connection region are removed, and the doped polysilicon layer, the undoped polysilicon layer and the conductive modification layer formed in the P+ channel are reserved. The method for removing the doped polysilicon layer and the undoped polysilicon layer formed on the surface of the rest regions such as the connection region can be removing by using photolithography and etching. The doped polysilicon layer / undoped polysilicon layer / conductive modification layer formed on the surface of the rest regions such as the connection region is removed, so that the surface of the connection region is exposed, to facilitate the implementation of the step of forming other components.

[0118] The process step of step S05 is as shown in the process step of FIG. m. Figure 5

[0119] In addition, the polysilicon field plate according to the structure contained therein further comprises the following steps after step S05:

[0120] S06: the surface of the conductive modification layer and the exposed surface of the connection region after the treatment in step S05 are processed as shown in Figure 5 The connection layer is formed in the process of FIG. n to FIG. q, and the connection layer 25 as shown in Figure 2 and Figure 4 is formed on the surface of the conductive modification layer and the exposed surface of the connection region.

[0121] S07: the surface of the connection layer 25 and the surface of the P+ ring region 2 are processed as shown in Figure 5 The step of forming the electrode 4 in the process of FIG. r to FIG. s;

[0122] S08: the step of forming a protective layer (such as PI) on the surface of the polysilicon electrode 4 as shown in FIG. s in 5.

[0123] Therefore, the preparation method of the polysilicon field plate containing the composite polysilicon layer can effectively form the composite polysilicon layer structure including the doped polysilicon layer / undoped polysilicon layer / conductive modification layer stacked and combined in sequence in the P+ channel between the two adjacent isolation islands, so that each layer contained in the composite polysilicon layer plays a conductive synergistic effect, thereby making the prepared polysilicon field plate have high and wide electric field effect. Further, by controlling and adjusting the formation method of the doped polysilicon layer and the undoped polysilicon layer, not only the uniform distribution of the doping elements in the doped polysilicon layer can be improved, but also the thickness uniformity within the wafer and the wafer-to-wafer uniformity can be improved. Moreover, the formed polysilicon layer is a doped polysilicon layer / undoped polysilicon layer, which reduces the difficulty of polysilicon etching thereafter, and under the same dry etching conditions, the film layer after etching has a better appearance compared with the traditional single-layer undoped UPOLY structure. In addition, the preparation method of the polysilicon field plate containing the composite polysilicon layer has easy-to-control process, can make the prepared composite polysilicon layer structure have stable performance, thereby ensuring the stable performance of the polysilicon field plate and improving the yield of mass production, and has high efficiency and reduces the cost.​

[0124] Due to the polycrystalline silicon field plate based on the above application embodiment has the composite polycrystalline silicon layer structure as shown in Figure 3 , and its conductive performance is high, and has good conduction. In mass production, the uniformity within and between the polycrystalline silicon layer pieces can be effectively controlled, and the yield of mass production is effectively improved, thereby improving and widening the electric field effect of the polycrystalline silicon field plate, and effectively enhancing the applicability of the polycrystalline silicon field plate of the application embodiment. For example, it can be applied in fast recovery diodes and field effect tubes. And the corresponding performance of the semiconductor power device is improved, such as when the semiconductor power device is externally pressurized, it can effectively improve the reliability of the semiconductor power device itself.

[0125] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for controlling the uniformity of a polycrystalline silicon layer in a furnace, comprising the following steps: Multiple substrates are placed inside a polycrystalline silicon deposition furnace, and are at least distributed within the furnace at the furnace opening and tail; wherein, The substrate has a connection region and a P+ ring region. The P+ ring region includes multiple isolation islands. Each isolation island is frame-shaped and attached to the surface of the substrate. The multiple isolation islands are spaced apart and sequentially surround the connection region. A frame-shaped P+ channel is formed between two adjacent isolation islands. The conditions inside the polysilicon deposition furnace are adjusted to polysilicon deposition conditions. A gaseous polysilicon precursor is introduced into the polysilicon deposition furnace from both the furnace opening and the furnace tail at the same time to react and deposit, forming a polysilicon layer on the surface including the P+ channel and the connection area. The thickness of the polysilicon layer formed at the furnace opening and furnace tail is measured at least and the furnace uniformity value is obtained. When the furnace uniformity value of the polysilicon layer thickness is greater than a predetermined value T, the furnace tail is heated or the furnace opening is cooled. The polycrystalline silicon deposition furnace is provided with a sloping temperature zone, which includes a furnace mouth temperature zone, a furnace middle temperature zone, and a furnace tail temperature zone; the temperature of the furnace mouth temperature zone is higher than the temperature of the furnace tail temperature zone, and the temperature of the furnace tail temperature zone is higher than the temperature of the furnace middle temperature zone.

2. The furnace uniformity control method as described in claim 1, characterized in that: The heating or cooling process is performed at the following rate until the furnace uniformity of the polysilicon layer thickness is less than or equal to the predetermined value T: Each time the temperature at the furnace tail or furnace opening is adjusted by 0.5-2℃, a second polycrystalline silicon layer formation process is performed, and the thickness of the polycrystalline silicon layer formed by the second polycrystalline silicon layer formation process is measured to obtain a second furnace uniformity value. The steps of the second polycrystalline silicon layer formation process and obtaining the second furnace uniformity value are repeated until the last furnace uniformity value obtained is less than or equal to the predetermined value T. and / or The predetermined value T is 5%.

3. The furnace uniformity control method according to any one of claims 1-2, characterized in that: When the heating or cooling process causes the temperature difference between the furnace tail and the furnace mouth to reach 10-20°C, the heating or cooling process is stopped, and the flow rate of the polycrystalline silicon precursor is adjusted.

4. The furnace uniformity control method as described in claim 3, characterized in that: The method for adjusting the flow rate of the polycrystalline silicon precursor includes the following steps: The thickness of the polycrystalline silicon layer at the furnace opening and furnace tail is compared; Increase the flow rate of the polysilicon precursor at the point where the polysilicon layer thickness is relatively small until the furnace uniformity value of the polysilicon layer thickness is less than or equal to the predetermined value T.

5. The furnace uniformity control method according to any one of claims 1-2 and 4, characterized in that: The polycrystalline silicon precursor is introduced into the polycrystalline silicon deposition furnace from both ends of the dispersion tube; and / or The polycrystalline silicon layer includes a doped polycrystalline silicon layer and / or an undoped polycrystalline silicon layer.

6. The furnace uniformity control method as described in claim 5, characterized in that: The polycrystalline silicon layer includes a doped polycrystalline silicon layer and an undoped polycrystalline silicon layer stacked with the doped polycrystalline silicon layer. The method of introducing the gaseous polycrystalline silicon precursor into the polycrystalline silicon deposition furnace for reaction includes the following steps: A gaseous doped element precursor and a first polycrystalline silicon precursor are simultaneously introduced into the polycrystalline silicon deposition furnace from both the furnace opening and the furnace tail to form a mixed gas, and a first chemical reaction is carried out and deposited to form a doped polycrystalline silicon layer on the surface including the P+ channel and the connection region. After vacuuming and N2 purging the polysilicon deposition furnace, the gaseous second polysilicon precursor is introduced into the polysilicon deposition furnace to carry out a second chemical reaction and deposit, forming an undoped polysilicon layer on the surface of the doped polysilicon layer.

7. The furnace uniformity control method as described in claim 6, characterized in that: In the first chemical reaction process, the doped element precursor and the first polycrystalline silicon precursor are introduced into the polycrystalline silicon deposition furnace at a rate ratio of (10-20):(100-200) sccm; and / or The dopant precursor includes at least one of PH3, B2H6, and ASH3; and / or The first polycrystalline silicon precursor and / or the second polycrystalline silicon precursor comprise pure SIH4 or a mixture of SIH4 and N2.

8. The furnace uniformity control method as described in claim 6 or 7, characterized in that, The thickness of the doped polycrystalline silicon layer is 2000-2500 Å; and / or The thickness of the undoped polycrystalline silicon layer is 2000-3000 Å.

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