semiconductor devices

Abstract

A semiconductor device capable of repeated use and suppressing damage to surrounding equipment. The semiconductor device of this embodiment includes a first circuit, a first terminal, a second terminal, a conductor connecting the first terminal and the second terminal in series, and a first switching element. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when a second condition is met.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-49999 (filed on March 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation methods mainly involve semiconductor devices. Background Technology

[0003] It is known that there is a semiconductor device that protects surrounding equipment from excessive power by cutting off the current path. Summary of the Invention

[0004] The embodiment provides a semiconductor device that can be reused and can suppress damage to surrounding devices.

[0005] The semiconductor device of the embodiment includes a first circuit, a first terminal, a second terminal, a conductor connected in series between the first terminal and the second terminal, and a first switching element. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when a second condition is met. Attached Figure Description

[0006] Figure 1 It is a block diagram showing the overall configuration of a power supply system including the semiconductor device involved in the implementation.

[0007] Figure 2 This is a top view showing the overall configuration of the semiconductor device involved in the implementation.

[0008] Figure 3 It is an indication of the semiconductor device involved in the implementation method along Figure 2 A sectional view of the section along line III-III.

[0009] Figure 4 This is a block diagram used to illustrate an example of the configuration of the circuit included in the semiconductor chip of the semiconductor device according to the embodiment.

[0010] Figure 5 This is a circuit diagram used to illustrate an example of the configuration of the circuit included in the electronic fuse section of the semiconductor device according to the embodiment, and the connection between the electronic fuse section and the physical fuse section.

[0011] Figure 6 This is a timeline used to illustrate an example of the operation of a semiconductor device involved in the implementation.

[0012] Figure 7This is a circuit diagram used to illustrate an example of the circuit included in the electronic fuse section of the semiconductor device involved in the first modification, and the connection between the electronic fuse section and the physical fuse section.

[0013] Figure 8 This is a time diagram used to illustrate an example of the operation of a semiconductor device using the first variation.

[0014] Figure 9 This is a block diagram illustrating an example of the configuration of the circuit included in the semiconductor chip of the semiconductor device involved in the second variation.

[0015] Figure 10 This is a time diagram used to illustrate an example of the operation of a semiconductor device using the second variation.

[0016] Figure 11 This is a block diagram illustrating an example of the configuration of the circuit included in the semiconductor chip of the semiconductor device involved in the third variation. Detailed Implementation

[0017] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, components having the same function and structure will be given common reference numerals in the accompanying drawings.

[0018] 1. Implementation Method

[0019] The semiconductor device involved in the implementation will be described.

[0020] 1.1 Composition

[0021] 1.1.1 Power Supply System

[0022] First, use Figure 1 The configuration of the power supply system including the semiconductor device involved in the embodiments will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a power supply system including the semiconductor device 1 according to the embodiment.

[0023] Semiconductor device 1 is a package of electronic components. Semiconductor device 1 includes terminals Pin and Pout. Terminal Pin is connected, for example, to an external power supply circuit 2 of semiconductor device 1. Power is supplied from power supply circuit 2 to terminal Pin. Terminal Pout is connected, for example, to an external load 3 of semiconductor device 1. Power is output from terminal Pout to load 3.

[0024] 1.1.2 Semiconductor Devices

[0025] Figure 2This is a top view used to explain the configuration of the semiconductor device involved in the embodiment.

[0026] Semiconductor device 1 includes a semiconductor chip 20, a header 30, multiple pins 40, and multiple wires 50. Figure 2 The insulation covering the semiconductor chip 20, the head 30, multiple pins 40, and multiple wires 50 is omitted.

[0027] A semiconductor chip 20 is disposed on the head 30. In the following description, the direction from the head 30 toward the semiconductor chip 20 is defined as the upward direction. That is, the semiconductor chip 20 is disposed on the upper surface of the head 30. The head 30 has the function of dissipating heat generated by the semiconductor device 1 to the outside of the semiconductor device 1.

[0028] The semiconductor chip 20 is electrically connected to a plurality of pins 40 via corresponding wires 50. Thus, the semiconductor chip 20 can be supplied with power from outside the semiconductor device 1 via the plurality of pins 40. Additionally, the semiconductor chip 20 can output power to outside the semiconductor device 1 via the plurality of pins 40.

[0029] Figure 3 It is an indication of the semiconductor device involved in the implementation method along Figure 2 A sectional view of the section along line III-III.

[0030] like Figure 3 As shown, the semiconductor chip 20, the head 30, multiple pins 40, and multiple wires 50 are sealed by an insulator 60.

[0031] A plurality of pad electrodes 21 are disposed on the upper surface of the semiconductor chip 20. The plurality of pad electrodes 21 include pad electrodes 21a and 21b.

[0032] Multiple pad electrodes 41 are provided on the upper surface of multiple pins 40. The multiple pad electrodes 41 include pad electrodes 41a and 41b. Pad electrode 41a corresponds to pad electrode 21a. Pad electrode 41b corresponds to pad electrode 21b. The pin 40 with pad electrode 41a functions as a terminal pin. The pin 40 with pad electrode 41b functions as a terminal pout.

[0033] One of the plurality of pad electrodes 41 and a corresponding one of the plurality of pad electrodes 21 are physically and electrically connected by at least one of a plurality of wires 50. The plurality of wires 50 includes wires 50a and 50b. Wire 50a includes a first end engaged with pad electrode 21a and a second end engaged with pad electrode 41a. Wire 50b includes a first end engaged with pad electrode 21b and a second end engaged with pad electrode 41b.

[0034] Power is supplied from the outside of the semiconductor device 1 to the semiconductor chip 20 via pad electrode 41a, wire 50a, and pad electrode 21a. Power is also output from the semiconductor chip 20 to the outside of the semiconductor device 1 via pad electrode 21b, wire 50b, and pad electrode 41b.

[0035] 1.1.3 Semiconductor Chips

[0036] use Figure 4 The semiconductor chip 20 of the semiconductor device 1 according to the embodiment will be described. Figure 4 This is a block diagram used to illustrate an example of the configuration of the circuit included in the semiconductor chip of the semiconductor device according to the embodiment.

[0037] The semiconductor chip 20 includes a physical fuse section 22 and an electronic fuse section 23. The physical fuse section 22 and the electronic fuse section 23 are connected in series sequentially between terminals Pin and Pout.

[0038] The physical fuse section 22 is, for example, a wiring pattern of a conductor provided on the semiconductor chip 20. The physical fuse section 22 forms a conductive path connecting the terminal Pin to the electronic fuse section 23. The physical fuse section 22 is configured to fuse based on the current flowing through it. More specifically, the physical fuse section 22 is configured to fuse when the current value Ip flowing through it is a first current value I1 or higher for a predetermined first period. That is, the physical fuse section 22 has the function of electrically insulating the terminal Pin and the terminal Pout by physically cutting off the current path (hereinafter simply referred to as the current path) connecting the terminal Pin and the terminal Pout.

[0039] The electronic fuse section 23 is, for example, an electronic circuit provided on the semiconductor chip 20. The electronic fuse section 23 forms a conductive path connecting the physical fuse section 22 and the terminal Pout. The electronic fuse section 23 is configured to physically connect the current path based on the current flowing through the physical fuse section 22, and electrically insulate the terminal Pin from the terminal Pout. More specifically, the electronic fuse section 23 is configured, for example, to physically connect the current path but electrically insulate the terminal Pin from the terminal Pout when the current value Ip is greater than or equal to a second current value I2. The second current value I2 is less than the first current value I1.

[0040] 1.1.4 Electronic Fuse Section

[0041] use Figure 5 The specific configuration of the electronic fuse section 23 of the semiconductor device 1 according to the embodiment will be described. Figure 5This is a circuit diagram used to illustrate an example of the configuration of the circuit included in the electronic fuse section according to the embodiment, and the connection between the electronic fuse section and the physical fuse section.

[0042] The electronic fuse unit 23 includes a switching circuit 230, a detection circuit 231, and a control circuit 232.

[0043] The switching circuit 230 includes a switching element Q1 and a voltage generation circuit VG. The switching element Q1 is an N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0044] The first terminal of the switching element Q1 is connected to the physical fuse section 22. Current is supplied to the first terminal of the switching element Q1 via the physical fuse section 22. The gate of the switching element Q1 is connected to node N1. The second terminal of the switching element Q1 is connected to terminal Pout.

[0045] The first terminal of the voltage generation circuit VG receives the input voltage VIN. The second terminal of the voltage generation circuit VG is connected to node N1. The voltage generation circuit VG boosts the voltage VIN. The boosted voltage is output from the second terminal of the voltage generation circuit VG.

[0046] The detection circuit 231 includes switching elements Q2 and Q3, resistor R1, operational amplifiers AMP1 and AMP2, and a constant voltage source VS1. Switching element Q2 is an N-type MOSFET. Switching element Q3 is a P-type MOSFET.

[0047] The first terminal of switching element Q2 is connected to the first terminal of switching element Q1. The gate of switching element Q2 is connected to node N1. The second terminal of switching element Q2 is connected to node N2.

[0048] The first terminal of switching element Q3 is connected to node N2. The gate of switching element Q3 is connected to operational amplifier AMP1. The second terminal of switching element Q3 is connected to node N3.

[0049] The first terminal of resistor R1 is connected to node N3. The second terminal of resistor R1 is grounded.

[0050] Operational amplifier AMP1 has a positive input terminal (+), an inverting input terminal (-), and an output terminal. The positive input terminal (+) of operational amplifier AMP1 is connected to node N2. The inverting input terminal (-) of operational amplifier AMP1 is connected to the second terminal of switching element Q1. The output terminal of operational amplifier AMP1 is connected to the gate of switching element Q3.

[0051] Operational amplifier AMP2 has a positive input terminal (+), an inverting input terminal (-), and an output terminal. The positive input terminal (+) of operational amplifier AMP2 is connected to node N3. The inverting input terminal (-) of operational amplifier AMP2 is connected to the constant voltage source VS1. The output terminal of operational amplifier AMP2 is connected to control circuit 232.

[0052] The first terminal of the constant voltage source VS1 is connected to the inverting terminal (-) of the operational amplifier AMP2. The second terminal of the constant voltage source VS1 is grounded. The constant voltage source VS1 is configured to output a voltage Vs from its first terminal. The voltage Vs is, for example, the same as the voltage of node N3 at which the current values ​​Ip and I2 are simultaneously present.

[0053] The control circuit 232 includes a switching element Q4. The switching element Q4 is an N-type MOSFET.

[0054] The first terminal of switching element Q4 is connected to node N1. The gate of switching element Q4 is connected to the output terminal of operational amplifier AMP2. The second terminal of switching element Q4 is grounded.

[0055] 1.2 Actions

[0056] Next, use Figure 6 The operation of the semiconductor device 1 according to the embodiment will be explained. Figure 6 This is a timeline used to illustrate an example of the operation of a semiconductor device according to an embodiment. Figure 6 The diagram illustrates an example where each of the physical fuse section 22 and the electronic fuse section 23 electrically insulates the terminal Pin from the terminal Pout. Figure 6 The diagram shows the current value Ip flowing through the physical fuse section 22.

[0057] At time T1, power supply from power supply circuit 2 to load 3 begins. Simultaneously, current flows within semiconductor device 1.

[0058] More specifically, the voltage generation circuit VG applies a common voltage to the gates of switching elements Q1 and Q2. Through the operation of operational amplifier AMP1, the voltage at the inverting input terminal (-) (the second terminal of switching element Q1) of operational amplifier AMP1 becomes equal to the voltage at the non-inverting input terminal (+) (node ​​N2) of operational amplifier AMP1. Therefore, the gate-source voltages of switching elements Q1 and Q2 are equal. Furthermore, through the operation of operational amplifier AMP1, a voltage is supplied from the output terminal of operational amplifier AMP1 to the gate of switching element Q3. Therefore, switching element Q3 is turned on. Consequently, a current corresponding to the size ratio of switching element Q1 flows to switching element Q2. The voltage at the second terminal of switching element Q3 (node ​​N3) is determined based on the current flowing through switching element Q2.

[0059] The output terminal of operational amplifier AMP2 outputs the comparison result between the voltage Vs at the inverting input terminal (-) and the voltage at the non-inverting input terminal (+) (node ​​N3) of operational amplifier AMP2. Here, the current value Ip at time T1 is less than the second current value I2. Therefore, a "L" level signal is output from the output terminal of operational amplifier AMP2. Consequently, switching element Q4 is turned off based on the "L" level signal.

[0060] With switching element Q4 in the off state, the voltage supplied from the voltage generation circuit VG causes the voltage at node N1 to become voltage VON. Voltage VON is the voltage at which switching elements Q1 and Q2 are in the on state. Therefore, switching elements Q1 and Q2 remain in the on state. Consequently, the electrical connection between terminals Pin and Pout is maintained.

[0061] At time T2, the current value Ip is equal to the second current value I2. Therefore, the electronic fuse section 23 physically connects the current path but electrically insulates the terminals Pin and Pout (in... Figure 6 In this context, it is indicated by "e-fuse disconnect". Therefore, the current output from the terminal Pout is stopped.

[0062] More specifically, when the current value Ip is greater than or equal to the second current value I2, a "H (High)" level signal is output from the output terminal of operational amplifier AMP2. Consequently, switching element Q4 becomes active based on the "H" level signal. Therefore, the voltage at node N1 drops from, for example, voltage VON to ground potential. Thus, switching element Q1 switches from the active state to the off state.

[0063] exist Figure 6In the example, the voltage increases during the period from time T2 to time T3. Therefore, for example, between time T2 and time T3, an overvoltage begins to be applied to the first terminal of switching element Q1. Consequently, at time T3, switching element Q1 becomes a short-circuit state (in...). Figure 6 (In this context, it is indicated by the term "short circuit state"). Therefore, current begins to flow through the physical fuse section 22.

[0064] At time T4, the current value Ip is the same as the first current value I1.

[0065] During the period from time T4 to time T5, the current value Ip is maintained at or above the first current value I1. Therefore, at time T5, the physical fuse section 22 blows (at...). Figure 6 (In this context, it is referred to as "fuse"). That is, the physical fuse section 22 electrically insulates the terminal Pin from the electronic fuse section 23 by physically cutting off the current path. As a result, the current flowing in the semiconductor device 1 stops.

[0066] The operation of semiconductor device 1 ends after the above process.

[0067] 1.3 Effects of the Implementation Method

[0068] The semiconductor chip 20 of the semiconductor device 1 according to the embodiment includes a terminal Pin, a terminal Pout, a physical fuse section 22 connected in series between the terminal Pin and the terminal Pout, a switching element Q1, and a control circuit 232. The control circuit 232 is configured to open the switching element Q1 when a first condition is met. The first condition is, for example, that the current value Ip becomes a second current value I2 or higher. Therefore, the semiconductor device 1 can physically connect the current path based on the current value Ip of the physical fuse section 22, but electrically insulate the terminal Pin and the terminal Pout. Thus, the semiconductor device 1 can repeatedly protect the semiconductor device 1 and surrounding equipment from excessive power.

[0069] Furthermore, the physical fuse section 22 is configured to be physically disconnected under both a first condition and a second condition. The second condition is, for example, that the current value Ip exceeds the first current value I1 during the first period. Therefore, even if the switching element Q1 becomes short-circuited after being in the open state, the semiconductor device 1 can physically disconnect the physical fuse section 22, electrically isolating the terminal Pin from the electronic fuse section 23. That is, even if the switching element Q1 becomes short-circuited due to a fault, the current flowing in the semiconductor device 1 can be stopped. Therefore, damage to surrounding equipment caused by excessive power supply can be suppressed.

[0070] 2. Variations

[0071] Furthermore, the above-described embodiments can be modified in various ways.

[0072] The semiconductor device according to the modified example will now be described. The structure and operation of the semiconductor device 1 according to the modified example will be described focusing on the differences from the semiconductor device according to the embodiment, and other descriptions will be omitted. The semiconductor device according to the modified example can achieve the same effects as the embodiment.

[0073] 2.1 First Variation Example

[0074] In the above embodiment, an example is shown where the semiconductor chip 20 electrically insulates the terminal Pin from the terminal Pout based on the current value Ip. However, it is not limited to this. The semiconductor chip 20 may also electrically insulate the terminal Pin from the terminal Pout based on the voltage Vp applied to the wiring pattern of the physical fuse section 22 (hereinafter simply referred to as the voltage Vp of the physical fuse section 22). Here, the voltage Vp of the physical fuse section 22 is, for example, the voltage at one end of the wiring pattern of the physical fuse section 22 that is connected to the first terminal of the switching element Q1.

[0075] 2.1.1 Composition

[0076] First, the configuration of the semiconductor device 1 according to the first modification will be described. Since the configuration of the physical fuse section 22, the head 30, the plurality of pins 40, and the plurality of wires 50 of the semiconductor chip 20 in the semiconductor device 1 according to the first modification is the same as that in the embodiment, their descriptions will be omitted. Hereinafter, the configuration of the electronic fuse section 23 will be described mainly based on the differences from the embodiment, and descriptions of other configurations will be omitted.

[0077] 2.1.1.1 Semiconductor Chips

[0078] The configuration of the electronic fuse section 23 involved in the first modified example will be described.

[0079] The electronic fuse section 23 is configured such that, for example, when the voltage of the physical fuse section 22 is a second voltage V2 or higher, the current path is physically connected and the terminals Pin and Pout are electrically insulated. Other configurations can be the same as in the embodiment.

[0080] 2.1.1.2 Electronic Fuse Section

[0081] use Figure 7 The specific configuration of the electronic fuse section 23 of the semiconductor device 1 involved in the first modified example will be described. Figure 7This is a circuit diagram used to illustrate an example of the configuration of the circuit included in the electronic fuse section of the semiconductor device according to the first modification example, and the connection between the electronic fuse section and the physical fuse section.

[0082] The electronic fuse unit 23 includes resistors R2 and R3, a switching circuit 230, a detection circuit 231, and a control circuit 232. Since the configuration of the switching circuit 230 can be the same as in the embodiment, its description is omitted.

[0083] The first terminal of resistor R2 is connected to the first terminal of switching element Q1. A voltage based on the voltage Vp of physical fuse section 22 is supplied to the first terminal of resistor R2 and the first terminal of switching element Q1. The second terminal of resistor R2 is connected to node N4.

[0084] The first terminal of resistor R3 is connected to node N4. The second terminal of resistor R3 is grounded.

[0085] The detection circuit 231 includes a switching element Q5, an operational amplifier AMP3, and resistors R4, R5, and R6. The switching element Q5 is, for example, an N-type JFET (Junction Field Effect Transistor).

[0086] The first terminal of resistor R4 is connected to node N4. The second terminal of resistor R4 is connected to node N5.

[0087] A voltage VREF is input to the first terminal of resistor R5. The second terminal of resistor R5 is connected to node N6. The voltage VREF is, for example, a constant voltage supplied by a constant voltage source (not shown).

[0088] The first terminal of resistor R6 is connected to node N6. The second terminal of resistor R6 is grounded.

[0089] The first terminal of switching element Q5 is connected to node N5. The second terminal and gate of switching element Q5 are grounded.

[0090] Operational amplifier AMP3 has a positive input terminal (+), an inverting input terminal (-), and an output terminal. The positive input terminal (+) of operational amplifier AMP3 is connected to node N5. The inverting input terminal (-) of operational amplifier AMP3 is connected to node N6. The output terminal of operational amplifier AMP3 is connected to control circuit 232.

[0091] The control circuit 232 includes a switching element Q4.

[0092] The first and second terminals of the switching element Q4 are configured in the same way as in the implementation method. The gate of the switching element Q4 is connected to the output terminal of the operational amplifier AMP3.

[0093] 2.1.2 Actions

[0094] Next, use Figure 8 The operation of the semiconductor device 1 involved in the first modified example will be explained. Figure 8 This is a timing diagram used to illustrate an example of the operation of the semiconductor device involved in the first variation. Figure 8 The example shown illustrates how each of the physical fuse section 22 and the electronic fuse section 23 electrically insulates the terminal Pin from the terminal Pout. Figure 8 The diagram shows the current value Ip and the voltage Vp of the physical fuse section 22.

[0095] At time T6, power supply from power supply circuit 2 to load 3 begins. Simultaneously, current flows within semiconductor device 1.

[0096] More specifically, the voltage generation circuit VG applies a voltage to the gate of the switching element Q1. The voltage at the inverting input terminal (-) of operational amplifier AMP3 is compared with the voltage at the non-inverting input terminal (+) of operational amplifier AMP3, and the output terminal of operational amplifier AMP3 is output. Here, the voltage VREF is, for example, set so that the voltage at the inverting input terminal (-) of operational amplifier AMP3 is the same as the voltage at the non-inverting input terminal (+) of operational amplifier AMP3 when voltage Vp and the second voltage V2 are the same. At time T6, the voltage Vp is less than the second voltage V2. Therefore, an "L" level signal is output from the output terminal of operational amplifier AMP3. Thus, operational amplifier AMP3 outputs a signal corresponding to whether voltage Vp is greater than or equal to the second voltage V2, based on the comparison result between the voltage at the non-inverting input terminal (+) of operational amplifier AMP3 (based on the voltage between the physical fuse section 22 and the electronic fuse section 23) and the voltage at the inverting input terminal (-) of operational amplifier AMP3.

[0097] Switching element Q4 is turned off based on the "L" level signal from the output terminal of operational amplifier AMP3. Meanwhile, switching element Q1 is kept on. Therefore, the electrical connection between terminals Pin and Pout is maintained.

[0098] At time T7, the voltage of the physical fuse section 22 is the same as the second voltage V2. Therefore, the electronic fuse section 23 physically connects the current path but electrically insulates the terminal Pin from the terminal Pout (in... Figure 8 In this context, it is indicated by "e-fuse disconnect". Therefore, the current output from terminal Pout stops. At time T7, the current value Ip is less than the first current value I1.

[0099] More specifically, when voltage Vp is the same as the second voltage V2, an "H" level signal is output from the output terminal of operational amplifier AMP3. Therefore, switching element Q4 at time T7 becomes on. Consequently, the voltage at node N1 drops from, for example, voltage VON to ground potential. Thus, switching element Q1 switches from the on state to the off state.

[0100] exist Figure 8 In the example, the voltage Vp increases during the period from time T7 to time T8. Therefore, for example, between time T7 and time T8, an overvoltage begins to be applied to the first terminal of switching element Q1. Thus, at time T8, for the same reason as time T3 in the embodiment, switching element Q1 becomes a short-circuit state (in...). Figure 8 (This is referred to as a "short-circuit state"). Therefore, current begins to flow in the physical fuse section 22. Additionally, the voltage Vp begins to decrease accordingly.

[0101] At time T9, the current value Ip is the same as the first current value I1.

[0102] During the period from time T9 to time T10, the current value Ip is maintained at or above the first current value I1. Therefore, at time T10, the physical fuse section 22 blows (at...). Figure 8 (In this context, it is referred to as "fuse"). That is, the physical fuse section 22 electrically insulates the terminal Pin from the electronic fuse section 23 by physically cutting off the current path. As a result, the current flowing in the semiconductor device 1 stops.

[0103] By operating as described above, the semiconductor device 1 can repeatedly protect surrounding equipment from excessive power when the electronic fuse section 23 detects the voltage.

[0104] 2.2 Second Variation

[0105] In the above-described embodiments and the first variation, examples were shown where the physical fuse section 22 blows when the switching element Q1 becomes short-circuited, but this is not a limitation. For example, in the embodiments, the semiconductor device 1 may also be configured to suppress the switching element Q1 from becoming short-circuited. Hereinafter, regarding the configuration and operation of the semiconductor device 1 in the second variation, descriptions will mainly focus on configurations and operations different from those in the embodiments and the first variation, omitting other descriptions.

[0106] 2.2.1 Composition

[0107] use Figure 9 The configuration of the semiconductor device 1 involved in the second variation will be described. Figure 9This is a block diagram illustrating an example of the circuit configuration included in the semiconductor chip of the semiconductor device according to the second modification. Since the configuration of the header 30, the plurality of pins 40, and the plurality of wires 50 of the semiconductor device 1 according to the second modification can be the same as those in the embodiment and the first modification, their description is omitted. Hereinafter, regarding the configuration of the semiconductor chip 20, mainly the points that differ from those in the embodiment and the first modification will be described, and descriptions of other configurations will be omitted.

[0108] The second variation involves a semiconductor chip 20 that, in addition to the configuration of the embodiment and the first variation, also includes a diode D. The diode D is, for example, a Zener diode. The configuration of the semiconductor chip 20, excluding the diode D, can be the same as in the embodiment and the first variation.

[0109] The first terminal (cathode) of diode D is connected between the physical fuse section and the electronic fuse section 23. The second terminal (anode) of diode D is grounded. Diode D is in the conducting state when the voltage at the first terminal of diode D is greater than or equal to the breakdown voltage of diode D.

[0110] When the electronic fuse section 23 has the same configuration as in the embodiment, the breakdown voltage of diode D is, for example, set to a voltage higher than the voltage at the first terminal of diode D when a current with a second current value I2 flows through the physical fuse section 22. Alternatively, the breakdown voltage of diode D is, for example, set to a voltage lower than the voltage at the first terminal of diode D when a current with a first current value I1 flows through the physical fuse section 22. Preferably, the breakdown voltage of diode D is, for example, a voltage closer to the voltage at the first terminal of diode D when a current with a second current value I2 flows through the physical fuse section 22.

[0111] When the electronic fuse section 23 has the same configuration as in the first modified example, the breakdown voltage of diode D is, for example, set to be a voltage greater than or equal to the voltage at the first terminal of diode D when the voltage of the physical fuse section 22 is the second voltage V2. In the following explanation, we will use the case where the breakdown voltage of diode D is the same as the voltage at the first terminal of diode D when the voltage of the physical fuse section 22 is the second voltage V2 as an example.

[0112] 2.2.2 Actions

[0113] Next, use Figure 10 The operation of the semiconductor device 1 involved in the second variation will be explained. Figure 10 This is a timing diagram used to illustrate an example of the operation of a semiconductor device using the second variation. In this context... Figure 10In this section, the operation of the physical fuse section 22 and the electronic fuse section 23, which have the same configuration as in the first modified example, will be described. Figure 10 The diagram shows the current value Ip and the voltage Vp of the physical fuse section 22.

[0114] The operation at time T11 in the implementation method is the same as the operation at time T6 in the first variation.

[0115] At time T12, voltage Vp is the same as the second voltage V2. Therefore, similar to the operation at time T7 in the first variation, the electronic fuse section 23 physically connects the current path but electrically insulates the terminals Pin and Pout (in... Figure 10 In this context, it is indicated by "e-fuse disconnect". Therefore, the current output from the terminal Pout stops.

[0116] Furthermore, diode D becomes in a conducting state because the voltage across the physical fuse section 22 becomes the second voltage V2. Figure 10 In this case, "D: On" indicates the conduction state. Thus, unlike the operation from time T7 to time T8 in the first variation, the diode D becomes on before the switching element Q1 becomes short-circuited due to the application of an overvoltage to the first terminal of the switching element Q1. As a result, the current flowing within the semiconductor device 1 flows through the physical fuse section 22 and the diode D.

[0117] At time T13, the current value Ip is equal to the first current value I1.

[0118] During the period from time T13 to time T14, the current value Ip is maintained at or above the first current value I1. Therefore, at time T14, the physical fuse section 22 blows (at...). Figure 10 (In this context, it is referred to as "fuse"). That is, the physical fuse section 22 electrically insulates the terminal Pin from the electronic fuse section 23 by physically cutting off the current path. As a result, the current flowing in the semiconductor device 1 stops.

[0119] The operation of semiconductor device 1 ends after the above process.

[0120] Furthermore, in the above description, the operation of the physical fuse section 22 and the electronic fuse section 23 having the same configuration as in the first modified example has been described, but it is not limited to this. When the physical fuse section 22 and the electronic fuse section 23 have the same configuration as in the embodiment, it is also possible to achieve an operation that is substantially equivalent to the operation described above.

[0121] 2.2.3 Effects

[0122] According to the second modification, diode D is in the conducting state before switching element Q1 becomes short-circuited. This suppresses the supply of large current and the application of high voltage to the electronic fuse section 23. Therefore, it is possible to prevent switching element Q1 from becoming short-circuited. Consequently, damage to surrounding equipment caused by excessive current supply can be more reliably suppressed.

[0123] 2.3 Third variation example

[0124] In the above-described embodiments, first modifications, and second modifications, examples are shown where the physical fuse section 22 (the wiring pattern for fusing) is provided on the semiconductor chip 20. However, this is not a limitation. The physical fuse section 22 may be provided outside the semiconductor chip 20 within the semiconductor device 1.

[0125] In the semiconductor device 1 according to the third modification, unlike the embodiment, the first modification, and the second modification, the semiconductor chip 20 does not contain a wiring pattern for fusing, and the wire 50a disposed upstream of the semiconductor chip 20 functions as a physical fuse part 22. Furthermore, since the configuration of the head 30, the plurality of pins 40, and the plurality of wires 50 (excluding wire 50a) in the semiconductor device 1 according to the third modification can be the same as in the embodiment, the first modification, and the second modification, their description is omitted. Hereinafter, the configuration of the semiconductor chip 20 and the wire 50a will be described in a configuration different from that in the embodiment, the first modification, and the second modification.

[0126] use Figure 11 An example of the configuration of the semiconductor chip 20 involved in the third variation will be described. Figure 11 This is a block diagram illustrating an example of the configuration of the circuit included in the semiconductor chip of the semiconductor device involved in the third variation.

[0127] like Figure 11 As shown, the semiconductor chip 20 in the third variation does not include a wiring pattern for fusing. Furthermore, the electronic fuse unit 23 is connected between the wire 50a, which functions as the physical fuse unit 22, and the terminal Pout. The configuration of the electronic fuse unit 23 can be the same as that in both the embodiment and the first variation.

[0128] The wire 50a is configured to melt based on the current value of the current flowing in the wire 50a. More specifically, the wire 50a is configured to melt when the current value flowing in the wire 50a throughout the first period is a first current value I1 or higher.

[0129] In addition, Figure 11The example shown illustrates a case where the semiconductor chip 20 does not include a diode D, but the semiconductor chip 20 in the third variation may also include a diode D, just like the semiconductor chip 20 in the second variation. In this case, the first terminal of the diode D is connected between the physical fuse section 22 and the electronic fuse section 23. The second terminal of the diode D is grounded in the same manner as the diode D in the second variation.

[0130] Based on this configuration, it can achieve the same effect as the implementation method, the first modification, and the second modification.

[0131] 3. Others

[0132] Furthermore, in the above-described embodiments, first modifications, and second modifications, the semiconductor device 1 is shown as being packaged, but it is not limited to this. The semiconductor device 1 may also be configured such as a semiconductor chip 20 that is not sealed by an insulator. Specifically, for example, the semiconductor device 1 may replace the multiple pins 40 with multiple ball-shaped (or bump-shaped) terminals that can be connected to external electronic instruments. In this case, the ball-shaped (or bump-shaped) terminals function as pins or outlets. Since the ball-shaped (or bump-shaped) terminals are located below the semiconductor chip 20, multiple wires 50 may not be required.

[0133] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention as well as in the invention described in the technical solution and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: First circuit; First terminal; Second terminal; The conductor and the first switching element are connected in series between the first terminal and the second terminal; The second switching element includes a first end connected between the conductor and the first switching element, a gate connected to the gate of the first switching element, and a second end; The third switching element includes a first terminal, a gate, and a second terminal connected to the second terminal of the second switching element; The first operational amplifier includes a first input terminal connected between the second terminal and the first switching element, a second input terminal connected to the second terminal of the second switching element and the first terminal of the third switching element, and an output terminal connected to the gate of the third switching element. as well as The second operational amplifier includes a first input terminal supplied with a third voltage, a second terminal connected to the second terminal of the third switching element, and an output terminal. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when the second condition is met. The first circuit includes a fourth switching element, which includes a first terminal connected to the gate of the first switching element, a gate connected to the output of the second operational amplifier, and a second terminal grounded.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second circuit that outputs a voltage to the gate of the first switching element.

3. A semiconductor device, characterized in that, have: First circuit; First terminal; Second terminal; A conductor and a first switching element are connected in series between the first terminal and the second terminal; and The first operational amplifier includes a first input terminal supplied with a first voltage, a second input terminal connected between the conductor and the first switching element, and an output terminal. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when the second condition is met. The first circuit includes a second switching element, which includes a first terminal connected to the gate of the first switching element, a gate connected to the output terminal of the first operational amplifier, and a second terminal grounded.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a second circuit that outputs a voltage to the gate of the first switching element.

5. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a third switching element comprising a first terminal connected to the second input terminal of the first operational amplifier, a grounded second terminal, and a gate connected to the second terminal.

6. The semiconductor device according to claim 5, characterized in that, The third switching element is a junction field-effect transistor.

Images