High electron mobility transistors and methods of forming the same

Abstract

A high electron mobility transistor and a method of forming the same are disclosed. The high electron mobility transistor includes a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is on the compound semiconductor substrate. The source electrode is on a first side of the gate electrode on the compound semiconductor substrate. The drain electrode is on a second side of the gate electrode on the compound semiconductor substrate, the first side being opposite the second side. The first metal pillar is on the source electrode. The second metal pillar is on the drain electrode. The dielectric layer is on the compound semiconductor substrate, the dielectric layer surrounding the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is on the dielectric layer, the metal layer spanning the gate electrode, the first metal pillar, and the second metal pillar. The present application can avoid alignment and breakage problems when forming a lead hole, and can also reduce gate resistance.

Description

Technical Field

[0001] This invention relates to a high electron mobility transistor (HEMT) structure, and more particularly to a high electron mobility transistor with reduced gate resistance and a method for forming the same. Background Technology

[0002] High electron mobility transistors (HEMTs) are widely used in high-power semiconductor devices due to their high breakdown voltage and high output voltage.

[0003] High electron mobility transistor structures can be stacked with different III-V semiconductor layers and heterojunctions can be formed at their interfaces. Due to the band bending at the heterojunction, potential wells can be formed at the bent conduction band, thereby forming two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) in the potential wells.

[0004] While existing high electron mobility transistor structures are sufficient for the original purpose, they are not satisfactory in every respect and need to be improved. Summary of the Invention

[0005] This invention provides a high electron mobility transistor, comprising: a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is located on the compound semiconductor substrate. The source electrode is located on a first side of the gate electrode on the compound semiconductor substrate. The drain electrode is located on a second side of the gate electrode on the compound semiconductor substrate, opposite to the first side. The first metal pillar is located on the source electrode. The second metal pillar is located on the drain electrode. The dielectric layer is located on the compound semiconductor substrate and surrounds the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is located on the dielectric layer and spans across the gate electrode, the first metal pillar, and the second metal pillar.

[0006] This invention also provides a high electron mobility transistor, comprising: a gate electrode located on a substrate; source / drain electrodes located on the substrate opposite to the gate electrode; a metal pillar located on the source / drain electrodes; a first dielectric layer surrounding the bottom of the gate electrode and the bottom of the metal pillar; and a first metal layer located on the first dielectric layer, covering the top surface of the metal pillar and the top of its sidewalls.

[0007] This invention provides a method for forming a high electron mobility transistor, comprising: forming a gate electrode on a compound semiconductor substrate; forming a source electrode and a drain electrode on opposite sides of the gate electrode on the compound semiconductor substrate; forming a first metal pillar and a second metal pillar on the source electrode and the drain electrode, respectively; forming a dielectric layer on the compound semiconductor substrate to cover the gate electrode, the first metal pillar, and the second metal pillar; thinning the dielectric layer to expose the top of the gate electrode, the top of the first metal pillar, and the top of the second metal pillar, wherein the bottom of the gate electrode, the bottom of the first metal pillar, and the bottom of the second metal pillar are surrounded by the remaining portion of the dielectric layer; and forming a metal layer on the remaining portion of the dielectric layer, the metal layer extending across the top of the gate electrode, the top of the first metal pillar, and the top of the second metal pillar.

[0008] This invention provides a high electron mobility transistor structure that avoids alignment and breakage problems during lead hole formation. Furthermore, since the metal layer formed on the thinned dielectric layer spans the gate electrode, gate resistance is reduced. Attached Figure Description

[0009] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0010] Figures 1A-1F The diagram illustrates cross-sectional views of the various stages in forming a high electron mobility transistor, based on some embodiments.

[0011] Figure 2 This is a top view of a high electron mobility transistor, illustrated according to some embodiments.

[0012] Figure 3 The diagram shows a cross-sectional view of a high electron mobility transistor based on some embodiments.

[0013] Figure 4 The diagram shows a cross-sectional view of a high electron mobility transistor based on some embodiments.

[0014] Figure 5 The diagram shows a cross-sectional view of a high electron mobility transistor based on some embodiments.

[0015] Figure 6 This is a top view of a high electron mobility transistor, illustrated according to some embodiments.

[0016] Figure 7 The diagram shows an enlarged cross-sectional view of a high electron mobility transistor based on some embodiments.

[0017] Figure 8The diagram shows an enlarged cross-sectional view of a high electron mobility transistor based on some embodiments.

[0018] Figure 9 The diagram shows an enlarged cross-sectional view of a high electron mobility transistor based on some embodiments.

[0019] Icon labels:

[0020] 10, 20, 30, 40, 50, 60, 70: High electron mobility transistor structures

[0021] 100: Compound semiconductor substrate

[0022] 102: Gate electrode

[0023] 104: Source electrode

[0024] 106: Drain electrode

[0025] 108: Adhesion layer

[0026] 110a, 110b: Metal pillars

[0027] 112: First dielectric layer

[0028] 113: Etching Process

[0029] 114: First metal layer

[0030] 114a, 114b, 114c: Partial

[0031] 114W: Width

[0032] 114H: Altitude

[0033] 116: Dielectric layer

[0034] 117: Lead hole

[0035] 118: Cover metal layer

[0036] 118a: Part

[0037] 120: Moisture-proof layer

[0038] 121: Lead hole

[0039] 122: Second dielectric layer

[0040] 123: Lead hole

[0041] 123a: Lead hole

[0042] 124: Second metal layer

[0043] 126: Adhesion layer

[0044] 128: Third dielectric layer

[0045] 130: Third metal layer

[0046] H1: First Height

[0047] H2: Second Altitude

[0048] H3: Third Height

[0049] W1, W2: Width

[0050] AA: Line Detailed Implementation

[0051] The following description provides many different embodiments or examples to implement different features of this invention. The following description illustrates specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the invention describes a first feature formed on or above a second feature, it may include embodiments where the first and second feature are in direct contact, or embodiments where an additional feature is formed between the first and second feature, so that the first and second feature may not be in direct contact. Furthermore, repeated reference numerals or designations may be used in different embodiments; these repetitions are only for the purpose of simply and clearly describing the embodiments of the invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0052] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one or more elements or features in the illustrations and another element or feature(s). These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0053] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0054] While the steps in some embodiments are performed in a specific order, these steps can also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.

[0055] This invention provides a high electron mobility transistor structure (e.g., a pseudo-high electron mobility transistor (pHEMT) structure). The high electron mobility transistor structure includes a gate electrode, a source electrode, and a drain electrode. The high electron mobility transistor structure also includes metal pillars on the source and drain electrodes. A dielectric layer is formed to cover the gate electrode and the metal pillars, and then the dielectric layer is thinned (e.g., by an etch-back process) to expose the gate electrode and the metal pillars. Subsequently, a metal layer is formed across the gate electrode and the metal pillars. Therefore, vias in the dielectric layer can be replaced by metal pillars as connections between the metal layer and the source / drain electrodes, thus avoiding alignment and breakage problems during via formation. Furthermore, since the metal layer formed on the thinned dielectric layer crosses the gate electrode, gate resistance can be reduced.

[0056] Figures 1A-1F The diagram illustrates cross-sectional views of the various stages of forming a high electron mobility transistor structure 10, based on some embodiments. Figure 1A This is a cross-sectional view illustrating the formation of a high electron mobility transistor structure 10 according to some embodiments. The high electron mobility transistor structure 10 may be a pseudo-high electron mobility transistor (pHEMT) structure. In some embodiments, the high electron mobility transistor structure 10 is used in a power amplifier operating at high frequencies (e.g., MHz or THz frequencies). For example, the high electron mobility transistor structure according to embodiments of the present invention can be used in a power amplifier operating in the D band (in the range of 110 GHz and 170 GHz) or the ultra-high frequency band (in the range of 300 MHz and 3 GHz).

[0057] According to some embodiments, such as Figure 1A As shown, the high electron mobility transistor structure 10 includes a compound semiconductor substrate 100. The compound semiconductor substrate 100 may include a III-V compound semiconductor (e.g., GaAs, GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, or combinations thereof). In some embodiments, the compound semiconductor substrate 100 includes a base layer and an epitaxial layer formed on the base layer.

[0058] In some embodiments, the compound semiconductor substrate 100 includes a base layer, a buffer layer, a channel layer, a carrier supply layer, and a Schottky barrier layer. A buffer layer may be formed on the base layer, and a channel layer may be formed on the buffer layer. A carrier supply layer may be formed on the channel layer, and a Schottky barrier layer may be formed on the carrier supply layer. In some embodiments, the base layer includes GaAs, and the buffer layer includes at least one of GaAs and AlGaAs. In some embodiments, the channel layer includes at least one of GaAs and InGaAs, and the carrier supply layer includes at least one of AlGaAs, AlGaAsP, and InAlGaAs. The Schottky barrier layer may be a single-layer structure or a multi-layer structure. In some embodiments, the Schottky barrier layer includes AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, AlInGaP, or combinations thereof. In some embodiments, a base layer, buffer layer, channel layer, carrier supply layer, and Schottky barrier layer are formed by molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof.

[0059] Because the channel layer and carrier supply layer can be formed from different materials, their band gaps may differ. A heterojunction can be formed at the interface between the channel layer and the carrier supply layer. The energy band may bend at the heterojunction, and an energy well can be formed deep within the conduction band. Piezoelectrically generated electrons may be confined within the quantum well. Therefore, a two-dimensional electron gas (2DEG) may be formed at the interface between the channel layer and the carrier supply layer, and this 2DEG can generate a conductive current.

[0060] Next, according to some embodiments, such as Figure 1AAs shown, a gate electrode 102 is formed on a compound semiconductor substrate 100. The gate electrode 102 may include molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), tungsten-titanium (TiW), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), rhenium (Re), other available conductive materials, or combinations thereof. The gate electrode 102 may be formed using physical vapor deposition (PVD) processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition (ALD), other suitable processes, or combinations thereof. In some embodiments, the gate electrode 102 is formed by an evaporation process. In some embodiments, the gate electrode 102 has a crown shape. A Schottky contact may be formed between the gate electrode 102 and the compound semiconductor substrate 100.

[0061] Next, according to some embodiments, such as Figure 1A As shown, a source electrode 104 and a drain electrode 106 are formed on a compound semiconductor substrate 100. The source electrode 104 and drain electrode 106 may respectively comprise Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. The source electrode 104 and drain electrode 106 may be formed using physical vapor deposition (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition, other suitable processes, or combinations thereof. In some embodiments, the source electrode 104 and drain electrode 106 are formed by an evaporation process. An ohmic contact may be formed between the source electrode 104 and the compound semiconductor substrate 100, and an ohmic contact may be formed between the drain electrode 106 and the compound semiconductor substrate 100. Patterns of the source electrode 104 and drain electrode 106 may be formed using a metal mask.

[0062] Next, according to some embodiments, such as Figure 1B As shown, metal pillars 110a are formed on the source electrode 104 and metal pillars 110b are formed on the drain electrode 106. In some embodiments, as Figure 1B As shown, the top surfaces of metal pillars 110a and 110b are substantially at the same level as the top surface of the gate electrode 102. Metal pillars 110a and 110b may comprise conductive metals such as Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. Metal pillars 110a and 110b may be formed using physical vapor deposition processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition, other suitable processes, or combinations thereof. In some embodiments, metal pillars 110a and 110b are formed using an evaporation process. In some embodiments, the bottom surfaces of each metal pillar 110a and 110b are wider than their respective top surfaces. In some embodiments, each metal pillar 110a and 110b has a trapezoidal shape. In some embodiments, the top surface of the gate electrode 102 is higher than the top surfaces of the metal pillars 110a and 110b respectively. In some embodiments, the top surface of the gate electrode 102 is substantially flush with the top surfaces of the metal pillars 110a and 110b respectively.

[0063] like Figure 1B As shown, the gate electrode 102 has a first height H1, the metal pillar 110a has a second height H2, and the metal pillar 110b has a third height H3. The ratio of the first height H1 to the second height H2 can be in the range of 1 to 5 (e.g., between 1 and 2.5), and the ratio of the first height H1 to the third height H3 can also be in the range of 1 to 5 (e.g., between 1 and 2.5). The ratios of the first height H1 to the second height H2 and the first height H1 to the third height H3 can be adjusted so that the top surfaces of the gate electrode 102 and the metal pillars 110a and 110b are substantially at the same level.

[0064] Subsequently, according to some embodiments, such as Figure 1BAs shown, a compliant adhesion layer 108 is formed on the compound semiconductor substrate 100, the gate electrode 102, the metal pillars 110a and 110b, the source electrode 104, and the drain electrode 106. The adhesion layer 108 improves the adhesion between the conductive components of the high electron mobility transistor structure 10 (e.g., the gate electrode 102, source electrode 104, drain electrode 106, metal pillars 110a and 110b) and the subsequently formed first dielectric layer 112. In some embodiments, the adhesion layer 108 is made of silicon nitride.

[0065] Subsequently, according to some embodiments, such as Figure 1C As shown, a dielectric layer material is formed on the adhesion layer 108. The dielectric layer material may cover the gate electrode 102, metal pillars 110a and 110b, source electrode 104, and drain electrode 106. The dielectric layer material... Figure 1C The dielectric layer material is shown as a dashed line. It can be a polymer material, such as benzocyclobutene (BCB), polyimide, polybenzoxazole (PBO), silicone, acrylates, siloxane, other suitable materials, or combinations thereof. In some embodiments, the dielectric layer material is made of benzocyclobutene. In some embodiments, the dielectric constant of the dielectric layer material is lower than that of the adhesion layer 108. The dielectric layer material can be formed by a spin coating process followed by a curing process.

[0066] Next, according to some embodiments, such as Figure 1C As shown, the dielectric layer material is thinned to form a first dielectric layer 112. In some embodiments, the dielectric layer material is etched back in etching process 113. Therefore, the top surface of the first dielectric layer 112 is lower than the top surface of the gate electrode 102 and the top surfaces of the metal pillars 110a and 110b. The top surface of the first dielectric layer 112 is generally flat. The generally flat top surface can be used as a platform on which a metal layer (e.g., a metal wiring layer) is formed.

[0067] The top of the adhesion layer 108 can also be removed during etching process 113. In some embodiments, such as Figure 1C As shown, the tops of the gate electrode 102 and the metal pillars 110a and 110b are exposed from the first dielectric layer 112. In some embodiments, such as Figure 1CAs shown, the sidewalls at the top of the gate electrode 102, the metal pillar 110a, and the metal pillar 110b are exposed from the first dielectric layer 112. Therefore, the adhesion layer 108 lining the bottom of the gate electrode 102 and the metal pillars 110a and 110b, but not the top of them. The etching process 113 may include dry etching processes (e.g., reactive ion etching (RIE), anisotropic plasma etching methods), wet etching processes, or combinations thereof.

[0068] Next, according to some embodiments, such as Figure 1D As shown, a first metal layer 114 is formed over the gate electrode 102 and metal pillars 110a and 110b. In some embodiments, the first metal layer 114 includes portions 114a, 114b, and 114c. In some embodiments, portion 114a spans the gate electrode 102, portion 114b spans the metal pillar 110a, and portion 114c spans the metal pillar 110b. In some embodiments, the first metal layer 114 covers the top surface and the top of the sidewalls of the metal pillars 110a and 110b.

[0069] In some embodiments, the width of a portion 114a of the first metal layer 114 is greater than the width of the gate electrode 102, reducing the gate resistance. The tops of the gate electrode 102 and the metal pillars 110a and 110b may provide electrical connections to the first metal layer 114. In some embodiments, the portion 114a of the first metal layer 114 has a mountain-shaped form.

[0070] According to some embodiments, such as Figure 1D As shown, a portion 114a of the first metal layer 114 has a width 114W ranging from about 0.5 μm to about 4 μm. If the portion 114a of the first metal layer 114 is too wide, additional parasitic effects may occur, and the performance of the high electron mobility transistor may be reduced. If the portion 114a of the first metal layer 114 is too narrow, the reduction in gate resistance may be insufficient. In some embodiments, the portion 114a of the first metal layer 114 has a height 114H ranging from about 0.5 μm to about 4 μm. If the portion 114a of the first metal layer 114 is too high, it may collapse in subsequent processes. If the portion 114a of the first metal layer 114 is too low, the reduction in gate resistance may be insufficient.

[0071] According to some embodiments, such as Figure 1D As shown, the adhesion layer 108 lining is applied to the bottom of the gate electrode 102 and the metal pillars 110a and 110b. In some embodiments, such as Figure 1DAs shown, the first metal layer 114 directly contacts the first dielectric layer 112 and the adhesion layer 108. In some embodiments, the bottom surface of the first metal layer 114a on the gate electrode 102 is substantially flush with the bottom surfaces of the first metal layers 114b and 114c covering the metal pillars 110a and 110b.

[0072] The first metal layer 114 can be made of metallic materials such as Co, W, Ru, Al, Mo, Ti, Cu, Au, Pt, metal alloys, other suitable conductive materials, or combinations thereof. The first metal layer material can be deposited using physical vapor deposition (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition, other suitable processes, or combinations thereof. The first metal layer 114 can be patterned using patterning processes. Patterning processes can include photolithography and etching processes. Examples of photolithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. Etching processes can be dry etching or wet etching.

[0073] In some embodiments, a dielectric layer material is formed to cover the gate electrode 102 and metal pillars 110a and 110b, and then the dielectric layer material is thinned (e.g., by an etch-back process) to form a first dielectric layer 112. In one embodiment, after forming the gate electrode 102 and metal pillars 110a and 110b, a first dielectric layer 112 is formed to surround the gate electrode 102 and metal pillars 110a and 110b, and a first metal layer 114 is formed across the gate electrode 102 and metal pillars 110a and 110b on the first dielectric layer 112 to provide electrical connections from the first metal layer 114 to the gate electrode 102, source electrode 104, and drain electrode 106. Therefore, the first metal layer 114 is electrically connected to the gate electrode 102, source electrode 104, and drain electrode 106 without forming vias in the first dielectric layer 112. In some embodiments, the first dielectric layer 112 is connected to the gate electrode 102, the source electrode 104, and the drain electrode 106 without any lead holes.

[0074] In some embodiments, such as Figure 1D As shown, the gate electrode 102 and metal pillars 110a and 110b taper away from the exposed top of the first dielectric layer 112 in a direction away from the compound semiconductor substrate 100. This improves the connection between the first metal layer 114 and the gate electrode 102, as well as the connection between the first metal layer 114 and the metal pillars (e.g., metal pillars 110a and 110b). In some embodiments, the first metal layer 114 is in direct contact with the sidewalls of the top of the gate electrode 102, the sidewalls of the top of the first metal pillar 110a, and the sidewalls of the top of the second metal pillar 110b.

[0075] In some embodiments, such as Figure 1E As shown, a dielectric layer 116 is formed over a first metal layer 114, and a cap metal layer 118 is formed over the dielectric layer 116. In some embodiments, the cap metal layer 118 is electrically connected to the first metal layer 114 through a lead hole 117 formed in the dielectric layer 116. In some embodiments, a capacitor is formed from the first metal layer 114, the cap metal layer 118, and the dielectric layer 116 inserted therebetween. The dielectric layer 116 may be made of silicon nitride. The dielectric layer material may be compliantly deposited over the first metal layer 114 and the first dielectric layer 112 by chemical vapor deposition (e.g., low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, subatmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), atomic layer deposition, other suitable methods, or combinations thereof. The dielectric layer 116 may be patterned by a patterning process. The patterning process may include photolithography and etching processes. The process for forming the cover metal layer 118 may be similar to or the same as the process for forming the first metal layer 114 described above, and will not be repeated here for the sake of brevity.

[0076] Next, according to some embodiments, such as Figure 1E As shown, a moisture barrier 120 is formed on the cover metal layer 118, a second dielectric layer 122 is formed on the moisture barrier 120, and a second metal layer 124 is formed on the second dielectric layer 122. In some embodiments, the second metal layer 124 is electrically connected to the cover metal layer 118 through a lead hole 123 formed in the second dielectric layer 122 and a lead hole 121 formed in the moisture barrier 120. In some embodiments, the second dielectric layer 122 and the first dielectric layer 112 are made of the same material (e.g., benzocyclobutene).

[0077] A moisture barrier 120 can be compliantly formed over the cap metal layer 118, the first metal layer 114, and the first dielectric layer 112. The moisture barrier 120 may include silicon nitride. The moisture barrier material can be deposited over the cap metal layer 118, the first metal layer 114, and the first dielectric layer 112 by chemical vapor deposition (e.g., low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, subatmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), atomic layer deposition, other suitable methods, or combinations thereof. The moisture barrier 120 can be patterned. After the patterning process, openings are formed in the cap metal layer 118 of the moisture barrier 120, and lead holes 121 are formed in the openings in the moisture barrier 120.

[0078] The processes for forming the second dielectric layer 122 and the second metal layer 124 may be similar to or the same as those for forming the first dielectric layer 112 and the first metal layer 114, and will not be repeated here for the sake of brevity.

[0079] Subsequently, according to some embodiments, such as Figure 1F As shown, an adhesion layer 126 is formed over the second metal layer 124, and a third dielectric layer 128 is formed over the adhesion layer 126. The adhesion layer 126 can improve the adhesion between the second metal layer 124 and the third dielectric layer 128. For example, the adhesion layer 126 can be made of silicon nitride, and the third dielectric layer 128 can be made of benzocyclobutene. In some embodiments, the first dielectric layer 112, the second dielectric layer 122, and the third dielectric layer 128 are made of the same material. The processes for forming the adhesion layer 126 and the third dielectric layer 128 can be similar to or the same as the processes for forming the adhesion layer 108 and the first metal layer 114 described above, and will not be repeated here for the sake of brevity.

[0080] Figure 2 This is a top view of a high electron mobility transistor 10 according to some embodiments. Figures 1A-1F For along Figure 2 A cross-sectional view taken along the center line AA. In some embodiments, since the gate electrode 102 is crossed by a portion 114a of the first metal layer 114 on the first dielectric layer 112, it is not necessary to form a wire hole in the first dielectric layer 112 to connect the first metal layer 114 to the gate electrode 102. Therefore, in some embodiments, the gate electrode 102 does not include a pad portion having an increased width for connection to the wire hole, improving the minimization of the high electron mobility transistor structure 10. In some embodiments, such as Figure 2 As shown, the width W1 of the gate electrode 102 is generally uniform along its longitudinal direction. For example, the ratio of the maximum width to the minimum width of the gate electrode 102 can range from 0.9 to 1.1. In some embodiments, a portion 114a of the first metal layer 114 has a width W2, and the ratio of width W2 to width W1 is in the range of 1 to 4 (e.g., in the range of 1.1 to 3). If the ratio of width W2 to width W1 is too high, additional parasitic effects may occur, and the performance of high electron mobility transistors may be reduced. If the ratio of width W2 to width W1 is too low, the reduction in gate resistance may be insufficient.

[0081] In some embodiments, such as Figure 2As shown, the high electron mobility transistor structure 10 includes a plurality of metal pillars 110a and a plurality of metal pillars 110b. For example, the metal pillars 110a on the source electrode 104 may be formed in an array (e.g., a 2×2 array and a 3×3 array), and the metal pillars 110b on the drain electrode 106 may also be formed in an array (e.g., a 2×2 array and a 3×3 array). In some embodiments, the etching rate of the etch-back process forming the first dielectric layer 112 is more uniform by utilizing the plurality of metal pillars 110a and the plurality of metal pillars 110b. Therefore, the first dielectric layer 112 has a generally flat upper surface, which is beneficial for forming a wiring layer (e.g., a first metal layer 114) thereon.

[0082] By extending the first metal layer 114 across the gate electrode 102, the gate resistance can be reduced. A lead hole pad structure connecting the first metal layer 114 and the gate electrode 102 is unnecessary, and the area of ​​the high electron mobility transistor structure 10 can be minimized. The lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b having tops protruding beyond the first dielectric layer 112, thus avoiding alignment and breakage issues during lead hole formation.

[0083] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 3 This is a cross-sectional view of a high electron mobility transistor structure 20 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 3 As illustrated, the cap metal layer 118 of the high electron mobility transistor structure 20 also includes a portion 118a that covers a portion 114a of the first metal layer 114.

[0084] In some embodiments, a cap metal layer 118 is compliantly formed over a first metal layer 114a. Since a portion 114a of the first metal layer 114 has a mountain-shaped form, a portion 118a on the portion 114a of the first metal layer 114 also has a mountain-shaped form. The gate resistance can be further reduced by the portion 118a of the cap metal layer 118.

[0085] By extending the first metal layer 114 across the gate electrode 102, the gate resistance can be reduced. The lead hole pad structure connecting the first metal layer 114 and the gate electrode 102 can be eliminated, and the area of ​​the high electron mobility transistor structure 20 can be minimized. The lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b having a top surface substantially flush with the top surface of the gate electrode 102, thus avoiding alignment and breakage problems during lead hole formation. Alternatively, a cap metal layer 118 can be formed over the first metal layer 114a on the gate electrode 102, further reducing the gate resistance.

[0086] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 4 This is a cross-sectional view of a high electron mobility transistor structure 30 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 4 As illustrated, the second metal layer 124 of the high electron mobility transistor structure 30 includes a portion 124a that is electrically connected to a portion 114a of the first metal layer 114 through a lead hole 123a formed in the second dielectric layer 122.

[0087] In some embodiments, the second metal layer 124 contacts a portion 114a of the first metal layer 114 on the gate electrode 102, and the second metal layer 124 contacts the overlay metal layer 118 on the metal pillars 110a and 110b. Therefore, the gate resistance can be further reduced.

[0088] By extending the first metal layer 114 across the gate electrode 102, the gate resistance can be reduced. The via pad structure connecting the first metal layer 114 and the gate electrode 102 can be eliminated, and the area of ​​the high electron mobility transistor structure 30 can be minimized. The vias connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b, thus avoiding alignment and breakage issues during via structure formation. Alternatively, a second metal layer 124 can be formed on the gate electrode 102 above the first metal layer 114a, further reducing the gate resistance.

[0089] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 5 This is a cross-sectional view of a high electron mobility transistor structure 40 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 5As shown, metal layer 130 covers gate electrode 102, metal pillars 110a and 110b, and a second dielectric layer 122 formed therebetween.

[0090] After the third dielectric layer 128 is formed, an opening is formed in the third dielectric layer 128 (not shown) on a portion 124a of the second metal layer 124. The opening can be formed by photolithography, etching, other available processes, or a combination thereof.

[0091] Subsequently, according to some embodiments, such as Figure 5 As shown, a third metal layer 130 is formed to cover the third dielectric layer 128 and fill the opening on a portion 124a of the second metal layer 124. In some embodiments, the third metal layer 130 is electrically connected to the adjacent gate electrode 102 and may be referred to as a planar gate 130. The planar gate 130 can further reduce the gate resistance. In some embodiments, the third metal layer 130 covers the top surfaces of the third dielectric layer 128 and the second metal layer 124. The process for forming the third metal layer 130 may be similar to or the same as the process for forming the first metal layer 114 described above, and will not be repeated here for the sake of brevity.

[0092] Figure 6 This is a top view illustrating a high electron mobility transistor 40 according to some embodiments. According to some embodiments, such as... Figure 6 As shown, the first metal layer 114 and the second metal layer 124 may together form a comb-shaped metal layer. In some embodiments, the third metal layer 130 covers adjacent gate electrodes 102. In some embodiments, the third metal layer 130 covers a plurality of gate electrodes 102. In some embodiments, the third metal layer 130 also covers the source electrode 104 and the drain electrode 106 formed between the gate electrodes 102.

[0093] By extending the first metal layer 114 across the gate electrode 102, the gate resistance can be reduced. The lead hole pad structure connecting the first metal layer 114 and the gate electrode 102 can be eliminated, and the area of ​​the high electron mobility transistor structure 40 can be minimized. The lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b, thus avoiding alignment and breakage problems during lead hole formation. A third metal layer 130 can be formed as a planar gate 130 above the third dielectric layer 128. This further reduces the gate resistance.

[0094] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 7This is an enlarged cross-sectional view of a high electron mobility transistor structure 50 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 7 As shown, the first metal layer 114 only covers the metal pillars 110a and 110b, but does not cover the gate electrode 102.

[0095] In some embodiments, the first metal layer 114 is separated from the gate electrode 102. The process for forming the first metal layer 114 may be similar to or the same as the process described above for forming the first metal layer 114, and will not be repeated here for the sake of brevity.

[0096] Since the first metal layer 114 is formed directly on the metal pillars 110a and 110b, the lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced by the metal pillars 110a and 110b, thus avoiding alignment and breakage problems when forming the lead hole structure. The first metal layer 114 can be separated from the gate electrode 102, depending on design requirements.

[0097] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 8 This is an enlarged cross-sectional view of a high electron mobility transistor structure 60 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 8 As shown, the first metal layer 114 only partially covers the gate electrode 102.

[0098] In some embodiments, the first metal layer 114 covers at least a portion of the gate electrode 102. The process for forming the first metal layer 114 may be similar to or the same as the process described above for forming the first metal layer 114, and will not be repeated here for the sake of brevity.

[0099] Since the first metal layer 114 at least partially covers the gate electrode 102, the gate resistance can be reduced. The lead hole pad structure connecting the first metal layer 114 and the gate electrode 102 is unnecessary, and the area of ​​the high electron mobility transistor structure 60 can be minimized. The lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b, thus avoiding alignment and breakage problems during lead hole structure formation.

[0100] Many changes and / or modifications can be made to the embodiments of the present invention. Figure 9This is an enlarged cross-sectional view of a high electron mobility transistor structure 70 according to some embodiments. Some processes or components are the same as or similar to those in the above embodiments, and therefore these processes and components are not repeated here. Unlike the above embodiments, according to some other embodiments, such as... Figure 9 As shown, a first metal layer 114 is compliantly formed on the gate electrode 102 and metal pillars 110a and 110b.

[0101] In some embodiments, a first metal layer 114 covers the top surface of the first dielectric layer 112 between the metal pillar 110a and the gate electrode 102. In some embodiments, the first metal layer 114 is formed between the metal pillar 110a and the gate electrode 102. The process for forming the first metal layer 114 may be similar to or the same as the process described above for forming the first metal layer 114, and will not be repeated here for the sake of brevity.

[0102] Since the first metal layer 114 spans the gate electrode 102, the gate resistance can be reduced. The lead hole pad structure connecting the first metal layer 114 and the gate electrode 102 is unnecessary, and the area of ​​the high electron mobility transistor structure 70 can be minimized. The lead holes connecting the first metal layer 114 and the source and drain electrodes 104 and 106 can be replaced with metal pillars 110a and 110b, thus avoiding alignment and breakage problems during lead hole structure formation. Alternatively, the first metal layer 114 can be compliantly formed on the gate electrode 102 and the metal pillars 110a and 110b.

[0103] It should be noted that although the embodiments of the present invention illustrate a high electron mobility transistor structure, the apparatus of the embodiments of the present invention is not limited thereto. The high electron mobility transistor structure according to the embodiments of the present invention can also be integrated with other semiconductor structures (e.g., heterojunction bipolar transistor structures and thin-film resistor structures).

[0104] As described above, this embodiment of the invention provides a high electron mobility transistor structure and a method for forming the high electron mobility transistor structure. By having a first metal layer span across the gate structure and the metal pillars, the lead holes connecting the first metal layer and the source and drain electrodes can be replaced by metal pillars, thus avoiding alignment and breakage problems. Furthermore, a gate pad lead hole structure can be omitted, reducing the area of ​​the high electron mobility transistor structure. Additionally, the gate resistance can be reduced.

[0105] It should be noted that while some benefits and effects are described in the above embodiments, not all embodiments are required to achieve all benefits and effects.

[0106] The foregoing description outlines the feature components of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments; therefore, the scope of protection of the present invention shall be determined by the scope of the claims. Furthermore, although the present invention has been described above with reference to several preferred embodiments, it is not intended to limit the invention, and not all advantages have been described in detail herein.

Claims

1. A high electron mobility transistor, characterized in that, include: A compound semiconductor substrate; A gate electrode is located on the compound semiconductor substrate; A source electrode is located on a first side of the gate electrode on the compound semiconductor substrate; A drain electrode is located on a second side of the gate electrode on the compound semiconductor substrate, wherein the first side is opposite to the second side; A first metal pillar is located on the source electrode; A second metal pillar is located above the drain electrode; A dielectric layer is located on the compound semiconductor substrate, wherein the dielectric layer surrounds the gate electrode, the first metal pillar, and the second metal pillar; and A metal layer is located above the dielectric layer, wherein the metal layer spans the gate electrode and extends from one side wall of the first metal pillar across the first metal pillar and from one side wall of the second metal pillar across the second metal pillar.

2. The high electron mobility transistor as described in claim 1, characterized in that, One top surface of the dielectric layer is lower than one top of the gate electrode, one top of the first metal pillar, and one top of the second metal pillar.

3. The high electron mobility transistor as described in claim 1, characterized in that, The dielectric layer comprises a polymer.

4. The high electron mobility transistor as described in claim 1, characterized in that, The top surface of the dielectric layer is flat.

5. The high electron mobility transistor as described in claim 1, characterized in that, Also includes: An adhesion layer is applied to a bottom of the gate electrode, but not to a top of the gate electrode.

6. The high electron mobility transistor as described in claim 5, characterized in that, The metal layer is in direct contact with the dielectric layer and the adhesion layer.

7. The high electron mobility transistor as described in claim 5, characterized in that, The dielectric constant of the dielectric layer is lower than that of the attached layer.

8. A high electron mobility transistor, characterized in that, include: A gate electrode is located on a substrate; The source electrode and drain electrode are located on the substrate on opposite sides of the gate electrode; Multiple metal pillars are located above the source electrode and the drain electrode; A first dielectric layer surrounds a bottom of the gate electrode and the bottom of the plurality of metal pillars; as well as A first metal layer is located above the first dielectric layer. The first metal layer covers the top surface of the plurality of metal pillars and the top of the sidewalls.

9. The high electron mobility transistor as described in claim 8, characterized in that, The first metal layer covers at least a portion of the top surface of the gate electrode.

10. The high electron mobility transistor as claimed in claim 9, characterized in that, Also includes: A cover metal layer is placed on top of the first metal layer. The cap metal layer is in contact with the first metal layer above the gate electrode.

11. The high electron mobility transistor as claimed in claim 8, characterized in that, Also includes: A metal layer is placed on top of the first metal layer; A second metal layer is located on top of the cover metal layer. The second metal layer is in contact with the first metal layer on the gate electrode and the capping metal layer on the plurality of metal pillars.

12. The high electron mobility transistor as claimed in claim 11, characterized in that, Also includes: A second gate electrode is located on the substrate below the first metal layer; A third metal layer is located on top of the second metal layer. The third metal layer is electrically connected to the gate electrode and the second gate electrode.

13. The high electron mobility transistor as claimed in claim 8, characterized in that, The gate electrode has a width less than or equal to the width of the first metal layer on the gate electrode.

14. The high electron mobility transistor as claimed in claim 8, characterized in that, The first dielectric layer includes phenylcyclobutene.

15. A method for forming a high electron mobility transistor, characterized in that, include: A gate electrode is formed on a compound semiconductor substrate; A source electrode and a drain electrode are formed on the opposite side of the gate electrode on the compound semiconductor substrate; A first metal pillar and a second metal pillar are formed on the source electrode and the drain electrode, respectively. A dielectric layer is formed on the compound semiconductor substrate to cover the gate electrode, the first metal pillar, and the second metal pillar; The dielectric layer is thinned to expose a top of the gate electrode, a top of the first metal pillar, and a top of the second metal pillar, wherein a bottom of the gate electrode, a bottom of the first metal pillar, and a bottom of the second metal pillar are surrounded by a remaining portion of the dielectric layer; A metal layer is formed on the remaining portion of the dielectric layer, wherein the metal layer extends across the top of the gate electrode and extends across the first metal pillar from the sidewall of the top of the first metal pillar and across the second metal pillar from the sidewall of the top of the second metal pillar.

16. The method for forming a high electron mobility transistor as described in claim 15, characterized in that, Thinning the dielectric layer includes etching back the dielectric layer.

17. The method for forming a high electron mobility transistor as described in claim 15, characterized in that, The metal layer is in direct contact with the top sidewall of the gate electrode, the top sidewall of the first metal pillar, and the top sidewall of the second metal pillar.

18. The method for forming a high electron mobility transistor as described in claim 15, characterized in that, Before forming the dielectric layer, the following are also included: An adhesion layer is formed on the compound semiconductor substrate to cover the gate electrode, the first metal pillar, and the second metal pillar.

19. The method for forming a high electron mobility transistor as described in claim 18, characterized in that, Also includes: Removing a portion of the adhesive layer, wherein removing the portion of the adhesive layer and thinning the dielectric layer includes an etch-back process.

20. The method for forming a high electron mobility transistor as described in claim 15, characterized in that, The bottom surface of the metal layer on the gate electrode is flush with the bottom surfaces of the first metal pillar and the second metal pillar.

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