Semiconductor device

Abstract

The semiconductor device of the embodiment includes a silicon layer between a silicon substrate and an upper electrode, a cell region, a side surface, and a terminal region between the cell region and the side surface; and a polysilicon portion embedded in the terminal region of the silicon layer, in contact with the silicon layer, having a higher density of crystal grains than the silicon layer, and containing heavy metals. The silicon layer has a drift layer of the first conductivity type in the cell region and the terminal region, having a lower concentration of impurities of the first conductivity type than the silicon substrate, and containing the same kind of heavy metals as the heavy metals contained in the polysilicon portion. The terminal region does not include a base layer in contact with the upper electrode, a source layer in contact with the upper electrode, and a gate electrode.

Description

[0001] Related applications

[0002] This application claims priority based on Japanese Patent Application No. 2021-49759 (filed on March 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods mainly involve semiconductor devices. Background Technology

[0004] In a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a built-in diode (body diode) exists independently of the control unit based on the gate electrode. Improving the reverse recovery characteristics of this built-in diode can contribute to the circuit's efficiency. Methods for improving the reverse recovery characteristics of the built-in diode include introducing heavy metals into the drift layer and controlling the lifetime of charge carriers in the drift layer. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device that can improve the reverse recovery characteristics of a built-in diode.

[0006] According to the technical solution, the semiconductor device includes: an upper electrode; a lower electrode; a silicon substrate of a first conductivity type, located between the upper electrode and the lower electrode, and in contact with the lower electrode; a silicon layer, located between the silicon substrate and the upper electrode, having a cell region, a side surface, and an end region located between the cell region and the side surface; a gate electrode disposed in the cell region of the silicon layer; a gate insulating film disposed between the gate electrode and the silicon layer; and a polysilicon portion, buried in the end region of the silicon layer, in contact with the silicon layer, having a higher crystal grain density than the silicon layer, and containing heavy metals. The aforementioned silicon layer comprises: a drift layer of a first conductivity type, disposed in the aforementioned cell region and the aforementioned end region, wherein the impurity concentration of the first conductivity type is lower than that of the aforementioned silicon substrate, and includes heavy metals of the same type as those included in the aforementioned polysilicon portion; a base layer of a second conductivity type, disposed on the aforementioned drift layer in the aforementioned cell region, and in contact with the aforementioned upper electrode; and a source layer of a first conductivity type, disposed on the aforementioned base layer, and in contact with the aforementioned upper electrode, wherein the impurity concentration of the first conductivity type is higher than that of the aforementioned drift layer; the aforementioned end region does not include the aforementioned base layer in contact with the aforementioned upper electrode, the aforementioned source layer in contact with the aforementioned upper electrode, and the aforementioned gate electrode. Attached Figure Description

[0007] Figure 1 This is a schematic top view of the semiconductor device according to the first embodiment.

[0008] Figure 2 is a schematic cross-sectional view along the line A-A of Figure 1

[0009] Figure 3 is a schematic cross-sectional view of the semiconductor device of the second embodiment.

[0010] Figure 4 is a schematic cross-sectional view of the semiconductor device of the third embodiment.

[0011] Figure 5 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment.

[0012] Figure 6 is a schematic plan view of the semiconductor device of the first modification of each embodiment.

[0013] Figure 7 is a schematic plan view of the semiconductor device of the second modification of each embodiment.

[0014] Figure 8 is a schematic cross-sectional view of the semiconductor device of the third modification of each embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same structure is given the same reference numeral. In the following embodiments, the first conductive type is set to n-type and the second conductive type is set to p-type, but the first conductive type can be set to p-type and the second conductive type can be set to n-type.

[0016] [First Embodiment]

[0017] Figure 1 is a schematic plan view of the semiconductor device 1 of the first embodiment. In addition, in Figure 1 , only the characteristic portions are shown for easy understanding of the explanation.

[0018] Figure 2 is a schematic cross-sectional view along the line A-A of Figure 1

[0019] As shown in Figure 2 ​​As shown, the semiconductor device 1 includes an upper electrode 60, a lower electrode 70, a silicon substrate 10 located between the upper electrode 60 and the lower electrode 70, a silicon layer 20 located between the silicon substrate 10 and the upper electrode 60, and a plurality of buried structures 30 embedded in the silicon layer 20. The terms "upper part" for the upper electrode 60 and "lower part" for the lower electrode 70 are relative positional relationships used for illustrative purposes and are independent of the direction of gravity. Each buried structure 30 has at least a gate electrode 31 and a gate insulating film 42. Furthermore, in this embodiment, the buried structure 30 also includes a field plate electrode 32 and an insulating film 41 covering the upper end, lower end, and side surface of the field plate electrode 32. The semiconductor device 1 is a vertical semiconductor device in which current flows in the direction (longitudinal direction) connecting the upper electrode 60 and the lower electrode 70, controlled by the gate electrode 31.

[0020] A silicon layer 20 is provided on a silicon substrate 10. A lower electrode 70 is provided on the back side of the silicon substrate 10. A plurality of trenches are formed in the silicon layer 20, and buried structures 30 are provided in the trenches. The silicon layer 20 has a plurality of mesa surfaces 20a adjacent to the buried structures 30. By forming trenches in the silicon layer 20 for forming the aforementioned components of the buried structures 30, mesa surfaces 20a adjacent to the trenches are also formed simultaneously. The buried structures 30 do not reach the silicon substrate 10.

[0021] like Figure 1 As shown, the plurality of embedded structural portions 30 and the plurality of platform surfaces 20a extend, for example, in a strip-like shape. Among the strip-like plurality of embedded structural portions 30, the embedded structural portion located at the outermost end in the direction in which the plurality of embedded structural portions 30 are arranged is designated as the outermost embedded structural portion 30a. Furthermore, the platform surface adjacent to the outermost embedded structural portion 30a among the strip-like plurality of platform surfaces 20a is designated as the outermost platform surface 20b.

[0022] like Figure 1 As shown, the silicon layer 20 has a planar shape that is a quadrilateral shape with four sides 300. The silicon layer 20 has a unit region 100 and an end region 200. The end region 200 is located between the unit region 100 and the side surfaces 300. The embedded structure 30 and the mesa 20a are provided in the unit region 100.

[0023] The quadrilateral shape with four sides of 300 degrees can be arbitrary. For example, it could also be... Figure 6 A rectangle as shown. When 30 embedded components extend in a strip-like pattern, the number of directions in which the strips extend is arbitrary. For example, it could also be... Figure 6The strip shape extending in both directions as shown. Furthermore, the shape of the buried structure portion 30 when viewed from the direction of the perpendicular of the planar shape formed by the four side surfaces 300 can also not be a strip shape. For example, it can also be a collection of a plurality of regular hexagonal shapes or circular shapes arranged most densely inside than the end region 200.

[0024] As Figure 2 shown, the silicon layer 20 has a drift layer 21, a base layer 22, and a source layer 23 provided on the silicon substrate 10. The conductive type of the silicon substrate 10 and the drift layer 21 is n-type. The n-type impurity concentration of the drift layer 21 is lower than the n-type impurity concentration of the silicon substrate 10. The silicon substrate 10 and the drift layer 21 are provided in the cell region 100 and the end region 200. The end region 200 does not include the base layer 22 in contact with the upper electrode 60, the source layer 23 in contact with the upper electrode 60, and the gate electrode 31.

[0025] The mesa portion 20a includes a portion of the drift layer 21, the base layer 22 of p-type provided on the portion of the drift layer 21, and the source layer 23 of n-type provided on the surface of the base layer 22. The n-type impurity concentration of the source layer 23 is higher than the n-type impurity concentration of the drift layer 21.

[0026] The outermost mesa portion 20b adjacent to the outermost buried structure portion 30a includes a portion of the drift layer 21 and the base layer 22 of p-type provided on the portion of the drift layer 21. The source layer 23 is not provided in the outermost mesa portion 20b. Therefore, in the outermost mesa portion 20b, current control (MOS action) based on the gate electrode 31 is not performed. In the end region 200, the extension of the depletion layer due to the change in potential is different from that in the cell region 100. By providing the mesa portion close to the end region 200 as the outermost mesa portion 20b that does not perform MOS action and forming the outermost buried structure portion 30a, the extension of the depletion layer between the cell region 100 and the end region 200 can be made uniform, and the decrease in breakdown voltage can be suppressed.

[0027] In the outermost buried structure portion 30a, for example, one gate electrode 31 can be formed on one side (the outermost mesa portion 20b side), or the gate electrode 31 can not be formed at all. Furthermore, in the case where the decrease in breakdown voltage is not a problem, the outermost mesa portion 20b and the outermost buried structure portion 30a can not be formed. In contrast, in the case where the decrease in breakdown voltage is a problem, the outermost mesa portion 20b and the outermost buried structure portion 30a are provided as one group, and the number of groups is set to two or more.

[0028] Two gate electrodes 31 are provided in one buried structure portion 30, for example. In one buried structure portion 30, the gate electrodes 31 can be, for example, one group of two gate electrodes 31 arranged in parallel with each other, or two groups of one gate electrode 31 each. Figure 8The gate electrode 31 opposes the side surface of the base layer 22 with the gate insulating film 42 interposed therebetween. The gate insulating film 42 is provided between the side surface of the base layer 22 and the gate electrode 31. Further, a seam or a void can be formed in the gate electrode 31.

[0029] By applying a voltage exceeding the threshold value to the gate electrode 31, an n-type channel (inversion layer) can be formed in the portion of the base layer 22 opposing the gate electrode 31.

[0030] Further, the buried structure portion 30 has a field plate electrode 32. The field plate electrode 32 is located substantially at the center in the width direction (lateral direction) of the buried structure portion 30. The field plate electrode 32 extends within the buried structure portion 30 to a position lower than the gate electrode 31. The bottom of the field plate electrode 32 is located closer to the silicon substrate 10 than the bottom of the gate electrode 31. The field plate electrode 32 is not limited to being completely buried, and a seam or a void can be formed in the field plate electrode 32.

[0031] An insulating film 41 is provided between the field plate electrode 32 and the drift layer 21 and between the field plate electrode 32 and the gate electrode 31. The insulating film 41 can be formed of the same material or of a plurality of different materials.

[0032] The field plate electrode 32 is electrically connected to, for example, the upper electrode 60. Alternatively, the field plate electrode 32 can be electrically connected to the gate electrode 31. The field plate electrode 32 makes the distribution of the electric field of the drift layer 21 gentle in an off state in which the application of a voltage exceeding the threshold value to the gate electrode 31 is stopped.

[0033] The upper electrode 60 is provided above the silicon layer 20 and above the buried structure portion 30. An insulating film 43 is provided between the gate electrode 31 and the upper electrode 60 and between the field plate electrode 32 and the upper electrode 60.

[0034] The source layer 23 and the base layer 22 constituting the upper portion of the mesa portion 20a have a contact portion 26 in which a portion of the upper electrode 60 is provided. The source layer 23 and the base layer 22 are electrically connected to the upper electrode 60 by a so-called trench contact structure. The source layer 23 electrically connected to the upper electrode 60 and the base layer 22 electrically connected to the upper electrode 60 are provided in the cell region 100 and are not provided in the end region 200.

[0035] The polysilicon portion 50 is buried in the drift layer 21 of the end region 200. The polysilicon portion 50 is buried in a trench formed in the drift layer 21 of the end region 200, for example, by a CVD (Chemical Vapor Deposition) method. The trench is not limited to being completely filled with the polysilicon portion 50, and a seam or a void can be formed in the polysilicon portion 50.

[0036] For example, it could also be Figure 7 The polysilicon portion 50 has a structure with notches 50a as shown. No trenches are formed within the drift layer 21 in the region of the notches 50a. The number of notches 50a in the polysilicon portion 50 is arbitrary, but it is desirable that... Figure 1 The structure shown in the figure is a continuous enclosure of the embedded structural part 30. This prevents the diffusion of heavy metals (Pt, Au, etc.) into the end region 200, which will be described later.

[0037] In the Figure 6 In the case where the strip-shaped embedded structure 30 extends in multiple directions, multiple embedded structure portions 30 extending in the same direction are grouped together. The number of groups of embedded structure portions 30 surrounded by the polysilicon portion 50 is arbitrary. For example, it could also be... Figure 6 The text indicates a structure in which the embedded structural portion 30 is surrounded by polysilicon portions 50 in groups. For example, it could also be a structure in which the embedded structural portion 30 is surrounded by two or more groups of polysilicon portions 50. In this case, a notch 50a could also be provided.

[0038] The polysilicon portion 50 is directly embedded into the trench formed in the drift layer 21 without passing through an insulating film such as a silicon oxide film. The side and bottom surfaces of the polysilicon portion 50 are in contact with the drift layer 21. No insulating film such as a silicon oxide film is provided between the polysilicon portion 50 and the drift layer 21. The upper surface of the polysilicon portion 50 is in contact with the insulating film 43.

[0039] The silicon layer 20, including the drift layer 21, is a monocrystalline layer (or a layer with high crystallinity close to monocrystalline) epitaxially grown on the silicon substrate 10. In contrast, the polycrystalline silicon portion 50 is composed of polycrystalline silicon with a higher grain density than the silicon layer 20. The grain boundary density of the polycrystalline silicon portion 50 is higher than that of the silicon layer 20.

[0040] The polysilicon portion 50 contains a heavy metal, such as Pt or Au. The cell regions 100 and 200 of the drift layer 21, and the regions between the cell regions 100 and the polysilicon portion 50, contain the same type of heavy metal as that contained in the polysilicon portion 50.

[0041] Next, the manufacturing method of semiconductor device 1 will be described.

[0042] A silicon layer 20 is formed on the silicon substrate 10, and a buried structure portion 30 and a polysilicon portion 50 are formed in the silicon layer 20. For example, the polysilicon portion 50 is formed earlier than the buried structure portion 30. In the upper portion of the mesa portion 20a, a base layer 22 and a source layer 23 are formed by, for example, an ion implantation method. Then, an insulating film 43 is formed on the silicon layer 20 and on the buried structure portion 30. After the insulating film 43 is formed, a contact portion 26 that penetrates the insulating film 43 to reach the base layer 22 and the source layer 23 is formed. Heavy metal (Pt, Au, etc.) is diffused into the drift layer 21. As a method of diffusing the heavy metal, a method of forming a silicide layer in the contact portion 26 and diffusing it by heat treatment, or a method of implanting the heavy metal near the contact portion 26 by an ion implantation method and diffusing it by heat treatment can be used. In the case of the method of forming a silicide layer in the contact portion 26 and diffusing it by heat treatment, in the contact portion 26, for example, a Pt film is formed as a film containing heavy metal. After the Pt film is formed, heat treatment is performed, and a Pt silicide is formed in the portion where the Pt film contacts the upper portion of the mesa portion 20a (the base layer 22 and the source layer 23). After the Pt silicide is formed, heat treatment at a higher temperature than the heat treatment for forming the Pt silicide is performed, and Pt is diffused into the drift layer 21. Then, the Pt silicide and the Pt film are removed, and an upper electrode 60 is formed in the contact portion 26 and on the insulating film 43.

[0043] The heavy metal (Pt, Au, etc.) diffused into the drift layer 21 functions as a lifetime killer that becomes a recombination center of electrons and holes. In the reverse recovery operation in which a reverse bias is applied to the built-in diode (a PIN diode constituted by the base layer 22, the drift layer 21, and the silicon substrate 10) of the semiconductor device 1, one of the carriers (electrons and holes) remaining in the drift layer 21 is captured by the heavy metal (Pt, Au, etc.), and the other carrier meets it and recombines. Thus, the reverse recovery charge amount Qrr of the built-in diode can be reduced, and the reverse recovery characteristics can be improved.

[0044] The cell region 100 has more carriers in the drift layer 21 than the end region 200, and thus the above-described heavy metal as a lifetime killer is required to exist in the cell region 100 for lifetime control.

[0045] Further, in a state where the built-in diode is forward biased, holes injected from the p-type base layer 22 of the cell region 100 into the drift layer 21 also flow into the end region 200. Also, in the reverse recovery operation of the built-in diode, the holes of the cell region 100 are discharged to the upper electrode 60 via the base layer 22, and there are also holes that return from the end region 200 to the cell region 100 side.

[0046] On the upper surface of the end region 200, since the drift layer 21 is not in contact with the upper electrode 60, holes of the end region 200 are diverted and moved to the cell region 100 under the outermost embedded structure portion 30a of the outer periphery of the cell region 100 at the time of the reverse recovery operation, and are discharged to the upper electrode 60. That is, the holes of the end region 200 are less likely to be discharged than the holes of the cell region 100. In order to reduce the return current (so-called tail current) from the end region 200, it is preferable that some degree of heavy metal exists in the end region 200 as well.

[0047] According to the present embodiment, while the heavy metal is retained in the drift layer 21 of the cell region 100, some degree of heavy metal is also retained in the end region 200 by the polysilicon portion 50 formed in the end region 200.

[0048] The grain boundary of the polysilicon portion 50 functions as a gettering site of the heavy metal such as Pt or Au. The heavy metal diffused into the end region 200 from the heavy metal introduced into the drift layer 21 of the cell region 100 with the metal silicide film formed on the above-mentioned contact portion 26 as a diffusion source is captured by the polysilicon portion 50. The polysilicon portion 50 that has captured the heavy metal also functions as a diffusion source of the new heavy metal. Thus, it is possible to retain the heavy metal in the drift layer 21 of the region between the original diffusion source of the heavy metal (the formation portion of the contact portion 26) and the polysilicon portion 50.

[0049] The polysilicon portion 50 can be either n-type or p-type, or can be undoped. The polysilicon portion 50 can also be the same material as the gate electrode 31 or the field plate electrode 32.

[0050] The heavy metal concentration in the drift layer 21 of the cell region 100 and the heavy metal concentration in the drift layer 21 of the region between the cell region 100 and the polysilicon portion 50 are higher than the heavy metal concentration in the drift layer 21 of the region between the polysilicon portion 50 and the side surface 300.

[0051] Since the thermal diffusion length of the heavy metal (Pt, Au, etc.) in the single crystal silicon is relatively long, in the case where the polysilicon portion 50 is not provided in the end region 200, it is difficult to retain the heavy metal in the region adjacent to the cell region 100 in the end region 200.

[0052] According to the present embodiment, by providing the polysilicon portion 50 in the end region 200, it is possible to make the heavy metal concentration in the region between the cell region 100 and the polysilicon portion 50 in the end region 200 also high, so it is possible to suppress the return current from the end region 200 at the time of the reverse recovery operation of the built-in diode, and to improve the reverse recovery characteristics.

[0053] To suppress the diffusion of heavy metals to the region outside the polysilicon portion 50, as shown in FIG. 1, the polysilicon portion 50 preferably continuously surrounds the cell region 100. Figure 1

[0054] Further, polysilicon has more defects than single-crystal silicon, and the polysilicon portion 50 itself contains energy levels as recombination centers, suppressing the reverse recovery current in the end region 200.

[0055] Further, the polysilicon portion 50 functions as a structure that limits the expansion of holes injected into the drift layer 21 of the cell region 100 in a state where the built-in diode is forward-biased, to the end region 200. By limiting the expansion of holes to the end region 200, the return current from the end region 200 can be reduced, and the discharge path of holes to the upper electrode 60 can be shortened, and the reverse recovery time can be shortened. From the viewpoint of limiting the diffusion of holes to the end region 200, the depth of the polysilicon portion 50 is preferably deeper than the depth of the buried structure portion 30. That is, the distance (shortest distance) between the polysilicon portion 50 and the lower electrode 70 is preferably shorter than the distance (shortest distance) between the buried structure portion 30 and the lower electrode 70. The polysilicon portion 50 does not reach the silicon substrate 10.

[0056] Heavy metals such as Pt and Au do not easily permeate a silicon oxide film. Therefore, if a silicon oxide film is provided between the polysilicon portion 50 and the drift layer 21, the silicon oxide film becomes an obstacle for heavy metals diffused to the end region 200, and it is possible to be sent back to the cell region 100.

[0057] If the depletion layer that extends to the end region 200 reaches the polysilicon portion 50, in this portion, the electric field distribution changes, and if the critical electric field strength is exceeded, it is possible that local avalanche breakdown occurs. Therefore, the polysilicon portion 50 is preferably formed at a position where the depletion layer does not reach.

[0058] [2nd Embodiment]

[0059] Figure 3 FIG. 1 is a schematic cross-sectional view of a semiconductor device 2 of a 2nd embodiment.

[0060] The silicon layer 20 of this semiconductor device 2 further has an n-type channel stopper 25 provided between the drift layer 21 of the end region 200 and the polysilicon portion 50, and having a higher n-type impurity concentration than the drift layer 21. The channel stopper 25 is formed on the sidewall and the bottom surface of the trench formed in the end region 200. Then, the polysilicon portion 50 is formed in the trench. The channel stopper 25 is provided between the sidewall of the polysilicon portion 50 and the drift layer 21 and between the bottom surface of the polysilicon portion 50 and the drift layer 21.

[0061] ​By the trench stopper 25, the depletion layer can be prevented from reaching the polysilicon portion 50, and local avalanche breakdown can be prevented.

[0062] [3rd Embodiment]

[0063] Figure 4 is a schematic cross-sectional view of a semiconductor device 3 of the 3rd embodiment.

[0064] For example, if the n-type impurity concentration in the drift layer 21 is high as in a device with a relatively low withstand voltage, the number of carriers subject to lifetime control is large, and accordingly, a large amount of heavy metal needs to be retained in the end region 200.

[0065] As shown in Figure 4 , by providing a plurality of polysilicon portions 50 including, for example, a 1st polysilicon portion 51, a 2nd polysilicon portion 52, and a 3rd polysilicon portion 53 in the end region 200, the amount of gettering of heavy metal in the end region 200 can be increased, and the increase in the number of carriers subject to lifetime control can be accommodated. For example, in the example shown in Figure 4 , the 1st polysilicon portion 51 is provided at a position closest to the cell region 100, the 2nd polysilicon portion 52 is provided between the 1st polysilicon portion 51 and the side surface 300 of the silicon layer 20 (shown in Figure 1 ), and the 3rd polysilicon portion 53 is provided between the 2nd polysilicon portion 52 and the side surface 300. The cell region 100 is surrounded by the three polysilicon portions 51 to 53. The number of polysilicon portions 50 can also be two or more than four.

[0066] [4th Embodiment]

[0067] Figure 5 is a schematic cross-sectional view of a semiconductor device 4 of the 4th embodiment.

[0068] As shown in Figure 5 , a 1st polysilicon portion 51 shallower than the buried structure portion 30 can also be provided. In Figure 5In the illustrated example, the cell region 100 is surrounded by the first, second, and third polysilicon portions 51, 52, and 53, which are different in depth from each other. The first, second, and third polysilicon portions 51, 52, and 53 are arranged in a direction in which the cell region 100 is connected to the side surface 300. The distance between the first polysilicon portion 51, which is located closest to the cell region 100, and the lower electrode 70 (shortest distance) is longer than the distance between the buried structure portion 30 and the lower electrode 70 (shortest distance). The distance between the second polysilicon portion 52 and the lower electrode 70 (shortest distance) is shorter than the distance between the first polysilicon portion 51 and the lower electrode 70 (shortest distance). The distance between the third polysilicon portion 53 and the lower electrode 70 (shortest distance) is shorter than the distance between the second polysilicon portion 52 and the lower electrode 70 (shortest distance). In this example, the number of polysilicon portions 50 can also be two or more than four.

[0069] Several embodiments of the present application have been described above, but these embodiments are presented by way of example only, and are not intended to limit the scope of the application. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof are included within the scope or spirit of the application, and are included within the scope of the application and its equivalents as recited in the claims.

Claims

1. A semiconductor device, wherein, have: Upper electrode; Lower electrode; A silicon substrate of the first conductivity type is located between the upper electrode and the lower electrode and is in contact with the lower electrode. A silicon layer, located between the silicon substrate and the upper electrode, has a unit region, a side surface, and an end region located between the unit region and the side surface; An insulating film is disposed between the silicon layer and the upper electrode. A gate electrode is disposed in the aforementioned cell region of the aforementioned silicon layer; A gate insulating film is disposed between the gate electrode and the silicon layer; and The polycrystalline silicon portion, embedded in the aforementioned end region of the silicon layer, has a higher density of crystal grains than the silicon layer and contains heavy metals. The above silicon layer has: The drift layer of the first conductivity type is provided in the above-mentioned unit region and the above-mentioned end region. The impurity concentration of the first conductivity type is lower than that of the above-mentioned silicon substrate, and it contains heavy metals of the same type as those contained in the above-mentioned polysilicon portion. A second conductivity type substrate layer is disposed on the drift layer of the aforementioned unit region and is in contact with the aforementioned upper electrode; and The source layer of the first conductivity type is disposed on the aforementioned substrate layer and is in contact with the aforementioned upper electrode. The impurity concentration of the first conductivity type is higher than that of the aforementioned drift layer. In the aforementioned unit region, the upper electrode has a contact that penetrates the insulating film and reaches the source layer and the substrate layer. The aforementioned end region does not include: the aforementioned base layer in contact with the aforementioned upper electrode, the aforementioned source layer in contact with the aforementioned upper electrode, and the aforementioned gate electrode. The heavy metal concentration in the drift layer of the aforementioned unit region is higher than the heavy metal concentration in the drift layer of the region between the aforementioned polysilicon portion and the aforementioned side surface. The aforementioned polysilicon portion is in contact with the aforementioned drift layer in the aforementioned silicon layer. On the upper surface of the aforementioned end region, the aforementioned drift layer does not contact the aforementioned upper electrode, but is positioned opposite the aforementioned upper electrode through the aforementioned insulating film.

2. The semiconductor device of claim 1, wherein, The aforementioned polysilicon portion continuously surrounds the aforementioned unit region.

3. The semiconductor device as claimed in claim 1, wherein, The aforementioned gate electrode and the aforementioned gate insulating film are disposed within a structure embedded in the aforementioned silicon layer of the aforementioned unit region. The distance between the polysilicon portion and the lower electrode is shorter than the distance between the structural portion and the lower electrode.

4. The semiconductor device of claim 3, wherein, The aforementioned structural portion also includes a field plate electrode electrically connected to the aforementioned upper electrode or the aforementioned gate electrode. The field plate electrode is located between the gate electrode and the silicon substrate.

5. The semiconductor device of claim 1, wherein, The silicon layer further includes a channel barrier of a first conductivity type disposed between the drift layer and the polysilicon portion, and having a first conductivity type impurity concentration higher than that of the drift layer.

6. The semiconductor device of claim 1, wherein, The heavy metal concentration in the drift layer in the region between the aforementioned unit region and the aforementioned polysilicon portion is higher than the heavy metal concentration in the drift layer in the region between the aforementioned polysilicon portion and the aforementioned side surface.

7. The semiconductor device of claim 1, wherein, The aforementioned heavy metal is Pt.

8. The semiconductor device of claim 1, wherein, The aforementioned heavy metal is Au.

9. The semiconductor device of claim 1, wherein, The aforementioned polysilicon portion has a first polysilicon portion and a second polysilicon portion located between the first polysilicon portion and the aforementioned side surface.

10. The semiconductor device of claim 9, wherein, The aforementioned gate electrode and the aforementioned gate insulating film are disposed within a structure embedded in the aforementioned silicon layer of the aforementioned unit region. The distance between the first polysilicon portion and the lower electrode is longer than the distance between the structural portion and the lower electrode.

11. The semiconductor device of claim 9, wherein, The distance between the second polysilicon portion and the lower electrode is shorter than the distance between the first polysilicon portion and the lower electrode.

12. The semiconductor device of claim 9, wherein, The first polysilicon portion and the second polysilicon portion continuously surround the unit region.

13. A semiconductor device, wherein, have: Upper electrode; Lower electrode; A silicon substrate of the first conductivity type is located between the upper electrode and the lower electrode and is in contact with the lower electrode. A silicon layer, located between the silicon substrate and the upper electrode, has a unit region, a side surface, and an end region located between the unit region and the side surface; A gate electrode is disposed in the aforementioned cell region of the aforementioned silicon layer; A gate insulating film is disposed between the gate electrode and the silicon layer; and The polycrystalline silicon portion, embedded in the aforementioned end region of the silicon layer, has a higher density of crystal grains than the silicon layer and contains heavy metals. The above silicon layer has: The drift layer of the first conductivity type is provided in the above-mentioned unit region and the above-mentioned end region. The impurity concentration of the first conductivity type is lower than that of the above-mentioned silicon substrate, and it contains heavy metals of the same type as those contained in the above-mentioned polysilicon portion. A second conductivity type substrate layer is disposed on the drift layer of the aforementioned unit region and is in contact with the aforementioned upper electrode; and The source layer of the first conductivity type is disposed on the aforementioned substrate layer and is in contact with the aforementioned upper electrode. The impurity concentration of the first conductivity type is higher than that of the aforementioned drift layer. The aforementioned end region does not include: the aforementioned base layer in contact with the aforementioned upper electrode, the aforementioned source layer in contact with the aforementioned upper electrode, and the aforementioned gate electrode. The aforementioned gate electrode and the aforementioned gate insulating film are disposed within a structure embedded in the aforementioned silicon layer of the aforementioned unit region. The distance between the polysilicon portion and the lower electrode is shorter than the distance between the structural portion and the lower electrode. The aforementioned polysilicon portion is in contact with the aforementioned drift layer in the aforementioned silicon layer. On the upper surface of the aforementioned end region, the aforementioned drift layer does not contact the aforementioned upper electrode, but is positioned opposite the aforementioned upper electrode through an insulating film.

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