A constant transconductance circuit for rail-to-rail amplifiers

Abstract

A constant transconductance circuit for rail-to-rail amplifier, by additionally adding a group B of two differential pairs on the basis of a group A of two differential pairs, tail current of the group A PMOS differential pairs is injected into the group A NMOS differential pairs through the group A current mirror, tail current of the group B NMOS differential pairs is injected into the group B PMOS differential pairs through the group B current mirror, the positive feedback loop formed by the current mirror and the tail current at low power supply voltage can be eliminated, so that the circuit can also work normally at low power supply voltage.

Description

Technical Field

[0007] ,

[0001] The present invention relates to the transconductance technology of rail-to-rail amplifiers, particularly a constant transconductance circuit for rail-to-rail amplifiers. By additionally adding two differential pairs in Group B based on two differential pairs in Group A, the tail current of the PMOS differential pair in Group A is injected into the NMOS differential pair in Group A through a current mirror in Group A, and the tail current of the NMOS differential pair in Group B is injected into the PMOS differential pair in Group B through a current mirror in Group B, it is possible to eliminate the positive feedback loop formed by the current mirror and the tail current under a low supply voltage, enabling the circuit to operate normally under a low supply voltage. Background Art

[0002] Rail-to-rail amplifiers usually achieve rail-to-rail input by paralleling PMOS differential pairs and NMOS differential pairs. When the common-mode input voltage is at the intermediate potential, both the PMOS and NMOS differential pairs are conducting simultaneously, and the input transconductance becomes twice that when a single differential pair is conducting. To keep the input transconductance constant over the entire common-mode input voltage range, traditional constant transconductance circuits use a triple current mirror to dynamically adjust the total current flowing into the differential pairs. However, when the supply voltage is relatively low, a positive feedback loop will form among the current mirror circuit, the tail currents of the NMOS and PMOS, and at this time the circuit cannot operate normally. Figure 2 It is a schematic diagram of a traditional constant transconductance circuit. Refer to Figure 2 As shown, where Mn1 and Mn2 form an NMOS differential pair, Mp1 and Mp2 form a PMOS differential pair, In and Ip are the tail current sources of the NMOS differential pair and the PMOS differential pair, and Vb1 and Vb2 are generated by a bias circuit.

[0003] For the case of Vb1 + Vb2 < Vdd:

[0004] 1) When Vb2 < Vcm < Vdd - Vb1, Mn5 and Mp5 are turned off, and both the NMOS differential pair and the PMOS differential pair are conducting simultaneously. At this time, the current mirror circuit is ineffective. To better describe the relationship of transconductance, it is assumed here that In is equal to Ip, and the product of the process parameters and dimensions of the NMOS and PMOS input pairs is equal. The input transconductance is given by the following formula:

[0005]

[0006] In the formula, W is the width of the MOS transistor, L is the length of the MOS transistor, I is the current, K and K' are both coefficients, the subscript n represents the NMOS transistor, the subscript p represents the PMOS transistor, gm represents the transconductance, and gmtot represents the total transconductance.

[0007] 2) When Vcm < Vb2, Mn5 conducts and Mp5 turns off. The NMOS differential pair is cut off and the PMOS differential pair conducts. The tail current of the NMOS differential pair is injected into the PMOS differential pair through the current mirrors Mp3 and Mp4. The current mirror replication ratio is N. The input transconductance at this time is given by the following formula. It can be seen that when N is equal to 3, a constant transconductance can be achieved.

[0008]

[0009] 3) When Vcm > Vdd - Vb1, Mn5 turns off and Mp5 conducts. The NMOS differential pair conducts and the PMOS differential pair is cut off. At this time, the input transconductance is equal to that when Vcm < Vb2.

[0010] For the case of Vb1 + Vb2 > Vdd, when Vdd - Vb1 < Vcm < Vb2, Mn5 and Mp5 conduct simultaneously. At this time, Mn3 - Mn5, Mp3 - Mp5, In, and Ip will form a positive feedback loop, and the circuit will not work properly. Summary of the Invention

[0011] In view of the defects or deficiencies in the prior art, the present invention provides a constant transconductance circuit for a rail-to-rail amplifier. By additionally adding two differential pairs in Group B on the basis of two differential pairs in Group A, the tail current of the PMOS differential pair in Group A is injected into the NMOS differential pair in Group A through the current mirror in Group A, and the tail current of the NMOS differential pair in Group B is injected into the PMOS differential pair in Group B through the current mirror in Group B, which can eliminate the positive feedback loop formed by the current mirror and the tail current under low power supply voltage, enabling the circuit to work properly under low power supply voltage.

[0012] The technical solution of the present invention is as follows:

[0013] A constant transconductance circuit for a rail-to-rail amplifier, characterized by comprising two differential pairs in group A and two differential pairs in group B, wherein the two differential pairs in group A are a group A PMOS differential pair and a group A NMOS differential pair, the tail current Ipa of the group A PMOS differential pair is injected into the group A NMOS differential pair through a group A current mirror, and the two differential pairs in group B are a group B NMOS differential pair and a group B PMOS differential pair, the tail current Inb of the group B NMOS differential pair is injected into the group B PMOS differential pair through a group B current mirror. In the S-differential pair, the first drain of the NMOS differential pair in group A and the first drain of the NMOS differential pair in group B are respectively connected to the first output terminal, the second drain of the NMOS differential pair in group A and the second drain of the NMOS differential pair in group B are respectively connected to the second output terminal, the first drain of the PMOS differential pair in group A and the first drain of the PMOS differential pair in group B are respectively connected to the fourth output terminal, and the second drain of the PMOS differential pair in group A and the second drain of the PMOS differential pair in group B are respectively connected to the third output terminal.

[0014] The A group of NMOS differential pairs includes NMOS transistors Mn1a (1a) and Mn2a (2a), and the A group of PMOS differential pairs includes PMOS transistors Mp1a (1a) and Mp2a (2a). The gates of Mn1a and Mp1a are interconnected and connected to the positive input voltage terminal Vin+. The gates of Mp2a and Mn2a are interconnected and connected to the negative input voltage terminal Vin-. The sources of Mn1a and Mn2a are interconnected and grounded through a tail current source Ina. The sources of Mp1a and Mp2a are interconnected and connected to the power supply voltage terminal VDD through a tail current source Ipa. The B group of NMOS differential pairs includes NMOS transistors Mn1b (1b) and Mn2b (2b). The B group of PMOS differential pairs... This includes PMOS transistors Mp1b (1b) and Mp2b (2b). The gates of Mn1b and Mp1b are interconnected and connected to the positive input voltage terminal Vin+. The gates of Mp2b and Mn2b are interconnected and connected to the negative input voltage terminal Vin-. The sources of Mn1b and Mn2b are interconnected and grounded through the tail current source Inb. The sources of Mp1b and Mp2b are interconnected and connected to the power supply voltage terminal VDD through the tail current source Ipb. The drains of Mn1a and Mn1b are connected to the first output terminal, the drains of Mn2a and Mn2b are connected to the second output terminal, the drains of Mp1a and Mp1b are connected to the fourth output terminal, and the drains of Mp2a and Mp2b are connected to the third output terminal.

[0015] The A-group current mirror includes a third NMOS transistor Mn3 and a fourth NMOS transistor Mn4 with gate interconnection. The sources of both Mn3 and Mn4 are grounded. The drain of Mn3 is grounded through the tail current source Ina. The gate and drain of Mn4 are interconnected and then connected to the drain of the fifth PMOS transistor Mp5. The source of Mp5 is connected to the power supply voltage terminal VDD through the tail current source Ipa. The gate of Mp5 is connected to the first bias voltage Vb1.

[0016] The first bias voltage Vb1 is generated by the bias circuit.

[0017] The sixth NMOS transistor, Mn6, has its source grounded via the tail current source Ina, its drain connected to VDD, and its gate connected to the second bias voltage Vb2. When the common-mode input voltage Vcm is low, Mn6 provides a freewheeling path for the tail current of the group A NMOS differential pair.

[0018] The second bias voltage Vb2 is generated by the bias circuit.

[0019] The B-group current mirror includes a third PMOS transistor Mp3 and a fourth PMOS transistor Mp4 with gate interconnection. The sources of both Mp3 and Mp4 are connected to VDD. The drain of Mp3 is connected to VDD through the tail current source Ipb. After the gate-drain interconnection of Mp4, it is connected to the drain of the fifth NMOS transistor Mn5. The source of Mn5 is grounded through the tail current source Inb. The gate of Mn5 is connected to the second bias voltage Vb2.

[0020] Including the sixth PMOS transistor Mp6, the source of Mp6 is connected to VDD through the tail current source Ipb, the drain of Mp6 is grounded, and the gate of Mp6 is connected to the first bias voltage Vb1. When the common-mode input voltage Vcm is high, Mp6 provides the freewheeling path for the tail current of the B group PMOS differential pair.

[0021] The technical effects of this invention are as follows: This invention provides a constant transconductance circuit for rail-to-rail amplifiers, which improves upon the traditional circuit by adding two additional differential pairs. The tail current of the PMOS differential pair in group A is injected into the NMOS differential pair in group A through a current mirror, and the tail current of the NMOS differential pair in group B is injected into the PMOS differential pair in group B through a current mirror, thereby eliminating the positive feedback loop.

[0022] The advantages of this invention compared to the prior art are: simple circuit structure, ingenious design, and the ability to operate normally under low power supply voltage. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a constant transconductance circuit for a rail-to-rail amplifier, which implements the present invention.

[0024] Figure 2 This is a schematic diagram of a traditional constant transconductance circuit.

[0025] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; GND - Ground terminal; Mn1~Mn6 - First NMOS transistors to sixth NMOS transistors; Mp1~Mp6 - First PMOS transistors to sixth PMOS transistors; Vb1~Vb2 - First bias voltage to second bias voltage; Mn1a~Mn2a - NMOS transistors 1a to 2a of the A group NMOS differential pair; Mp1a~Mp2a - PMOS transistors 1a to 2a of the A group PMOS differential pair; Mn1b~Mn2b - NMOS transistors of the B group S differential pair, NMOS transistors 1b to 2b; Mp1b to Mp2b-B group PMOS differential pair, PMOS transistors 1b to 2b; In-NMOS differential pair tail current source; Ip-PMOS differential pair tail current source; Ina-A group NMOS differential pair tail current source; Ipa-A group PMOS differential pair tail current source; Inb-B group NMOS differential pair tail current source; Ipb-B group PMOS differential pair tail current source; Vin+- positive input voltage terminal; Vin-- negative input voltage terminal. Detailed Implementation

[0026] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0027] Figure 1 This is a schematic diagram of a constant transconductance circuit for a rail-to-rail amplifier, implementing the present invention. (Reference) Figure 1 As shown, a constant transconductance circuit for a rail-to-rail amplifier includes two differential pairs in group A and two differential pairs in group B. The two differential pairs in group A are a PMOS differential pair and an NMOS differential pair. The tail current Ipa of the PMOS differential pair in group A is injected into the NMOS differential pair in group A through a current mirror in group A. The two differential pairs in group B are an NMOS differential pair and a PMOS differential pair in group B. The tail current Inb of the NMOS differential pair in group B is injected into the PMOS differential pair in group B through a current mirror in group B. In the differential pair, the first drain of the NMOS differential pair in group A and the first drain of the NMOS differential pair in group B are respectively connected to the first output terminal, the second drain of the NMOS differential pair in group A and the second drain of the NMOS differential pair in group B are respectively connected to the second output terminal, the first drain of the PMOS differential pair in group A and the first drain of the PMOS differential pair in group B are respectively connected to the fourth output terminal, and the second drain of the PMOS differential pair in group A and the second drain of the PMOS differential pair in group B are respectively connected to the third output terminal.

[0028] The A group of NMOS differential pairs includes NMOS transistors Mn1a (1a) and Mn2a (2a), and the A group of PMOS differential pairs includes PMOS transistors Mp1a (1a) and Mp2a (2a). The gates of Mn1a and Mp1a are interconnected and connected to the positive input voltage terminal Vin+. The gates of Mp2a and Mn2a are interconnected and connected to the negative input voltage terminal Vin-. The sources of Mn1a and Mn2a are interconnected and grounded through a tail current source Ina. The sources of Mp1a and Mp2a are interconnected and connected to the power supply voltage terminal VDD through a tail current source Ipa. The B group of NMOS differential pairs includes NMOS transistors Mn1b (1b) and Mn2b (2b). The B group of PMOS differential pairs... This includes PMOS transistors Mp1b (1b) and Mp2b (2b). The gates of Mn1b and Mp1b are interconnected and connected to the positive input voltage terminal Vin+. The gates of Mp2b and Mn2b are interconnected and connected to the negative input voltage terminal Vin-. The sources of Mn1b and Mn2b are interconnected and grounded through the tail current source Inb. The sources of Mp1b and Mp2b are interconnected and connected to the power supply voltage terminal VDD through the tail current source Ipb. The drains of Mn1a and Mn1b are connected to the first output terminal, the drains of Mn2a and Mn2b are connected to the second output terminal, the drains of Mp1a and Mp1b are connected to the fourth output terminal, and the drains of Mp2a and Mp2b are connected to the third output terminal.

[0029] The A-group current mirror includes a third NMOS transistor Mn3 and a fourth NMOS transistor Mn4 with interconnected gates. Both Mn3 and Mn4 have their sources grounded. The drain of Mn3 is grounded through a tail current source Ina. Mn4's gate-drain interconnect is connected to the drain of a fifth PMOS transistor Mp5. The source of Mp5 is connected to the power supply voltage VDD through a tail current source Ipa. The gate of Mp5 is connected to a first bias voltage Vb1, generated by a bias circuit. A sixth NMOS transistor Mn6 is also included. The source of Mn6 is grounded through a tail current source Ina. The drain of Mn6 is connected to VDD. The gate of Mn6 is connected to a second bias voltage Vb2. Mn6 provides a freewheeling path for the tail current of the A-group NMOS differential pair when the common-mode input voltage Vcm is low. The second bias voltage Vb2 is generated by a bias circuit. The B-group current mirror includes a third PMOS transistor Mp3 and a fourth PMOS transistor Mp4 with interconnected gates. The sources of both Mp3 and Mp4 are connected to VDD. The drain of Mp3 is connected to VDD via a tail current source Ipb. Mp4's gate-drain interconnect is then connected to the drain of a fifth NMOS transistor Mn5. The source of Mn5 is grounded via a tail current source Inb, and the gate of Mn5 is connected to a second bias voltage Vb2. A sixth PMOS transistor Mp6 is also included. The source of Mp6 is connected to VDD via a tail current source Ipb, and the drain of Mp6 is grounded. The gate of Mp6 is connected to a first bias voltage Vb1. Mp6 provides a freewheeling path for the tail current of the B-group PMOS differential pair when the common-mode input voltage Vcm is high.

[0030] Rail-to-rail amplifiers typically implement rail-to-rail input by connecting PMOS differential pairs and NMOS differential pairs in parallel. When the common-mode input voltage is at the mid-level, the input transconductance is twice that when the common-mode input voltage is near the rail potential. (See traditional constant transconductance circuits...) Figure 2 The previous method involved injecting the tail current of the PMOS differential pair into the NMOS differential pair through a 3x current mirror when the common-mode input voltage was close to the power rail; a similar process was performed when the common-mode input voltage was close to the ground rail. However, when the power supply voltage was relatively low, a positive feedback loop would form between the current mirror circuit and the tail currents of the NMOS and PMOS differential pairs. In this case, the circuit would not function properly, and the input transconductance would change significantly with the common-mode input voltage. This invention improves upon the traditional constant transconductance circuit by adding an additional PMOS and NMOS differential pair (group B) to the existing PMOS and NMOS differential pairs (group A). ​​The tail current of the group A PMOS differential pair is injected into the group A NMOS differential pair through a current mirror, and the tail current of the group B NMOS differential pair is injected into the group B PMOS differential pair through a current mirror. This eliminates the positive feedback loop between the current mirror and the tail current, ensuring that the input transconductance remains essentially unchanged with the common-mode input voltage. This invention... Figure 1As shown, where Mn1a, Mn2a, Mp1a, and Mp2a form a differential pair in Group A, and Mn1b, Mn2b, Mp1b, and Mp2b form a differential pair in Group B. The tail current of the PMOS differential pair in Group A is injected into the NMOS differential pair in Group A through a current mirror, and the tail current of the NMOS differential pair in Group B is injected into the PMOS differential pair in Group B through a current mirror. Mn6 provides a continuous conduction path for the tail current of the NMOS differential pair in Group A when Vcm is low, and Mp6 provides a continuous conduction path for the tail current of the PMOS differential pair in Group B when Vcm is high.

[0031] For the case of Vb1 + Vb2 < Vdd:

[0032] 1) When Vb2 < Vcm < Vdd - Vb1 (where Vdd is the power supply voltage and Vcm is the common-mode input voltage), Mn5 and Mp5 are both turned off, and the NMOS and PMOS differential pairs in both Group A and Group B are both conducting. At this time, the current mirror circuit is not functioning. To better represent the relationship of transconductance, it is assumed here that the currents of Ina, Ipa, Inb, and Ipb are all equal, and the product of the process parameters and dimensions of the NMOS and PMOS input pairs is equal. The input transconductance is given by the following formula:

[0033]

[0034] In the formula, W is the width of the MOS transistor, L is the length of the MOS transistor, I is the current, K and K' are both coefficients, the subscript n represents the NMOS transistor, the subscript p represents the PMOS transistor, gm represents the transconductance, gmtot represents the total transconductance, the subscript 1a represents the MOS transistor serial number of the differential pair in Group A, and the subscript 1b represents the MOS transistor serial number of the differential pair in Group B.

[0035] 2) When Vcm < Vb2, Mn5 is conducting and Mp5 is turned off. The NMOS differential pairs in both Group A and Group B are cut off, and the PMOS differential pairs are both conducting. The tail current of the NMOS differential pair in Group B is injected into the PMOS differential pair through the current mirrors Mp3 and Mp4, and the current mirror replication ratio is N. The input transconductance at this time is given by the following formula. It can be seen that when N is equal to 8, a constant transconductance can be achieved.

[0036]

[0037] 3) When Vcm > Vdd - Vb1, Mn5 is turned off and Mp5 is conducting. The NMOS differential pairs in both Group A and Group B are both conducting, and the PMOS differential pairs are both cut off. The tail current of the PMOS differential pair in Group A is injected into the NMOS differential pair through the current mirrors Mn3 and Mn4. At this time, the input transconductance is the same as when Vcm < Vb2.

[0038] For the case where Vb1 + Vb2 > Vdd, when Vdd - Vb1 < Vcm < Vb2, both Mn5 and Mp5 are conducting. In this design, the two current mirror circuits are divided into groups A and B. Since there is no relationship between the two groups of circuits, there is no positive feedback loop in the circuit, and the circuit can work properly throughout the rail-to-rail input. The constant transconductance can be achieved by adjusting the proportional relationship between Mn6, Mp6 and the differential pair.

[0039] The content not described in detail in the specification of the present invention belongs to the prior art well-known to those skilled in the art. It is hereby specified that the above description helps those skilled in the art to understand the present invention, but does not limit the protection scope of the present invention. Any implementation that is an equivalent replacement, modification, improvement, and / or simplification of the above description without departing from the substantial content of the present invention falls within the protection scope of the present invention.

Claims

1. A constant transconductance circuit for a rail-to-rail amplifier, characterized by, The A group two differential pairs and the B group two differential pairs, the A group two differential pairs are A group PMOS differential pair and A group NMOS differential pair, the tail current Ipa of the A group PMOS differential pair is injected into the A group NMOS differential pair through the A group current mirror, the B group two differential pairs are B group NMOS differential pair and B group PMOS differential pair, the tail current Inb of the B group NMOS differential pair is injected into the B group PMOS differential pair through the B group current mirror, the first drain of the A group NMOS differential pair and the first drain of the B group NMOS differential pair are connected with the first output end respectively, the second drain of the A group NMOS differential pair and the second drain of the B group NMOS differential pair are connected with the second output end respectively, the first drain of the A group PMOS differential pair and the first drain of the B group PMOS differential pair are connected with the fourth output end respectively, the second drain of the A group PMOS differential pair and the second drain of the B group PMOS differential pair are connected with the third output end respectively; The A group NMOS differential pair includes the 1a NMOS tube Mn1a and the 2a NMOS tube Mn2a, the A group PMOS differential pair includes the 1a PMOS tube Mp1a and the 2a PMOS tube Mp2a, the gate of Mn1a and Mp1a is interconnected and connected with the positive input voltage end Vin+, the gate of Mp2a and Mn2a is interconnected and connected with the negative input voltage end Vin-, the source of Mn1a and Mn2a is interconnected and grounded through the tail current source Ina, the source of Mp1a and Mp2a is interconnected and connected with the power voltage end VDD through the tail current source Ipa;The B group NMOS differential pair includes the 1b NMOS tube Mn1b and the 2b NMOS tube Mn2b, the B group PMOS differential pair includes the 1b PMOS tube Mp1b and the 2b PMOS tube Mp2b, the gate of Mn1b and Mp1b is interconnected and connected with the positive input voltage end Vin+, the gate of Mp2b and Mn2b is interconnected and connected with the negative input voltage end Vin-, the source of Mn1b and Mn2b is interconnected and grounded through the tail current source Inb, the source of Mp1b and Mp2b is interconnected and connected with the power voltage end VDD through the tail current source Ipb;The drain of Mn1a and the drain of Mn1b are connected with the first output end respectively, the drain of Mn2a and the drain of Mn2b are connected with the second output end respectively, the drain of Mp1a and the drain of Mp1b are connected with the fourth output end respectively, the drain of Mp2a and the drain of Mp2b are connected with the third output end respectively; The A group current mirror includes the third NMOS tube Mn3 and the fourth NMOS tube Mn4 which are interconnected, the source of Mn3 and Mn4 is grounded, the drain of Mn3 is grounded through the tail current source Ina, the gate and drain of Mn4 is interconnected and connected with the drain of the fifth PMOS tube Mp5, the source of Mp5 is connected with the power voltage end VDD through the tail current source Ipa, the gate of Mp5 is connected with the first bias voltage Vb1. The B group current mirror comprises a third PMOS tube Mp3 and a fourth PMOS tube Mp4 which are interconnected at the gate, the source of Mp3 and Mp4 is connected to VDD, the drain of Mp3 is connected to VDD through a tail current source Ipb, the drain of Mp4 is connected to the drain of a fifth NMOS tube Mn5 after being interconnected at the gate and drain, the source of Mn5 is connected to ground through a tail current source Inb, and the gate of Mn5 is connected to a second bias voltage Vb2.

2. The constant transconductance circuit for a rail-to-rail amplifier of claim 1, wherein, The first bias voltage Vb1 is generated by a bias circuit.

3. The constant transconductance circuit for a rail-to-rail amplifier of claim 1, wherein, The bias circuit comprises a sixth NMOS tube Mn6, the source of Mn6 is connected to ground through a tail current source Ina, the drain of Mn6 is connected to VDD, the gate of Mn6 is connected to the second bias voltage Vb2, and Mn6 provides a freewheeling path for the tail current of the A group NMOS differential pair when the common mode input voltage Vcm is low.

4. The constant transconductance circuit for a rail-to-rail amplifier of claim 3, wherein, The second bias voltage Vb2 is generated by a bias circuit.

5. The constant transconductance circuit for a rail-to-rail amplifier of claim 1, wherein, The bias circuit comprises a sixth PMOS tube Mp6, the source of Mp6 is connected to VDD through a tail current source Ipb, the drain of Mp6 is connected to ground, the gate of Mp6 is connected to the first bias voltage Vb1, and Mp6 provides a freewheeling path for the tail current of the B group PMOS differential pair when the common mode input voltage Vcm is high.

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