Decoder device for product code

Abstract

The present application provides a decoding device for product codes. The decoding device includes an input shift module, a storage module, a sub-decoding module, a soft information comparison module, an address allocation module, an early termination module, and an output shift module. Among them, the storage module uses a random access memory with a smaller area and lower power consumption as the storage unit. At the same time, the sub-decoding module adopts a partially parallel design, with fewer sub-decoders and a smaller hardware area, thus saving hardware resources and reducing hardware power consumption. Further, in order to ensure a high throughput with as small a hardware area as possible, the decoding device adopts an overlapping hardware architecture design, a skip circuit, and an early termination strategy, which greatly improves the overall decoding rate.

Description

Technical Field

[0001] This application relates to the field of communication decoding technology, and particularly to a decoding device for product codes. Background Art

[0002] A product code is a parallel concatenated block code with a codeword structure in the form of a two-dimensional matrix. The encoding process of the product code is to arrange the input information bits in the form of a two-dimensional matrix, then use the first component code to encode the information bits in the row direction, and then use the second component code to encode the information bits in the column direction to obtain the product codeword for channel transmission. The product code can be said to be the first forward error correction code that achieves error-free transmission at a non-zero code rate after the Shannon information theory was proposed. Currently, product codes are widely used in scenarios such as the IEEE802.16 standard, satellite communication standards, deep space communication, and large data transmission in digital storage systems.

[0003] The decoding process of the product code is to perform multiple iterative decodings on the product code matrix row by row and column by column. Among them, when decoding the row code, the decoding algorithm corresponding to the component code in the row direction is used, and when decoding the column code, the decoding algorithm corresponding to the component code in the column direction is used. In a complete row-column decoding iteration process, a complete decoding process for the codewords in the row direction or a complete decoding process for the codewords in the column direction is called a semi-iteration process, that is, a single-iteration decoding process, including the semi-iteration decoding process in the row direction and the semi-iteration decoding process in the column direction.

[0004] Currently, many specific decoding algorithms for product codes have been proposed and corresponding decoding devices have been implemented. Among them, when the component code is a BCH (Bose–Chaudhuri–Hocquenghem) code, a decoding device based on the Soft-Assisted Iterative Bounded Distance Decoding (SA-iBDD) algorithm has been studied. This decoding device adopts a fully parallel architecture, bringing the benefit of high throughput. However, because the decoding device with a fully parallel architecture needs to complete all data storage / retrieval operations within the same clock cycle, the memory in the decoding device can only use registers with large area and high power consumption, resulting in a large hardware area and high power consumption for the decoding device with a fully parallel architecture. Summary of the Invention

[0005] To solve the problems of large hardware area and high power consumption of the existing product code decoding device with a fully parallel architecture, this application provides a decoding device for product codes in the following aspects.

[0006] The first aspect of the present application provides a decoding device for product codes, including an input shift module, a storage module, a sub-decoding module, a soft information comparison module, an address allocation module, an early termination module, and an output shift module;

[0007] The input end of the input shift module serves as the input end of the decoding device, and is used to receive the input codeword to be decoded, shift the codeword to be decoded to obtain the shifted codeword, and output the shifted codeword to the storage module;

[0008] The storage module is used to store the shifted codeword and the temporary decoding result. The storage module includes a first number of random access memories;

[0009] The sub-decoding module is used to read the shifted codeword or the temporary decoding result from the storage module for decoding to obtain an intermediate decoding result, and output the intermediate decoding result to the soft information comparison module and the output shift module respectively. Among them, the sub-decoding module includes a second number of sub-decoders, and the second number is less than the code length of the component code of the codeword to be decoded;

[0010] The soft information comparison module is used to obtain a temporary decoding result according to the preset soft information and the intermediate decoding result, and transmit it to the address allocation module;

[0011] The address allocation module is used to compare the temporary decoding result with the temporary decoding result of the previous semi-iteration process to obtain a jump address, and send it to the storage module. The jump address is used to indicate the row or column address that the sub-decoding module reads from the storage module in the next semi-iteration process;

[0012] The sub-decoding module is further used to output a decoding result judgment value to the early termination module. The decoding result judgment value includes a first decoding result judgment value, and the first decoding result judgment value is used to indicate that there is no error bit in the row codeword or column codeword of the data read by the sub-decoding module;

[0013] The early termination module is used to count a third number, where the third number is the number of the first decoding result judgment values output by the sub-decoding module;

[0014] The output shift module is used to store the decoded result codeword, receive the intermediate decoding result, and shift the intermediate decoding result to update the decoded result codeword;

[0015] When the third number is equal to the number of rows or columns of the product code, the early termination module is used to output a stop signal to the sub-decoding module, and the output shift module outputs the decoded result codeword.

[0016] Optionally, the soft information comparison module includes a register, a comparator connected to the register, and a first counter connected to the comparator. Among them,

[0017] The register is used to store preset soft information;

[0018] The comparator is used to compare all the flipped bit positions in the target intermediate decoding result with the preset soft information, where the target intermediate decoding result is the output data of the sub-decoding module for the target column or the target row in the current half-iteration decoding process;

[0019] The first counter is used to count the fourth quantity and select to output the data input to the sub-decoding module or the data output by the sub-decoding module according to the fourth quantity; where, when the fourth quantity is less than or equal to the preset comparison threshold, the first counter selects to output the data output by the sub-decoding module, and when the fourth quantity is greater than the preset comparison threshold, the first counter selects to output the data input to the sub-decoding module, where the fourth quantity is the number of bit positions with a value of 1 in the corresponding preset soft information among all the flipped bit positions in the target intermediate decoding result.

[0020] Optionally, when the channel information of the target bit position of the product code is less than the preset reliability threshold, the preset soft information corresponding to the target bit position is set to 0;

[0021] When the channel information of the target bit position of the product code is greater than or equal to the preset reliability threshold, the preset soft information corresponding to the target bit position is set to 1; where the target bit position is any bit position in the product code.

[0022] Optionally, the sub-decoding module adopts an overlapping working mode.

[0023] Optionally, each column or each row in the temporary decoding result is divided into n / p positioning groups, where n is the code length in the column direction or the row direction of the product code, and p is the number of sub-decoders in the sub-decoding module;

[0024] If the current half-iteration process performs column decoding, the address allocation module calculates the jump address according to the following calculation method:

[0025]

[0026] where, x represents the jump address, n is the code length of the component code of the product code, j represents the address of the positioning group where the flipped bit position is located, and i represents the address of the flipped bit position in the storage module;

[0027] If the current half-iteration process performs row decoding, the address allocation module calculates the jump address according to the following calculation method:

[0028] x = j + i + 1 (mod n / p),

[0029] Where, x represents the jump address, n is the code length of the component code of the product code, j represents the address of the positioning group where the flipped bit is located, and i represents the address of the flipped bit in the storage module.

[0030] Optionally, the address allocation module includes a multiplexer.

[0031] Optionally, the early termination module includes a second counter and an AND gate circuit connected to the second counter;

[0032] The second counter is used to determine the number of values according to the first decoding result output by the sub-decoding module, and obtain the third quantity;

[0033] The initial values of the first enable signal and the second enable signal of the AND gate circuit are both 1. When the third quantity is equal to the number of rows or columns of the product code, the second enable signal is set to 0; the output end of the AND gate circuit is connected to the input end of the sub-decoding module.

[0034] Optionally, the code device further includes a first intermediate shift module and a second intermediate shift module;

[0035] Among them, the input end of the first intermediate shift module is connected to the output end of the storage module, and the output end of the first intermediate shift module is connected to the input end of the sub-decoding module;

[0036] The input end of the second intermediate shift module is connected to the output end of the soft information comparison module, and the output end of the second intermediate shift module is connected to the input end of the address allocation module.

[0037] Optionally, both the input shift module and the output shift module are barrel shift registers.

[0038] Optionally, both the first intermediate shift module and the second intermediate shift module are barrel shift registers.

[0039] This application provides a decoding device for a product code. The decoding device includes an input shift module, a storage module, a sub-decoding module, a soft information comparison module, an address allocation module, an early termination module, and an output shift module. Among them, the storage module uses a random access memory with a smaller area and lower power consumption as the storage unit. At the same time, the sub-decoding module adopts a partially parallel design, with fewer sub-decoders, smaller hardware area, thus saving hardware resources and reducing hardware power consumption. Further, in order to ensure a higher throughput with as small a hardware area as possible, the decoding device adopts an overlapping hardware architecture design, a jump circuit, and an early termination strategy, which greatly improves the overall decoding rate. Description of the Drawings

[0040] Figure 1 It is a schematic structural diagram of a decoding device for a product code provided by an embodiment of this application;

[0041] Figure 2 Schematic diagram of the storage state of the shifted codeword in the storage module of a decoding device for product code provided by an embodiment of the present application;

[0042] Figure 3 Schematic diagram of the decoding cycle when the sub - decoding module in a decoding device for product code provided by an embodiment of the present application adopts an overlapping working mode;

[0043] Figure 4 Schematic diagram of the structure of the soft - information comparison module in a decoding device for product code provided by an embodiment of the present application in one implementation manner;

[0044] Figure 5 Schematic diagram of the structure of the address allocation module in a decoding device for product code provided by an embodiment of the present application in one implementation manner;

[0045] Figure 6 Schematic diagram of the structure of the early - termination module in a decoding device for product code provided by an embodiment of the present application in one implementation manner. Detailed implementation manners

[0046] In the present application, taking the input product - code word as (n, k, t) 2 to illustrate the working process of the decoding device for the product code provided by the present application, where n represents the code length of the component code, k represents the information - bit length, and t represents the error - correction ability of the sub - code. It should be noted that the two component codes of the product code usually use the same code word, but they can also use different code words, and only the corresponding sub - decoders in the sub - decoder group need to be used during row and column decoding.

[0047] See Figure 1 , a decoding device for product code provided by the first embodiment of the present application includes: an input shift module, a storage module, a sub - decoding module, a soft - information comparison module, an address allocation module, an early - termination module, and an output shift module.

[0048] The input end of the input shift module serves as the input end of the decoding device, and is used to receive the input code word to be decoded, shift the code word to be decoded to obtain a shifted code word, and output the shifted code word to the storage module.

[0049] In the decoding process of the product code, assuming that decoding is performed in the order of row decoding first and then column decoding, there is a very troublesome problem for the sub-decoding module, that is, the memory access conflict problem. Therefore, for the decoding device of the product code provided in this embodiment, in order to ensure that when performing row-column decoding, the sub-decoding module can read multiple rows or multiple columns of codewords simultaneously, the input shift module is used to shift the codewords to be decoded to obtain the shifted codewords, which are stored in the storage module.

[0050] See Figure 2 , the storage module in the decoding device provided in this embodiment includes y random access memories (Random Access Memory, RAM), and the depth of each RAM is x. Then the storage order of the data in the storage module is as Figure 2 shown in (a) of, where y is the first quantity. First, it is shifted by the input shift module, and then the data is stored in the storage module. The storage order of the data is as Figure 2 shown in (b) of.

[0051] In some embodiments, the input shift module uses a barrel shifter. Compared with the subsequent sub-decoding module, the hardware area occupied by the barrel shifter is almost negligible.

[0052] The storage module is used to store the shifted codewords and to store temporary decoding results. The storage module includes a first number of random access memories. In this embodiment, the storage module includes y RAMs. Among them, the temporary decoding result is the result after a complete row half-iteration or column half-iteration decoding of the decoding device.

[0053] The sub-decoding module is used to read the shifted codewords or the temporary decoding results from the storage module for decoding to obtain intermediate decoding results, and output the intermediate decoding results to the soft information comparison module and the output shift module respectively. Among them, the sub-decoding module includes a second number of sub-decoders, and the second number is less than the code length of the component code of the codewords to be decoded. That is, the decoding device of this embodiment is a partially parallel architecture. Each time the sub-decoding module can only read p rows or p columns of codewords from the storage module, and n / p decoding stages are required to complete one half-iteration, where p is the second number.

[0054] In this embodiment, the sub-decoding module includes p sub-decoders. It should be noted that the code length n of the component code of the product code needs to be divisible by p and y. If n cannot be divisible, some redundancy needs to be added to the codewords, and the added redundancy does not participate in decoding.

[0055] In this embodiment, a mode where p sub-decoders work in parallel is adopted, which means that n / p decoding stages (1 decoding stage is equal to T clock cycles) are required to complete a semi-iterative decoding in the row direction or a semi-iterative decoding in the column direction. If the decoding for each cycle is performed serially, not only will a huge time delay be generated, but also a certain degree of hardware waste will be caused.

[0056] Therefore, in this embodiment, the sub-decoding module adopts an overlapping working mode, that is, an overlapping design is adopted for different decoding stages, so that after the previous decoding stage has been carried out for one clock cycle, the next decoding stage can start, resulting in the work that originally required clock cycles to complete can be completed within n / p + T - 1 clock cycles, and the decoding rate has been greatly improved. Refer to Figure 3 , taking T = 7 as an example, to illustrate the specific operation timing of the sub-decoding module after adopting the overlapping design.

[0057] The soft information comparison module is used to obtain the temporary decoding result according to the preset soft information and the intermediate decoding result, and transmit it to the address allocation module.

[0058] In a fiber optic receiver based on a Digital Signal Processor (DSP), soft information is usually available. After receiving the hard-decided codeword to be decoded from the channel, the codeword to be decoded can be compared with the channel information. Assuming that the channel information for each bit of the codeword is L and the threshold is set to r, when |L| < r, we store the preset soft information corresponding to the bit as 0, indicating that the reliability of this bit is not high; on the contrary, the corresponding preset soft information is stored as 1, regarding it as a bit with higher reliability.

[0059] After this special form of preset soft information is stored, the formal decoding process can start and no value needs to be changed thereafter. After each successful decoding by the sub-decoder group, the soft information comparison module will compare and count the output codeword with the pre-stored soft information to determine whether to accept or reject this decoding.

[0060] Exemplarily, when and only when a group of sub-decoding modules successfully decodes, first, count all the flipped bit positions in the output data of the sub-decoding modules, compare them with the stored preset soft information, first count the number of "1"s in the preset soft information corresponding to these bit positions to obtain a fourth quantity, and set a preset comparison threshold to M. It should be noted that when counting the fourth quantity, it is for the bit positions with a value of 1 in the preset soft information corresponding to the flipped bit positions in a certain row or a certain column. If the fourth quantity is not greater than this threshold, it is considered that the current decoding is successful and this result is accepted. Otherwise, it is considered that the sub-decoding module has flipped too many bit positions with high reliability during decoding, resulting in misdecoding, and thus the current decoding result is rejected. That is to say, the soft information comparison module compares the flipped bit positions with the preset soft information row by row or column by column to determine whether to accept the decoding result of this row or this column.

[0061] In some embodiments, the soft information comparison module includes a register, a comparator, and a first counter. Refer to Figure 4 , which is a schematic structural diagram of the soft information comparison module in an implementation manner of the decoding device provided in the embodiment of the present application.

[0062] The register is used to store the preset soft information.

[0063] The comparator is used to compare all the flipped bit positions in the target intermediate decoding result with the preset soft information, where the target intermediate decoding result is the output data of the sub-decoding module for the target row or the target column in the current semi-iteration process.

[0064] The first counter is used to count the fourth quantity and select to output the data input to the sub-decoding module or the data output by the sub-decoding module according to the fourth quantity; where when the fourth quantity is less than or equal to the preset comparison threshold, the first counter selects to output the data output by the sub-decoding module, and when the fourth quantity is greater than the preset comparison threshold, the first counter selects to output the data input to the sub-decoding module, where the fourth quantity is the number of bit positions with a value of 1 in the preset soft information corresponding to all the flipped bit positions in the target intermediate decoding result.

[0065] Exemplarily, for the first row, during the decoding process of a sub-decoding module at a certain time, the input codeword of the sub-decoding module is R, and the output codeword is C. The comparator compares the output codeword C with the preset soft information, and counts the number of bit positions (i.e., the fourth quantity) corresponding to the preset soft information with a value of 1 for the flipped bit positions in the output codeword C. The preset comparison threshold M is set to 1. When the fourth quantity is greater than 1, the soft information comparison module outputs the input codeword R to the address allocation module; when the fourth quantity is less than or equal to 1, the soft information comparison module outputs the output codeword C to the address allocation module. That is to say, when there is 1 highly reliable bit position flipped in the output codeword C, it is considered that the decoding process is unreliable, there is a misdecoding, and the decoding result of this time is not accepted.

[0066] The address allocation module is used to compare the temporary decoding result with the temporary decoding result of the previous semi-iteration process to obtain a jump address, and send it to the storage module, where the jump address is used to indicate the row or column address that the sub-decoding module reads from the storage module in the next semi-iteration process. In this embodiment, the address allocation module is a jump circuit.

[0067] The decoding device of this embodiment follows the decoding order of row first and column second, and must perform a complete row-column iterative decoding first. After the row decoding of the second iteration starts, the address allocation module will record the row (column) addresses changed by the sub-decoding module during the previous semi-iteration, and perform decoding on these rows (columns) during this semi-iteration, and this is also the essence of the operation of the jump circuit.

[0068] See Figure 5 , which is the structural schematic diagram of the address allocation module provided by this embodiment. In this embodiment, the address allocation module can be implemented using a multiplexer.

[0069] First, a complete row-column decoding must be performed to ensure that correct row or column codewords can be skipped and rows or columns that need further decoding can be selected during the subsequent iterative decoding process. This is the basic condition for the normal operation of the jump circuit. It should be noted that a correct row or column codeword means that there is no error codeword in this row or column and no decoding is required. In the next semi-iteration process, the rows or columns that need to be decoded refer to the bit positions that have been successfully decoded (flipped) during this semi-iteration process. In the next semi-iteration process, for the rows or columns where these flipped bit positions are located, the decoding process is executed. Assume that the current semi-iteration decoding process is a row decoding process, and the successfully flipped bit position is O. Then in the next semi-iteration process, which is a column decoding process, decoding is performed on the column where the bit position O is located.

[0070] Since this embodiment adopts p sub-decoders operating in parallel, each p rows (columns) will be divided into a group, and each group is recorded as the i-th group (i=0, 1, 2...p-1), where i also represents the address number of the codeword stored in the corresponding RAM.

[0071] In each half-iteration after the first iteration of column decoding begins, when p rows (columns) in a group are successfully decoded, the positions of the flipped bits are recorded. There are n possible positions for each flipped bit. To facilitate storage of these positions, the rows or columns are also divided into n / p groups. That is, each column or row in the temporary decoding result is divided into n / p positioning groups; each positioning group contains p positions, and each group is denoted as group j (j = 0, 1, 2…p-1). The advantage of this is that after each successful decoding, only the RAM address read during the decoding process needs to be recorded. Due to the shift storage, the RAM address read this time is simply converted to the address to be read from the RAM for the next half-iteration decoding. In other words, starting from the first iteration of column decoding, only the RAM address to be read for the next half-iteration needs to be stored. When row and column decoding alternate, only one additional clock cycle is required to allocate the address. The specific address conversion rules are as follows:

[0072] If the current semi-iterative process performs column decoding, the address allocation module calculates the jump address in the following manner:

[0073]

[0074] Among them, x represents the jump address, n is the component code length of the product code, j represents the address of the positioning group where the flipped bit is located, and i represents the address of the flipped bit in the storage module, that is, the address of the RAM where it is located.

[0075] If the current semi-iterative process performs row decoding, the address allocation module calculates the jump address in the following manner:

[0076] x=j+i+1×(mod n / p),

[0077] Among them, x represents the jump address, n is the component code length of the product code, j represents the address of the positioning group where the flipped bit is located, and i represents the address of the flipped bit in the storage module, that is, the address of the RAM where it is located.

[0078] The address allocation module provided in this embodiment records the addresses of rows or columns that are successfully decoded in a certain half iteration, and decodes only these rows or columns in the next half iteration, thereby -15 In this case, the decoding rate can be increased by nearly half.

[0079] The sub - decoding module is further configured to output a decoding result judgment value to the early termination module. The decoding result judgment value includes a first decoding result judgment value, where the first decoding result judgment value is used to indicate that there are no error bits in the row codeword or column codeword in the data read by the sub - decoding module. The early termination module is used to count a third quantity, where the third quantity is the number of the first decoding result judgment values output by the sub - decoding module.

[0080] In the actual decoding process, not all codewords need to go through a complete iteration to be decoded successfully. Therefore, when all codewords have no errors, if a determination condition can be set to terminate the decoding in time when there is no need to continue the iteration, resulting in a reduction in the actual number of decoding iterations, the overall decoding rate can still be guaranteed to increase. Therefore, this embodiment adds an early termination function to the decoding device.

[0081] When the sub - decoder works, different results will be obtained according to different input codewords. According to whether the decoding is successful, the output results can be roughly divided into the following three cases. The sub - decoder block adopted in this embodiment will output different output decoding result judgment values corresponding to these three cases:

[0082] The first decoding result judgment value Flag0: The sub - decoder determines that there are no error bits in the input codeword;

[0083] The second decoding result judgment value Flag1: The input codeword is successfully decoded;

[0084] The third decoding result judgment value Flag2: The number of error bits in the input codeword exceeds the error - correcting ability of the sub - decoder, the decoding fails, and the input codeword remains unchanged.

[0085] According to the above three cases, the corresponding early termination situation can be considered starting from whether the decoder successfully decodes in a certain iteration process. According to software simulation, when the determination condition is that all sub - decoders output Flag0, it means that in a certain semi - iteration, the sub - decoder determines that all codewords have no error bits. If the decoding is stopped at this time, it will not have much impact on the final decoding accuracy.

[0086] See Figure 6 , which is a schematic structural diagram of the early termination module provided in this embodiment. In this embodiment, the early termination module includes a second counter and an AND - gate circuit connected to the second counter.

[0087] The second counter is used to obtain the third quantity according to the number of the first decoding result judgment values output by the sub - decoding module.

[0088] The initial values of the first enable signal and the second enable signal of the AND gate circuit are both 1. When the third quantity is equal to the number of rows or columns of the product code, the second enable signal is set to 0; the output end of the AND gate circuit is connected to the input end of the sub-decoder module.

[0089] That is to say, initially setting the enable signals E1 and E to 1 ensures the normal operation of the sub-decoder (the enable signal E is always set to 1). For one semi-iteration, there are a total of n rows or columns to be decoded. Therefore, there will be a total of n outputs (because it is p sub-decoders in parallel, so it takes n / p cycles to complete one semi-iteration, but finally there will be n outputs). When and only when n flag0s are output, the enable signal E1 is set to 0, and after passing through the AND gate with the enable signal E, it is set to 0, causing the sub-decoder module to stop working and achieving the effect of early termination.

[0090] The early termination module provided in this embodiment realizes the early termination function for the iterative decoding process according to the decoding result judgment value output by the sub-decoder module, so that the decoding process can be terminated when the sub-decoder module determines that all codewords are error-free in any iteration cycle, thereby omitting unnecessary decoding cycles and further improving the decoding rate.

[0091] The output shift module is used to store the decoded result codeword, receive the intermediate decoding result, and shift the intermediate decoding result to update the decoded result codeword.

[0092] Regardless of whether the decoding process is terminated early, the final output codeword must go through a barrel shift register again so that the codeword stored in the storage module is restored to the original format before it can be output. In this embodiment, the output shift module can adopt a barrel shift register. The output shift module is the output end of the decoding device.

[0093] After the output shift module receives the intermediate decoding result output by the sub-decoder module, it shifts the intermediate decoding result to obtain the decoded result codeword. In the next semi-iteration process, it shifts the received intermediate decoding result again to update the decoded result codeword. Because there is an address allocation module, starting from the second iteration process, the codeword to be decoded is not the size of the entire codeword, but only the rows or columns where the successfully decoded bits were located in the previous semi-iteration process. Correspondingly, only the corresponding columns or rows in the decoded result codeword need to be updated according to the current intermediate decoding result.

[0094] When the third quantity is equal to the number of rows or columns of the product code, the early termination module is used to output a stop signal to the sub-decoder module, and the output shift module outputs the decoded result codeword.

[0095] This embodiment provides a decoding device for product codes. The device adopts a partially parallel architecture design. Compared with the decoding device with a fully parallel architecture, a random access memory with a smaller area and lower power consumption can be used as a storage unit. At the same time, the sub-decoding module adopts a partially parallel design, with fewer sub-decoders and a smaller hardware area, thus saving hardware resources and reducing hardware power consumption.

[0096] Furthermore, in order to ensure a high throughput with as small a hardware area as possible, the decoding device adopts a hardware architecture design with an overlapping method, a skip circuit, and an early termination strategy, which greatly improves the overall decoding rate.

[0097] It should be noted that the component codes of the product codes supported by the decoding device for product codes provided in the first embodiment of this application need to have a cyclic property. A codeword with a cyclic property remains another codeword after such cyclic shift and can still be decoded. However, a codeword without a cyclic property may have a decoding error after cyclic shift, so it must be restored to its original format before decoding. Considering that in practical applications, some component codes of product codes do not have a cyclic property, for this reason, the second embodiment of this application provides another decoding device for product codes.

[0098] Another decoding device for product codes provided in the second embodiment of this application is different from the decoding device provided in the first embodiment of this application in that a first intermediate shift module is further included between the storage module and the sub-decoding module, and a second intermediate shift module is further included between the soft information comparison module and the address allocation module.

[0099] In an implementation manner of the second embodiment of this application, both the first intermediate shift module and the second intermediate shift module can adopt barrel shift registers.

[0100] The beneficial effects of implementing the second embodiment of this application can refer to the description in the first embodiment of this application and will not be elaborated here.

[0101] To better illustrate the hardware architecture and working process of the decoding device for product codes provided in this embodiment, the following makes a further exemplary description in combination with specific product codewords.

[0102] Exemplarily, for a product code with BCH(255, 231, 3) used for both rows and columns, the proposed partially parallel decoding device in this application requires y = 32 RAM units with a depth of 32 and a width of 64 as a storage module, and p = 8 BCH sub-decoders as a group of parallel working sub-decoding modules.

[0103] Since the component code length of the above product code is 255 and it is not divisible by 32 and 8, in order to facilitate grouping, first add 1 bit of redundancy to the original BCH component code with a length of 255. This 1 bit of redundancy does not participate in the BCH decoding process, so that the original 255×255 matrix becomes a 256×256 matrix. Then divide the 256×256 matrix into 32×32 sub-matrix blocks of 8×8, and store these sub-matrix blocks in 32 RAMs respectively. Each sub-matrix block contains 64-bit data, and every 8 columns of data of the product codeword are stored in one RAM. The present application uses a mode where 8 BCH decoders work in parallel, which means that 32 decoding cycles (1 decoding cycle is equal to 7 clock cycles) are required to complete one iteration. If the decoding of each cycle is performed serially, not only will there be a huge time delay, but also a certain degree of hardware waste will be caused. Therefore, the present application also adds a pipeline design, so that the work that originally took 32×7 clock cycles to complete can be completed within 38 clock cycles, and the decoding efficiency is greatly improved.

[0104] After receiving the codeword to be decoded that has undergone hard decision from the channel, the codeword to be decoded can be compared with the channel information. Assume that the channel information for each bit of the codeword is L, and assume that the threshold is 0.45. When |L| < 0.45, store the corresponding preset soft information of the corresponding bit as 0, which means that the reliability of this bit is not high. On the contrary, store the corresponding preset soft information as 1 and regard it as a bit with higher reliability.

[0105] After this special form of preset soft information is stored, the formal decoding process can start and no value needs to be changed thereafter. When and only when a sub-decoding module successfully decodes, first count all the flipped bits in the decoding result of the sub-decoding module and compare it with the stored preset soft information. First count the number of "1"s in the corresponding preset soft information among the flipped bits, and set the preset comparison threshold to 1. If the counting result is not greater than this threshold, it is considered that the decoding is successful this time and accept this decoding result. Otherwise, it is considered that too many bits with high reliability have been flipped in this decoding, resulting in misdecoding, so the decoding result this time is rejected.

[0106] After that, the jump circuit (that is, the address allocation module) starts to work. It should be noted that a complete row-column decoding needs to be performed first to ensure that correct rows or column codewords can be skipped and the rows or columns that need further decoding can be selected during the subsequent iterative decoding process. This is the basic condition for the normal operation of the jump circuit.

[0107] Since this example uses eight BCH decoders operating in parallel, each eight rows (columns) must be grouped together. Therefore, the 256 rows (columns) are divided into 32 groups. For example, rows (columns) 1-8 are group 0, rows (columns) 9-16 are group 1. In each half-iteration after the first iteration of column decoding, when eight rows (columns) in a group are successfully decoded, the flipped bit position is recorded. There are 256 possible bit positions. To conveniently store these positions, each column or row is also divided into 32 positioning groups, each containing eight positions. For example, if the flipped bit position during row (column) decoding is 7, it is recorded as group 0; if the flipped bit position is 12, it is recorded as group 1. In other words, starting from the first iteration of column decoding, only the RAM address to be read in the next half-iteration needs to be stored. When alternating between row and column decoding, only one additional clock cycle is required to allocate the address.

[0108] After each half-iteration, the early termination module determines whether the decoding has reached the termination condition. Since the product code used in this example has a code length of 255*255, when the number of Flag0 counted by the early termination module counter reaches 255, it indicates that the decoding can be terminated early. Otherwise, the next half-iteration decoding will continue.

[0109] In order to further demonstrate the performance advantages of the product code decoding device provided by this application, this application uses Verilog language to write relevant codes for comprehensive simulation. Table 1 shows the experimental values after normalization of different processes.

[0110] Among them, Scheme ① is a decoding device designed with a fully parallel hardware architecture, which is simulated under a 28nm process. Scheme ② is a partially parallel decoding device, but no jump circuit (i.e., address allocation module) is designed, and the sub-decoding module does not adopt an overlapping working mode, which is simulated under a 55nm process. Scheme ③ is a partially parallel decoding device, which does not design a jump circuit, and the sub-decoding module adopts an overlapping working mode, which is simulated under a 55nm process. Scheme ④ is the partially parallel decoding device provided in the first embodiment of this application, that is, a jump circuit is designed and the sub-decoding module adopts an overlapping working mode, which is simulated under a 55nm process.

[0111] As can be seen from Table 1, under actual working conditions (bit error performance reaches 10 -15 The partially parallel decoder architecture provided by this application can achieve throughput similar to that of a fully parallel architecture using a smaller hardware area. Furthermore, the hardware efficiency of the decoding device provided by this application (i.e., the ratio of average throughput to logic gate count) is approximately 6.7 times higher than that of previous fully parallel decoders.

[0112] Table 1: Experimental data of different decoding devices

[0113]

[0114] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the disclosed application. The present application aims to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include the well-known common knowledge or conventional technical means in the technical field disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims of the present application.

[0115] For the similar and identical parts between the various embodiments in this specification, reference may be made to each other.

Claims

1. A decoding device for a product code, characterized in that: include: Input shift module, storage module, sub-decoding module, soft information comparison module, address allocation module, early termination module and output shift module; The input end of the input shift module serves as the input end of the decoding device, and is used to receive an input codeword to be decoded, shift the codeword to be decoded to obtain a shifted codeword, and output the shifted codeword to the storage module; The storage module is used to store the shifted codeword and to store a temporary decoding result, and the storage module includes a first number of random access memories; The sub-decoding module is configured to read the shifted codeword or the temporary decoding result from the storage module for decoding to obtain an intermediate decoding result, and output the intermediate decoding result to the soft information comparison module and the output shift module, respectively, wherein the sub-decoding module includes a second number of sub-decoders, where the second number is less than the code length of the component code of the codeword to be decoded, and the sub-decoding module adopts an overlapping working mode; The soft information comparison module is used to obtain the temporary decoding result according to the preset soft information and the intermediate decoding result, and transmit the temporary decoding result to the address allocation module; The soft information comparison module includes a register, a comparator connected to the register, and a first counter connected to the comparator, wherein: The register is used to store the preset soft information; The comparator is configured to compare all flipped bits in a target intermediate decoding result with the preset soft information, wherein the target intermediate decoding result is output data of the sub-decoding module for the target column or target row in this half-iteration process; The first counter is configured to count a fourth number and select, based on the fourth number, to output data input by the sub-decoding module or data output by the sub-decoding module; when the fourth number is less than or equal to a preset comparison threshold, the first counter selects to output the data output by the sub-decoding module; and when the fourth number is greater than the preset comparison threshold, the first counter selects to output the data input by the sub-decoding module, wherein the fourth number is the number of bits having a value of 1 in the preset soft information corresponding to all flipped bits in the target intermediate decoding result; The address allocation module is configured to compare the temporary decoding result with the temporary decoding result of the previous semi-iterative process to obtain a jump address, and send the jump address to the storage module, wherein the jump address is used to indicate the row or column address to be read from the storage module by the sub-decoding module in the next semi-iterative process; Divide each column or each row in the temporary decoding result into n / p positioning groups, where n is the code length in the column direction or the code length in the row direction of the product code, and p is the number of sub-decoders in the sub-decoding module; If the current semi-iterative process performs column decoding, the address allocation module calculates the jump address in the following manner: Wherein, x represents the jump address, n is the component code length of the product code, j represents the address of the positioning group where the flipped bit is located, and i represents the address of the flipped bit in the storage module; If the current semi-iterative process performs row decoding, the address allocation module calculates the jump address in the following manner: x=j+i+1×(mod n / p), Wherein, x represents the jump address, n is the component code length of the product code, j represents the address of the positioning group where the flipped bit is located, and i represents the address of the flipped bit in the storage module; The sub-decoding module is further configured to output a decoding result judgment value to the early termination module, wherein the decoding result judgment value includes a first decoding result judgment value, wherein the first decoding result judgment value is used to indicate whether there is an erroneous bit in the row codeword or the column codeword in the data read by the sub-decoding module; The early termination module is configured to count a third number, wherein the third number is the number of the first decoding result judgment values output by the sub-decoding module; The output shift module is used to store the decoding result codeword, receive the intermediate decoding result, and shift the intermediate decoding result to update the decoding result codeword; When the third number is equal to the number of rows or columns of the product code, the early termination module is used to output a stop signal to the sub-decoding module, and the output shift module outputs the decoding result codeword; When the channel information of the target bit of the product code is less than a preset reliability threshold, the preset soft information corresponding to the target bit is set to 0; When the channel information of the target bit of the product code is greater than or equal to the preset reliability threshold, the preset soft information corresponding to the target bit is set to 1; wherein the target bit is any bit in the product code; The early termination module includes a second counter and an AND gate circuit connected to the second counter; The second counter is configured to obtain the third number according to the number of the first decoding result judgment values output by the sub-decoding module; The initial values of the first enable signal and the second enable signal of the AND gate circuit are both 1, and when the third number is equal to the number of rows or columns of the product code, the second enable signal is set to 0; the output end of the AND gate circuit is connected to the input end of the sub-decoding module; The decoding device further includes a first intermediate shift module and a second intermediate shift module; The input end of the first intermediate shift module is connected to the output end of the storage module, and the output end of the first intermediate shift module is connected to the input end of the sub-decoding module; An input end of the second intermediate shift module is connected to an output end of the soft information comparison module, and an output end of the second intermediate shift module is connected to an input end of the address allocation module.

2. The product code decoding device according to claim 1, wherein The address allocation module includes a multiplexer.

3. The product code decoding device according to claim 1, wherein The input shift module and the output shift module are both barrel shift registers.

4. The product code decoding device according to claim 1, wherein The first intermediate shift module and the second intermediate shift module are both barrel shift registers.

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