Semiconductor integrated circuit device

Abstract

The present disclosure provides a layout structure of a capacitor unit using a fork sheet FET. The pad pairs (22c, 22d) of the transistors (P3, N3) and the gate wiring (36c) are supplied with VDD, and the pad pairs (27c, 27d) and the gate wiring (31c) are supplied with VSS. Capacitance is generated between the nanosheet (21c) and the gate wiring (31c), and between the nanosheet (26c) and the gate wiring (36c). The surface of the nanosheet (21c) on the side of the nanosheet (26c) is exposed from the gate wiring (31c), and the surface of the nanosheet (26c) on the side of the nanosheet (21c) is exposed from the gate wiring (36c).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit device including a nanosheet (nanowire) FET (Field Effect Transistor). Background Art

[0002] As a method for forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method means that: by preparing basic cells (such as inverters, latches, flip - flops, full - adders, etc.) having specific logic functions in advance as standard cells, arranging a plurality of standard cells on a semiconductor substrate, and connecting these standard cells with wirings, an LSI (Large - Scale Integration) chip is designed thereby.

[0003] The basic component of an LSI, namely a transistor, has achieved an increase in integration density, a reduction in operating voltage, and an increase in operating speed by reducing the gate length (scaling). However, in recent years, the problem has arisen that excessive scaling causes a cut - off current, and the cut - off current in turn causes a significant increase in power consumption. To solve this problem, active research has been started on three - dimensional structure transistors, that is, changing the transistor structure from the existing planar type to a three - dimensional type. The nanosheet (nanowire) FET has attracted much attention as one of them.

[0004] In Non - Patent Documents 1 and 2, the layouts of SRAM memory cells and standard cells using nanosheet FETs with fork - shaped gate electrodes are disclosed.

[0005] Non - Patent Document 1: P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co - optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17 - 505~508

[0006] Non - Patent Document 2: P. Weckx et a1., ″Novel forksheet device architecture as ultimate logic scaling device towards 2nm″, 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, IEDM19 - 871~874 Summary of the Invention

[0007] -Technical Problem to be Solved by the Invention-

[0008] In this specification, the nanosheet FET with a fork-shaped gate electrode is referred to as a fork sheet FET according to the description in Non-Patent Document 1.

[0009] In recent years, the miniaturization and high integration of semiconductor integrated circuits have developed significantly. Along with this, the reduction of the operating voltage and the increase of the operating frequency are accelerating. However, with the increase of the operating frequency, noise increases, and with the reduction of the operating voltage, the noise immunity decreases. Therefore, in recent semiconductor integrated circuits, there is a problem that circuit malfunction is likely to occur due to noise. As a method for preventing circuit malfunction caused by noise, there is a method of providing a decoupling capacitor between the power supplies of the circuit. The unit formed with such a decoupling capacitor is called a capacitor unit.

[0010] However, so far, no research has been conducted on a capacitor unit using a fork sheet FET.

[0011] An object of the present disclosure is to provide a layout structure of a capacitor unit that uses a fork sheet FET.

[0012] -Technical Solution for Solving the Technical Problem-

[0013] In a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a standard cell as a capacitor unit. In the semiconductor integrated circuit device, in the standard cell, a P-type region in which a P-type transistor is formed and an N-type region in which an N-type transistor is formed are formed adjacent to each other in a first direction. The standard cell includes: a first nanosheet portion, a second nanosheet portion, a first gate wiring, a first pad pair, a second gate wiring, and a second pad pair. In the P-type region, the first nanosheet portion is composed of one nanosheet extending in a second direction perpendicular to the first direction or two or more nanosheets arranged in the first direction. In the N-type region, the second nanosheet portion is composed of one nanosheet extending in the second direction or two or more nanosheets arranged in the first direction. The first gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the first nanosheet portion in the first direction and a third direction perpendicular to the first direction and the second direction. The first pad pair is respectively connected to two end portions of the nanosheets included in the first nanosheet portion in the second direction. The second gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the second nanosheet portion in the first direction and the third direction. The second pad pair is respectively connected to two end portions of the nanosheets included in the second nanosheet portion in the second direction. The first pad pair and the second gate wiring are supplied with a first power supply voltage, and the second pad pair and the first gate wiring are supplied with a second power supply voltage lower than the first power supply voltage. The first nanosheet portion and the second nanosheet portion face each other in the first direction, and a surface of the nanosheet closest to the second nanosheet portion among the nanosheets included in the first nanosheet portion on the side closer to the second nanosheet portion in the first direction is exposed from the first gate wiring. A surface of the nanosheet closest to the first nanosheet portion among the nanosheets included in the second nanosheet portion on the side closer to the first nanosheet portion in the first direction is exposed from the second gate wiring.

[0014] According to this aspect, since the first pad pair and the second gate wiring are supplied with the first power supply voltage, and the second pad pair and the first gate wiring are supplied with the second power supply voltage, capacitances are generated between the first nanosheet portion and the first gate wiring, and between the second nanosheet portion and the second gate wiring. In addition, capacitances are also generated between the first gate wiring and the second gate wiring, and between the first pad pair and the second pad pair. Moreover, the surface of the nanosheet in the first nanosheet portion that is closest to the second nanosheet portion and is on the side of the second nanosheet portion is exposed from the first gate wiring, and the surface of the nanosheet in the second nanosheet portion that is closest to the first nanosheet portion and is on the side of the first nanosheet is exposed from the second gate wiring. Thereby, the interval between the first nanosheet portion and the second nanosheet portion can be reduced, and thus the area of the capacitance unit can be further decreased. A larger capacitance can be achieved between the first gate wiring and the second gate wiring, and between the first pad pair and the second pad pair.

[0015] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a standard cell as a capacitor unit. In the semiconductor integrated circuit device, in the standard cell, a first region where a first-conductivity-type transistor is formed and a second region where a second-conductivity-type transistor is formed are formed adjacent to each other in a first direction. The standard cell includes: a first nanosheet portion, a second nanosheet portion, a first gate wiring, a first pad pair, a second gate wiring, and a second pad pair. In the first region, the first nanosheet portion is composed of one nanosheet extending in a second direction perpendicular to the first direction or two or more nanosheets arranged in the first direction. In the second region, the second nanosheet portion is composed of one nanosheet extending in the second direction or two or more nanosheets arranged in the first direction. The first gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the first nanosheet portion in the first direction and a third direction perpendicular to the first direction and the second direction. The first pad pair is respectively connected to two end portions of the nanosheets included in the first nanosheet portion in the second direction. The second gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the second nanosheet portion in the first direction and the third direction. The second pad pair is respectively connected to two end portions of the nanosheets included in the second nanosheet portion in the second direction. The first gate wiring and the second gate wiring are supplied with a first power supply voltage, and the first pad pair and the second pad pair are supplied with a second power supply voltage different from the first power supply voltage. The first nanosheet portion and the second nanosheet portion face each other in the first direction, and a surface of the nanosheet closest to the second nanosheet portion among the nanosheets included in the first nanosheet portion on the side closer to the second nanosheet portion in the first direction is exposed from the first gate wiring. A surface of the nanosheet closest to the first nanosheet portion among the nanosheets included in the second nanosheet portion on the side closer to the first nanosheet portion in the first direction is exposed from the second gate wiring.

[0016] According to this aspect, since the first gate wiring and the second gate wiring are supplied with the first power supply voltage and the first pad pair and the second pad pair are supplied with the second power supply voltage, a capacitance is generated between the first nanosheet portion and the first gate wiring or between the second nanosheet portion and the second gate wiring. Also, a surface of the nanosheet closest to the second nanosheet portion among the nanosheets included in the first nanosheet portion on the side closer to the second nanosheet portion in the first direction is exposed from the first gate wiring, and a surface of the nanosheet closest to the first nanosheet portion among the nanosheets included in the second nanosheet portion on the side closer to the first nanosheet portion in the first direction is exposed from the second gate wiring. Thus, the interval between the first nanosheet portion and the second nanosheet portion can be reduced, and therefore the area of the capacitor unit can be further decreased.

[0017] - Effects of the Invention -

[0018] According to the present disclosure, a layout structure of a large-capacitance capacitor unit using a fork-shaped FET can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a top view showing an example of the layout structure of the capacitor unit according to the first embodiment;

[0020] Figure 2 (a) and (b) of Figure 1 are cross-sectional views taken along the horizontal direction when looking down at the layout structure of

[0021] Figure 3 (a) to (c) of Figure 1 are cross-sectional views taken along the vertical direction when looking down at the layout structure of

[0022] Figure 4 is Figures 1 to 3 the circuit diagram of the capacitor unit shown in

[0023] Figure 5 (a) and (b) of

[0024] Figure 6 are cross-sectional views showing the layout structure of the capacitor unit according to a modification of the first embodiment;

[0025] Figure 7 (a) and (b) of Figure 6 are cross-sectional views taken along the vertical direction when looking down at the layout structure of

[0026] Figure 8 is Figure 6 and Figure 7 the circuit diagram of the capacitor unit shown in

[0027] Figure 9 is a top view showing the layout structure of the capacitor unit according to Modification 1 of the second embodiment;

[0028] Figure 10 is Figure 9 the circuit diagram of the capacitor unit shown in

[0029] Figure 11 is a top view showing the layout structure of the capacitor unit according to Modification 2 of the second embodiment;

[0030] Figure 12 is Figure 11 the circuit diagram of the capacitor unit shown in

[0031] Figure 13 FIG. Figure 13 shows the basic structure of a fork-fin FET, where (a) is a top view and (b) is a cross-sectional view. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (which may be simply referred to as cells in this specification), and at least a part of the plurality of standard cells includes nanosheet FETs (Field Effect Transistors). A nanosheet FET is an FET formed using a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, a part of the nanosheet FETs are fork-fin FETs in which the gate electrodes are in a fork shape.

[0033] In the present disclosure, a semiconductor layer portion that is formed at both ends of a nanosheet and constitutes a terminal serving as a source or a drain of a nanosheet FET is referred to as a "pad".

[0034] First, the basic structure of the fork-fin FET will be described.

[0035] Figure 13 FIG. Figure 13 shows the basic structure of a fork-fin FET, where (a) is a top view and (b) is a cross-sectional view taken along line Y-Y' in (a). In Figure 13 the basic structure, two transistors TR1 and TR2 are arranged at intervals of S in the Y direction. The gate wiring 531 that serves as the gate of transistor TR1 and the gate wiring 532 that serves as the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0036] The channel portions 521 that serve as the channel regions of transistor TR1 and the channel portions 526 that serve as the channel regions of transistor TR2 are formed of nanosheets. In Figure 13 this, the channel portions 521 and 526 are each formed of a nanosheet formed by a three-sheet structure that overlaps in a top view. On both sides in the X direction of the channel portion 521, pads 522a and 522b that serve as the source region or the drain region of transistor TR1 are formed. On both sides in the X direction of the channel portion 526, pads 527a and 527b that serve as the source region or the drain region of transistor TR2 are formed. The pads 522a and 522b are formed by epitaxial growth of the nanosheets constituting the channel portion 521. The pads 527a and 527b are formed by epitaxial growth of the nanosheets constituting the channel portion 526.

[0037] The gate wiring 531 surrounds the outer periphery of the channel portion 521 formed of nanosheets in the Y direction and the Z direction with a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel portion 521 on the side of the transistor TR2 in the Y direction is not covered by the gate wiring 531 but is exposed from the gate wiring 531. That is to say, in Figure 13 in the cross-sectional view of (b), the gate wiring 531 does not cover the right side in the drawing of the nanosheet constituting the channel portion 521, but covers the upper side, the left side, and the lower side in the drawing. The gate wiring 531 extends toward the side opposite to the transistor TR2 in the Y direction with respect to the nanosheet constituting the channel portion 521, and the amount of extension is the length OL.

[0038] The gate wiring 532 surrounds the outer periphery of the channel portion 526 formed of nanosheets in the Y direction and the Z direction with a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel portion 526 on the side of the transistor TR1 in the Y direction is not covered by the gate wiring 532 but is exposed from the gate wiring 532. That is to say, in Figure 13 in the cross-sectional view of (b), the gate wiring 532 does not cover the left side in the drawing of the nanosheet constituting the channel portion 526, but covers the upper side, the right side, and the lower side in the drawing. The gate wiring 532 extends toward the side opposite to the transistor TR1 in the Y direction with respect to the nanosheet constituting the channel portion 526, and the amount of extension is the length OL.

[0039] If the width (dimension in the Y direction) of each nanosheet is set to W and the height (dimension in the Z direction) is set to H, the effective gate width Weff is: Weff = 2×W + H.

[0040] Since the channel portions 521 of the transistor TR1 and the channel portions 526 of the transistor TR2 are both composed of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are: 3×(2×W + H).

[0041] According to Figure 13 the structure of, the gate wiring 531 does not extend toward the transistor TR2 side in the Y direction with respect to the nanosheet constituting the channel portion 521. The gate wiring 532 does not extend toward the transistor TR1 side in the Y direction with respect to the nanosheet constituting the channel portion 526. In this way, the transistors TR1 and TR2 can be made closer to each other, and thus miniaturization can be achieved.

[0042] It should be noted that the number of nanosheets constituting the channel portion of the transistor is not limited to three. That is to say, the nanosheet can be formed of a single sheet-like structure, or can be formed of multiple sheet-like structures overlapping in a top view. In Figure 13In (b) of [], the cross-sectional shape of the nanosheet is shown as a rectangle, but it is not limited thereto. For example, the cross-sectional shape of the nanosheet may also be a square, a circle, an ellipse, etc.

[0043] The fork-sheet FET and the nanosheet FET may coexist in the semiconductor integrated circuit device, and the entire periphery of the nanosheet of the nanosheet FET is surrounded by the gate wiring.

[0044] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "the same wiring width" that mean equality of width, etc. include the deviation range in manufacturing.

[0045] (First Embodiment)

[0046] Figures 1 to 3 is a diagram showing an example of the layout structure of the capacitor unit according to the first embodiment. Figure 1 is a top view. Figure 2 (a) and (b) of [] are cross-sectional views taken along the horizontal direction in the top view. Figure 3 (a) to (c) of [] are cross-sectional views taken along the vertical direction in the top view. Figure 2 (a) of [] is a cross-section taken along line X1-X1'. Figure 2 (b) of [] is a cross-section taken along line X2-X2'. Figure 3 (a) of [] is a cross-section taken along line Y1-Y1'. Figure 3 (b) of [] is a cross-section taken along line Y2-Y2'. Figure 3 (c) of [] is a cross-section taken along line Y3-Y3'.

[0047] It should be noted that in the following description, in Figure 1 such top views, the horizontal direction in the drawing is set as the X direction (equivalent to the second direction), the vertical direction in the drawing is set as the Y direction (equivalent to the first direction), and the direction perpendicular to the substrate surface is set as the Z direction (equivalent to the third direction).

[0048] Figure 4 is Figures 1 to 3 the circuit diagram of the capacitor unit shown in. As Figure 4 shown, Figures 1 to 3The capacitor unit shown has P-type transistors P1, P2, P3, P4, P5 and N-type transistors N1, N2, N3, N4, N5. Transistors P2 to P4 and transistors N2 to N4 function as capacitor elements. Transistors P1 and N5 constitute a fixed-value output section 5. The fixed-value output section 5 outputs a low fixed value (VSS) to node X1 and a high fixed value (VDD) to node X2. The source of transistor P1 is connected to VDD, the drain is connected to the gate of transistor N5, and the gate is connected to the drain of transistor N5. The source of transistor N5 is connected to VSS, and the drain is connected to the gate of transistor P1. The gate of transistor P1 corresponds to node X1, and the gate of transistor N5 corresponds to node X2.

[0049] It should be noted that transistors P5 and N1 are transistors in a cut-off state. As the circuit structure of the capacitor unit, transistors P5 and N1 may not be present, but if transistors P5 and N1 are present, the regularity of the layout of the capacitor unit is improved, so the manufacturing ease of the device is improved, the yield is improved, and manufacturing deviations are suppressed.

[0050] The sources and drains of transistors P2 to P4 are connected to VDD, and the gates are connected to node X1. Since VSS is output from the fixed-value output section 5 to node X1, transistors P2 to P4 function as capacitor elements. The sources and drains of transistors N2 to N4 are connected to VSS, and the gates are connected to node X2. Since VDD is output from the fixed-value output section 5 to node X2, transistors N2 to N4 function as capacitor elements.

[0051] Figures 1 to 3 The capacitor units are arranged in a row along the X direction in such a way that they are adjacent to other standard units with a unit frame CL, thereby forming a unit row. Multiple unit rows are arranged in a row along the Y direction in such a way that they are adjacent to each other with a unit frame CL. Each column in the multiple unit rows is inverted up and down compared to the previous column.

[0052] As Figure 1 shown, at both ends in the Y direction of the capacitor unit, power supply wirings 11 and 12 extending in the X direction are respectively provided. Power supply wirings 11 and 12 are both buried power supply wirings (BPR: Buried Power Rail) formed in a buried wiring layer. Power supply wiring 11 supplies the power supply voltage VDD, and power supply wiring 12 supplies the power supply voltage VSS. Power supply wirings 11 and 12 are shared with other units in the unit row including the capacitor unit and become power supply wirings extending in the X direction. Power supply wirings 11 and 12 constitute power supply wirings arranged between unit rows adjacent to each other in the Y direction.

[0053] P-type transistors P1, P2, P3, P4, and P5 are formed in the P-type regions on the N-well. N-type transistors N1, N2, N3, N4, and N5 are formed in the N-type regions on the P-type substrate. The P-type regions and the N-type regions are formed adjacent to each other in the Y direction. In the X direction, the arrangement positions of transistors P1, P2, P3, P4, and P5 are the same as those of transistors N1, N2, N3, N4, and N5 respectively. That is, transistors P1 and N1 are arranged in a column in the Y direction. Transistors P2 and N2 are arranged in a column in the Y direction. Transistors P3 and N3 are arranged in a column in the Y direction. Transistors P4 and N4 are arranged in a column in the Y direction. Transistors P5 and N5 are arranged in a column in the Y direction.

[0054] Transistors P1, P2, P3, P4, and P5 each have nanosheets 21a, 21b, 21c, 21d, and 21e formed by three sheet-like structures overlapping when viewed from above as channel portions. That is, transistors P1, P2, P3, P4, and P5 are nanosheet FETs.

[0055] As Figure 1 shown, pads 22a are formed on the left side in the drawing of nanosheet 21a, pads 22b are formed between nanosheet 21a and nanosheet 21b, pads 22c are formed between nanosheet 21b and nanosheet 21c, pads 22d are formed between nanosheet 21c and nanosheet 21d, pads 22e are formed between nanosheet 21d and nanosheet 21e, and pads 22f are formed on the right side in the drawing of nanosheet 21e. The pads 22a, 22b, 22c, 22d, 22e, and 22f are formed of a semiconductor layer with an integrated structure connected to the three sheet-like structures. Pads 22a and 22b serve as the source region and drain region of transistor P1. Pads 22b and 22c serve as the source region and drain region of transistor P2. Pads 22c and 22d serve as the source region and drain region of transistor P3. Pads 22d and 22e serve as the source region and drain region of transistor P4. Pads 22e and 22f serve as the source region and drain region of transistor P5.

[0056] Transistors N1, N2, N3, N4, and N5 each have nanosheets 26a, 26b, 26c, 26d, and 26e formed by three sheet-like structures overlapping when viewed from above as channel portions. That is, transistors N1, N2, N3, N4, and N5 are nanosheet FETs.

[0057] As Figure 1As shown, pads 27a are formed on the left side in the drawing of nanosheet 26a, pads 27b are formed between nanosheet 26a and nanosheet 26b, pads 27c are formed between nanosheet 26b and nanosheet 26c, pads 27d are formed between nanosheet 26c and nanosheet 26d, pads 27e are formed between nanosheet 26d and nanosheet 26e, and pads 27f are formed on the right side in the drawing of nanosheet 26e. The pads 27a, 27b, 27c, 27d, 27e, 27f are formed of a semiconductor layer having an integral structure connected to three sheet-like structures. Pads 27a and 27b serve as the source region and drain region of transistor N1. Pads 27b and 27c serve as the source region and drain region of transistor N2. Pads 27c and 27d serve as the source region and drain region of transistor N3. Pads 27d and 27e serve as the source region and drain region of transistor N4. Pads 27e and 27f serve as the source region and drain region of transistor N5.

[0058] In the P-type region, gate wirings 31a, 31b, 31c, 31d, 31e extending in parallel in the Y direction are formed. The gate wirings 31a, 31b, 31c, 31d, 31e are formed with equal widths and arranged at equal intervals. In the N-type region, gate wirings 36a, 36b, 36c, 36d, 36e extending in parallel in the Y direction are formed. The gate wirings 36a, 36b, 36c, 36d, 36e are formed with equal widths and arranged at equal intervals. In the X direction, the arrangement positions of the gate wirings 31a, 31b, 31c, 31d, 31e are the same as those of the gate wirings 36a, 36b, 36c, 36d, 36e respectively. That is, the gate wirings 31a and 36a are aligned in the Y direction. The gate wirings 31b and 36b are aligned in the Y direction. The gate wirings 31c and 36c are aligned in the Y direction. The gate wirings 31d and 36d are aligned in the Y direction. The gate wirings 31e and 36e are aligned in the Y direction. dummy gate wirings 38a, 38b are formed on the unit frames CL on both sides in the X direction.

[0059] The gate wiring 31a surrounds the outer peripheries of the nanosheet 21a of the transistor P1 in the Y direction and Z direction with a gate insulating film (not shown). The gate wiring 31a serves as the gate of the transistor P1. Similarly, the gate wirings 31b, 31c, 31d, 31e respectively surround the outer peripheries of the nanosheets 21b, 21c, 21d, 21e of the transistors P2, P3, P4, P5 in the Y direction and Z direction with a gate insulating film (not shown). The gate wirings 31b, 31c, 31d, 31e respectively serve as the gates of the transistors P2, P3, P4, P5.

[0060] The gate wiring 36a surrounds the outer peripheries of the nanosheets 26a of the transistor N1 in the Y direction and the Z direction with a gate insulating film (not shown). The gate wiring 36a serves as the gate of the transistor N1. Similarly, the gate wirings 36b, 36c, 36d, and 36e respectively surround the outer peripheries of the nanosheets 26b, 26c, 26d, and 26e of the transistors N2, N3, N4, and N5 in the Y direction and the Z direction with a gate insulating film (not shown). The gate wirings 36b, 36c, 36d, and 36e respectively serve as the gates of the transistors N2, N3, N4, and N5.

[0061] The gate wiring 31a and the gate wiring 36a arranged in the Y direction are connected via a bridge portion 33a formed between the gate wiring 31a and the gate wiring 36a. The gate wiring 31e and the gate wiring 36e arranged in the Y direction are connected via a bridge portion 33b formed between the gate wiring 31e and the gate wiring 36e.

[0062] In the local wiring layer, local wirings 41, 42, 43a, 43b, 43c, 43d, 44a, 44b, 44c, and 44d extending in the Y direction are formed. The local wiring 41 is connected to the pads 22a and 27a. The local wiring 42 is connected to the pads 22f and 27f. The local wirings 43a, 43b, 43c, and 43d are respectively connected to the pads 22b, 22c, 22d, and 22e, and are connected to the power supply wiring 11 via vias. The local wirings 44a, 44b, 44c, and 44d are respectively connected to the pads 27b, 27c, 27d, and 27e, and are connected to the power supply wiring 12 via vias.

[0063] In the M1 wiring layer, metal wirings 51, 52, 53, and 54 extending in the X direction are formed. The metal wiring 52 and the metal wiring 54 correspond to the node X1 of the circuit, and the metal wirings 51 and 53 correspond to the node X2 of the circuit. The metal wiring 51 is connected to the gate wiring 31c via a via and is connected to the local wiring 41 via a via. The metal wiring 52 is connected to the gate wirings 31a, 31b, 31c, and 31d via vias and is connected to the local wiring 42 via a via. The metal wiring 53 is connected to the gate wirings 36b, 36c, 36d, and 36e via vias and is connected to the local wiring 41 via a via. The metal wiring 54 is connected to the gate wiring 36a, and the metal wiring 54 is connected to the local wiring 42 via a via. The metal wirings 51, 52, 53, and 54 form an inter-wiring capacitance.

[0064] Here, the nanosheets 21a and 26a are opposed to each other in the Y direction. The surface of the nanosheet 21a on the side of the nanosheet 26a in the Y direction is not covered by the gate wiring 31a but is exposed from the gate wiring 31a. The surface of the nanosheet 26a on the side of the nanosheet 21a in the Y direction is not covered by the gate wiring 36a but is exposed from the gate wiring 36a.

[0065] Similarly, the nanosheets 21b and 26b are opposed to each other in the Y direction, the nanosheets 21c and 26c are opposed to each other in the Y direction, the nanosheets 21d and 26d are opposed to each other in the Y direction, and the nanosheets 21e and 26e are opposed to each other in the Y direction. The surfaces of the nanosheets 21b, 21c, 21d, and 21e on the sides of the nanosheets 26b, 26c, 26d, and 26e in the Y direction are not covered by the gate wirings 31b, 31c, 31d, and 31e but are exposed from the gate wirings 31b, 31c, 31d, and 31e. The surfaces of the nanosheets 26b, 26c, 26d, and 26e on the sides of the nanosheets 21b, 21c, 21d, and 21e in the Y direction are not covered by the gate wirings 36b, 36c, 36d, and 36e but are exposed from the gate wirings 36b, 36c, 36d, and 36e.

[0066] Here, attention is paid to the transistor P3 that functions as a capacitor element. In the transistor P3, VSS is supplied from the node X1 to the gate wiring 31c that becomes the gate, and VDD is supplied to the pads 22c and 22d that become the source / drain via the local wirings 43b and 43c. Therefore, a capacitance is generated across the gate oxide film of the transistor P3. In addition, capacitances are also generated at the following locations.

[0067] 1) Between the pads 22c and 22d and the gate wiring 31c (see Figure 2 (a) of

[0068] 2) Between the local wirings 43b and 43c and the gate wiring 31c (see Figure 2 (a) of

[0069] 3) Between the gate wiring 31c and the gate wiring 36c of the transistor N3 (see Figure 3 (a) of

[0070] 4) Between the pads 22c and 22d and the pads 27c and 27d of the transistor N3 (see Figure 3 (b) of

[0071] 5) Between the local wirings 43b and 43c and the gate wiring 44b and 44 (see Figure 3 (b) of

[0072] Moreover, in the present embodiment, the surface of the nanosheet 21c of the transistor P3 on the side of the nanosheet 26c of the transistor N3 is not covered by the gate wiring 31c, and the surface of the nanosheet 26c of the transistor N3 on the side of the nanosheet 21c of the transistor P3 is not covered by the gate wiring 36c. Thus, the distance between the transistor P3 and the transistor N3 is shortened. Therefore, the capacitances in the above 3) and 4) become larger.

[0073] As described above, according to the present embodiment, for the transistors P2, P3, and P4, capacitances are generated between the nanosheets 21b, 21c, and 21d and the gate wirings 31b, 31c, and 31d. For the transistors N2, N3, and N4, capacitances are generated between the nanosheets 26b, 26c, and 26d and the gate wirings 36b, 36c, and 36d. Also, the surfaces of the nanosheets 21b, 21c, and 21d on the side of the nanosheets 26b, 26c, and 26d are exposed from the gate wirings 31b, 31c, and 31d, and the surfaces of the nanosheets 26b, 26c, and 26d on the side of the nanosheets 21b, 21c, and 21d are exposed from the gate wirings 36b, 36c, and 36d. Thus, the interval between the nanosheets 21b, 21c, and 21d and the nanosheets 26b, 26c, and 26d can be narrowed, and therefore the area of the capacitor unit can be further reduced. In addition, for example, in the transistors P3 and N3, larger capacitances can also be achieved between the gate wiring 31c and the gate wiring 36c, and between the pad pairs 22c, 22d and the pad pairs 27c, 27d.

[0074] It should be noted that in the above embodiment, the fixed value output unit may be omitted. In this case, for example, the capacitor unit may be configured to directly supply VSS to the gates of the transistors P2, P3, and P4 and directly supply VDD to the gates of the transistors N2, N3, and N4.

[0075] In the above embodiment, three P-type transistors and three N-type transistors are respectively provided as the transistors constituting the capacitor, but the number of the transistors constituting the capacitor is not limited thereto.

[0076] (Modified Example)

[0077] In the above-described embodiments, in each transistor, one nanosheet is arranged in the Y direction, but two or more nanosheets may be arranged in the Y direction. In this case, as long as the opposing nanosheets are exposed from the gate wiring at the boundary between the P-type region and the N-type region. That is, when the nanosheets of the P-type transistor are regarded as the first nanosheet portion and the nanosheets of the N-type transistor are regarded as the second nanosheet portion, the surface on the side closer to the second nanosheet portion in the Y direction of the nanosheet closest to the second nanosheet portion among the nanosheets of the first nanosheet portion is exposed from the gate wiring, and the surface on the side closer to the first nanosheet portion in the Y direction of the nanosheet closest to the first nanosheet portion among the nanosheets of the second nanosheet portion is exposed from the gate wiring. Thus, the same functions and effects as those of the above-described embodiments can be obtained.

[0078] Figure 5 (a) and (b) of FIG. are cross-sectional views taken along the longitudinal direction when looking down, showing the structure of this modified example. In Figure 5 this structure, the transistor P3 has two nanosheets 21c and 23c arranged along the Y direction, and the transistor N3 has two nanosheets 26c and 28c arranged along the Y direction. Bond pads 24d, 22d, 27d, and 29d are formed on one side in the X direction of the nanosheets 21c, 23c, 26c, and 28c, respectively.

[0079] The surface on the side closer to the nanosheet 26a in the Y direction of the nanosheet 21c is not covered by the gate wiring 31c but is exposed from the gate wiring 31c. The surface on the side closer to the nanosheet 21c in the Y direction of the nanosheet 26a is not covered by the gate wiring 36c but is exposed from the gate wiring 36c.

[0080] That is, when the nanosheets 21c and 23c are regarded as the first nanosheet portion 24 and the nanosheets 26c and 28c are regarded as the second nanosheet portion 25, the surface on the side closer to the second nanosheet portion 25 in the Y direction of the nanosheet 21c, which is the nanosheet closest to the second nanosheet portion 25 among the nanosheets of the first nanosheet portion 24, is exposed from the gate wiring 31c, and the surface on the side closer to the first nanosheet portion 24 in the Y direction of the nanosheet 26c, which is the nanosheet closest to the first nanosheet portion 24 among the nanosheets of the second nanosheet portion 25, is exposed from the gate wiring 36c.

[0081] (Second Embodiment)

[0082] Figure 6 and Figure 7 are diagrams showing an example of the layout structure of the capacitor unit according to the second embodiment. Figure 6 is a top view. Figure 7 is a cross-sectional view taken along the longitudinal direction when looking down. Figure 7 (a) of FIG. is a cross-section taken along the line Y4 - Y4'. Figure 7The cross-section shown in (b) is a cross-section taken along line Y5 - Y5'. It should be noted that Figure 6 and Figure 7 The layout structures shown are similar to the layout structure shown in Figures 1 to 3 For example, the power supply wiring, and the arrangement of the nanosheets and pads of the transistors are the same. In the following description, the description of the same components as those in the first embodiment may sometimes be omitted.

[0083] Figure 8 is Figure 6 and Figure 7 The circuit diagram of the capacitor unit shown. As shown in Figure 8 shown, Figure 6 and Figure 7 The unit shown has P-type transistors P1, P2, P3, P4, P5 and N-type transistors N1, N2, N3, N4, N5. Transistors N2 to N4 function as capacitor elements. Transistors P5 and transistor N1 constitute a fixed-value output section 5. The fixed-value output section 5 outputs a high fixed value (VDD) to node X1 and a low fixed value (VSS) to node X2. The source of transistor P5 is connected to VDD, the drain is connected to the gate of transistor N1, and the gate is connected to the drain of transistor N1. The source of transistor N1 is connected to VSS, and the drain is connected to the gate of transistor P5. The gate of transistor N1 corresponds to node X1, and the gate of transistor P5 corresponds to node X2.

[0084] It should be noted that transistors P1 to P4 and transistor N5 are transistors in the cut-off state. As the circuit structure of the capacitor unit, transistors P1 to P4 and transistor N5 may not be present, but if transistors P1 to P4 and transistor N5 are present, the regularity of the layout of the capacitor unit is improved, so the ease of manufacturing the device is improved, the yield is improved, and manufacturing deviations are suppressed.

[0085] The sources and drains of transistors N2 to N4 are connected to VSS, and the gates are connected to node X1. Since VDD is output from the fixed-value output section 5 to node X1, transistors N2 to N4 function as capacitor elements.

[0086] As shown in Figure 6 and Figure 7As shown, gate wirings 131a, 131b, 131c, 131d, and 131e are formed in the P-type region and extend in parallel along the Y direction. The gate wirings 131a, 131b, 131c, 131d, and 131e are formed with equal widths and arranged at equal intervals. Gate wirings 136a, 136b, 136c, 136d, and 136e are formed in the N-type region and extend in parallel along the Y direction. The gate wirings 136a, 136b, 136c, 136d, and 136e are formed with equal widths and arranged at equal intervals. In the X direction, the arrangement positions of the gate wirings 131a, 131b, 131c, 131d, and 131e are respectively the same as the arrangement positions of the gate wirings 136a, 136b, 136c, 136d, and 136e. That is, the gate wirings 131a and 136a are arranged in a row in the Y direction. The gate wirings 131b and 136b are arranged in a row in the Y direction. The gate wirings 131c and 136c are arranged in a row in the Y direction. The gate wirings 131d and 136d are arranged in a row in the Y direction. The gate wirings 131e and 136e are arranged in a row in the Y direction.

[0087] The gate wiring 131a surrounds the outer periphery of the nanosheet 21a of the transistor P1 in the Y direction and the Z direction via a gate insulating film (not shown). The gate wiring 131a becomes the gate of the transistor P1. Similarly, the gate wirings 131b, 131c, 131d, and 131e surround the outer periphery of the nanosheets 21b, 21c, 21d, and 21e of the transistors P2, P3, P4, and P5 in the Y direction and the Z direction via a gate insulating film (not shown). The gate wirings 131b, 131c, 131d, and 131e become the gates of the transistors P2, P3, P4, and P5, respectively.

[0088] The gate wiring 136a surrounds the outer periphery of the nanosheet 26a of the transistor N1 in the Y direction and the Z direction via a gate insulating film (not shown). The gate wiring 136a becomes the gate of the transistor N1. Similarly, the gate wirings 136b, 136c, 136d, and 136e surround the outer periphery of the nanosheets 26b, 26c, 26d, and 26e of the transistors N2, N3, N4, and N5 in the Y direction and the Z direction, respectively, via a gate insulating film (not shown). The gate wirings 136b, 136c, 136d, and 136e become the gates of the transistors N2, N3, N4, and N5, respectively.

[0089] The gate wirings 131a and 136a arranged in the Y direction are connected via a bridge portion 133a formed between the gate wiring 131a and the gate wiring 136a. The gate wirings 131b and 136b arranged in the Y direction are connected via a bridge portion 133b formed between the gate wiring 131b and the gate wiring 136b. The gate wirings 131c and 136c arranged in the Y direction are connected via a bridge portion 133c formed between the gate wiring 131c and the gate wiring 136c. The gate wirings 131d and 136d arranged in the Y direction are connected via a bridge portion 133d formed between the gate wiring 131d and the gate wiring 136d. The gate wirings 131e and 136e arranged in the Y direction are connected via a bridge portion 133e formed between the gate wiring 131e and the gate wiring 136e.

[0090] Local wirings 141, 142, 143, 144, 145, 146, 147, 148 extending in the Y direction are formed in the local wiring layer. The local wiring 141 is connected to the pads 22a and 27a. The local wiring 142 is connected to the pads 22b and 27b, and the local wiring 142 is connected to the power supply wiring 12 via a via hole. The local wiring 143 is connected to the pads 22c and 27c, and the local wiring 143 is connected to the power supply wiring 12 via a via hole. The local wiring 144 is connected to the pads 22d and 27d, and the local wiring 144 is connected to the power supply wiring 12 via a via hole. The local wiring 145 is connected to the pad 22e. The local wiring 146 is connected to the pad 22f, and the local wiring 146 is connected to the power supply wiring 11 via a via hole. The local wiring 147 is connected to the pad 27e, and the local wiring 147 is connected to the power supply wiring 12. The local wiring 148 is connected to the pad 27f.

[0091] In the M1 wiring layer, metal wirings 151, 152, 153, 154 extending in the X direction are formed. The metal wirings 152 and 154 correspond to the node X1 of the circuit, and the metal wirings 151 and 153 correspond to the node X2 of the circuit. The metal wiring 151 is connected to the gate wiring 131e via a via hole, and the metal wiring 151 is connected to the local wiring 141 via a via hole. The metal wiring 152 is connected to the gate wirings 131a, 131b, 131c, 131d via a via hole, and the metal wiring 152 is connected to the local wiring 145 via a via hole. The metal wiring 153 is connected to the gate wiring 136e via a via hole, and the metal wiring 153 is connected to the local wiring 141 via a via hole. The metal wiring 154 is connected to the gate wirings 136a, 136b, 136c, 136d via a via hole, and the metal wiring 154 is connected to the local wiring 148 via a via hole.

[0092] Here, similar to the first embodiment, the nanosheet 21a and the nanosheet 26a face each other in the Y direction. The surface of the nanosheet 21a on the side of the nanosheet 26a in the Y direction is not covered by the gate wiring 131a, but is exposed from the gate wiring 131a. The surface of the nanosheet 26a on the side of the nanosheet 21a in the Y direction is not covered by the gate wiring 136a, but is exposed from the gate wiring 136a.

[0093] Similarly, the nanosheet 21b and the nanosheet 26b face each other in the Y direction. The nanosheet 21c and the nanosheet 26c face each other in the Y direction. The nanosheet 21d and the nanosheet 26d face each other in the Y direction. The nanosheet 21e and the nanosheet 26e face each other in the Y direction. The surfaces of the nanosheets 21b, 21c, 21d, and 21e on the sides of the nanosheets 26b, 26c, 26d, and 26e in the Y direction are not covered by the gate wirings 131b, 131c, 131d, and 131e, but are exposed from the gate wirings 131b, 131c, 131d, and 131e. The surfaces of the nanosheets 26b, 26c, 26d, and 26e on the sides of the nanosheets 21b, 21c, 21d, and 21e in the Y direction are not covered by the gate wirings 136b, 136c, 136d, and 136e, but are exposed from the gate wirings 136b, 136c, 136d, and 136e.

[0094] From the P-type region to the N-type region, a gate wiring supplied with VDD and a local wiring supplied with VSS are formed, and a capacitor is formed between the gate wiring and the local wiring. For example, if we focus on the transistors P3 and N3, the gate wirings 131c and 136c are connected by a bridge portion 133c, and VDD is supplied to the gate wirings 131c and 136c via the metal wiring 152. VSS is supplied from the power supply wiring 12 to the local wirings 143 and 144. Therefore, a capacitor is formed between the gate wirings 131c and 136c, the bridge portion 133c, and the local wirings 143 and 144.

[0095] As described above, according to the present embodiment, for transistors N2, N3, and N4, a capacitance is generated between the nanosheets 26b, 26c, and 26d and the gate wirings 136b, 136c, and 136d. Moreover, the surfaces of the nanosheets 21b, 21c, and 21d on the side of the nanosheets 26b, 26c, and 26d are exposed from the gate wirings 131b, 131c, and 131d, and the surfaces of the nanosheets 26b, 26c, and 26d on the side of the nanosheets 21b, 21c, and 21d are exposed from the gate wirings 136b, 136c, and 136d. Thus, the interval between the nanosheets 21b, 21c, and 21d and the nanosheets 26b, 26c, and 26d can be narrowed, and therefore the area of the capacitance unit can be further reduced. In addition, for example, in transistors P3 and N3, a large capacitance can be realized between the gate wiring 131c, the gate wiring 136c, the bridge portion 133c, and the local wirings 143 and 144.

[0096] It should be noted that in the above embodiment, the fixed-value output unit may be omitted. In this case, for example, the capacitance unit may be configured to directly supply VDD to the gates of transistors N2, N3, and N4.

[0097] In the above embodiment, three N-type transistors are provided as the transistors constituting the capacitance, but the number of transistors constituting the capacitance is not limited thereto.

[0098] Similar to the modification of the first embodiment, in each transistor, two or more nanosheets may be arranged in the Y direction.

[0099] (Modification 1)

[0100] The capacitance unit according to the above embodiment may be configured by replacing the conductivity type of the transistors.

[0101] Figure 9 It is a top view showing the layout structure of the capacitance unit according to Modification 1 of the second embodiment. Figure 9 The shown layout structure is equivalent to the layout structure in Figure 6 being turned upside down, interchanging P-type and N-type, and interchanging VDD and VSS. In the layout structure of Figure 9 , the arrangement manners of the power supply wiring, transistors, gate wirings, local wirings, and M1 wiring are the same as those in Figure 6 . However, the difference from the layout structure in Figure 6 lies in the connection relationships between the M1 wiring and the local wirings and the gate wirings, and the connection relationships between the local wirings and the power supply wiring.

[0102] Figure 10 It is Figure 9 the circuit diagram of the capacitance unit shown.Figure 10 The circuit in Figure 8 is equivalent to the circuit in

[0103] being flipped vertically, with the P-type and N-type interchanged, and VDD and VSS interchanged. Figure 10 As shown in Figure 9 the cell shown in

[0104] has P-type transistors P1, P2, P3, P4, P5 and N-type transistors N1, N2, N3, N4, N5. Transistors P2 to P4 function as capacitive elements. Transistors P1 and transistor N5 constitute a fixed-value output section 5. The fixed-value output section 5 outputs a low fixed value (VSS) to node X1 and a high fixed value (VDD) to node X2. The source of transistor P1 is connected to VDD, the drain is connected to the gate of transistor N5, and the gate is connected to the drain of transistor N5. The source of transistor N5 is connected to VSS, and the drain is connected to the gate of transistor P1. The gate of transistor P1 corresponds to node X1, and the gate of transistor N5 corresponds to node X2.

[0105] In Figure 9 the local wirings 142, 143, 144, 145 are connected to the power supply wiring 11 via vias. The local wiring 148 is connected to the power supply wiring 12 via a via. The metal wiring 151 is connected to the gate wirings 131a, 131b, 131c, 131d via vias and is also connected to the local wiring 146 via a via. The metal wiring 152 is connected to the gate wiring 131e via a via and is also connected to the local wiring 141 via a via. The metal wiring 153 is connected to the gate wirings 136a, 136b, 136c, 136d via vias and is also connected to the local wiring 147 via a via. The metal wiring 154 is connected to the gate wiring 136e via a via and is also connected to the local wiring 141 via a via.

[0106] In this modification example, the same operations and effects as those of the above-described embodiment can also be obtained.

[0107] (Modification Example 2)

[0108] Figure 11 is a top view showing the layout structure of the capacitive cell according to Modification Example 2 of the second embodiment. In Figure 11 the layout structure, the arrangement of the power supply wiring, transistors, and gate wirings is the same as that in Figure 6The layout structures are the same. However, there are some differences in the arrangement of the local wirings, and the connection relationships between the M1 wiring and the local wirings and the gate wiring, as well as the connection relationships between the local wirings and the power supply wiring, are different.

[0109] Figure 12 is Figure 11 the circuit diagram of the capacitor unit shown. Figure 12 The circuit of Figure 8 is equivalent to the circuit in which the sources and drains of the transistors P1 to P4 and N2 to N4 directly connected to VSS in the circuit of

[0110] are connected to node X2, and the fixed value output section 5 outputs a low fixed value (VSS) to this node X2. Figure 12 As shown Figure 11 The unit shown has P-type transistors P1, P2, P3, P4, P5 and N-type transistors N1, N2, N3, N4, N5. The transistors N2 to N4 function as capacitive elements. The transistor P5 and the transistor N1 constitute the fixed value output section 5. The fixed value output section 5 outputs a high fixed value (VDD) to node X1 and a low fixed value (VSS) to node X2. The source of the transistor P5 is connected to VDD, the drain is connected to the gate of the transistor N1, and the gate is connected to the drain of the transistor N1. The source of the transistor N1 is connected to VSS, and the drain is connected to the gate of the transistor P5. The gate of the transistor N1 corresponds to node X1, and the gate of the transistor P5 corresponds to node X2.

[0111] The sources and drains of the transistors N2 to N4 are connected to node X2, and the gates are connected to node X1. Since VDD is output from the fixed value output section 5 to node X1 and VSS is output from the fixed value output section 5 to node X2, the transistors N2 to N4 function as capacitive elements.

[0112] It should be noted that the transistors P1 to P4 and the transistor N5 are transistors in the cut-off state. As the circuit structure of the capacitor unit, the transistors P1 to P4 and the transistor N5 may not be present, but if the transistors P1 to P4 and the transistor N5 are present, the regularity of the layout of the capacitor unit is improved, so the manufacturing ease of the device is improved, the yield is improved, and the manufacturing deviation is suppressed.

[0113] Local wirings 241, 242, 243, 244, 245, 246, 247, 248 extending in the Y direction are formed in the local wiring layer. The local wiring 241 is connected to the pad 22a. The local wiring 242 is connected to the pad 27a, and the local wiring 242 is connected to the power supply wiring 12 via a via. The local wiring 243 is connected to the pads 22b, 27b. The local wiring 244 is connected to the pads 22c, 27c. The local wiring 245 is connected to the pads 22d, 27d. The local wiring 246 is connected to the pad 22e, and the local wiring 246 is connected to the power supply wiring 11 via a via. The local wiring 247 is connected to the pad 27e. The local wiring 248 is connected to the pads 22f, 27f.

[0114] In the M1 wiring layer, metal wirings 251, 252, 253, 254 extending in the X direction are formed. The metal wirings 252 and 254 correspond to the node X1 of the circuit, and the metal wirings 251 and 253 correspond to the node X2 of the circuit. The metal wiring 251 is connected to the local wirings 241, 243, 244, 245 via vias, and is connected to the gate wiring 131e via a via. The metal wiring 252 is connected to the gate wirings 131a, 131b, 131c, 131d via vias, and is connected to the local wiring 248 via a via. The metal wiring 253 is connected to the local wirings 243, 244, 245, 247 via vias. The metal wiring 254 is connected to the gate wirings 136a, 136b, 136c, 136d via vias, and is connected to the local wiring 248 via a via.

[0115] According to this modification example, the same functions and effects as those of the above-described embodiment can also be obtained. Moreover, in this modification example, the sources and drains of the transistors other than the transistor N1 constituting the fixed value output section are not directly connected to VSS, so that device damage caused by ESD (Electro Static Discharge) can be suppressed.

[0116] It should be noted that, similar to Modification Example 1 of the second embodiment, the conductivity type of the transistor can also be replaced in this modification example.

[0117] It should be noted that in the above-described embodiments and modification examples, the power supply wirings for supplying VDD and VSS are BPR, but this is not limiting. For example, it can also be M1 wiring or the like.

[0118] In the above-described embodiments and modification examples, four M1 wirings extending in the X direction are formed, but a part of the M1 wirings can also be omitted.

[0119] -Industrial Applicability-

[0120] In the present disclosure, a layout structure of a large-capacity capacitor unit using a fork-sheet FET can be realized, and thus it is useful for, for example, improving the miniaturization and integration degree of a semiconductor chip.

[0121] -Symbol Explanation-

[0122] 5 Fixed-value output section

[0123] 11, 12 Power supply wiring

[0124] 21b, 21c, 21d, 23c, 26b, 26c, 26d, 28c Nanowires

[0125] 22b, 22c, 22d, 22e, 27b, 27c, 27d, 27e Pads

[0126] 24, 25 Nanowire section

[0127] 31b, 31c, 31d, 36b, 36c, 36d Gate wiring

[0128] 131b, 131c, 131d, 136b, 136c, 136d Gate wiring

[0129] 133b, 133c, 133d Bridge section

[0130] 142, 143, 144, 145 Local wiring

[0131] P1, P2, P3, P4, P5 P-type transistors

[0132] N1, N2, N3, N4, N5 N-type transistors

Claims

1. A semiconductor integrated circuit device includes a standard cell as a capacitor unit. The semiconductor integrated circuit device is characterized in that: In the standard cell, a P-type region where a P-type transistor is formed and an N-type region where an N-type transistor is formed are formed adjacent to each other in a first direction. The standard cell includes: A first nanosheet portion, a second nanosheet portion, a first gate wiring, a first pad pair, a second gate wiring, a second pad pair In the P-type region, the first nanosheet portion is composed of one nanosheet extending in a second direction perpendicular to the first direction or two or more nanosheets arranged in the first direction. In the N-type region, the second nanosheet portion is composed of one nanosheet extending in the second direction or two or more nanosheets arranged in the first direction. The first gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets of the first nanosheet portion in the first direction and a third direction perpendicular to the first direction and the second direction. The first pad pair is respectively connected to two end portions of the nanosheets of the first nanosheet portion in the second direction. The second gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets of the second nanosheet portion in the first direction and the third direction. The second pad pair is respectively connected to two end portions of the nanosheets of the second nanosheet portion in the second direction. The first pad pair and the second gate wiring are supplied with a first power supply voltage, and the second pad pair and the first gate wiring are supplied with a second power supply voltage lower than the first power supply voltage. The first nanosheet portion and the second nanosheet portion are opposed to each other in the first direction, and a surface of the nanosheet of the first nanosheet portion closest to the second nanosheet portion on the side of the second nanosheet portion in the first direction is exposed from the first gate wiring, and a surface of the nanosheet of the second nanosheet portion closest to the first nanosheet portion on the side of the first nanosheet portion in the first direction is exposed from the second gate wiring.

2. The semiconductor integrated circuit device according to claim 1, characterized in that: Each nanosheet of the first nanosheet portion and the second nanosheet portion is respectively composed of a single sheet structure or a plurality of sheet structures overlapping when viewed from above.

3. The semiconductor integrated circuit device according to claim 1, characterized in that: The first gate wiring and the second gate wiring are arranged at the same position in the second direction.

4. The semiconductor integrated circuit device according to claim 1, wherein: Including: A first power supply wiring, a second power supply wiring, and a fixed value output portion The first power supply wiring extends in the second direction and supplies the first power supply voltage. The second power supply wiring extends in the second direction and supplies the second power supply voltage. The fixed-value output unit is connected to the first power supply wiring and the second power supply wiring. The fixed-value output unit supplies the second power supply voltage to the first gate wiring and supplies the first power supply voltage to the second gate wiring. The fixed-value output unit includes a first P-type transistor and a first N-type transistor. The first P-type transistor is formed in the P-type region, and the source of the first P-type transistor is connected to the first power supply wiring. The first N-type transistor is formed in the N-type region, and the source of the first N-type transistor is connected to the second power supply wiring. The first gate wiring is electrically connected to the gate of the first P-type transistor and the drain of the first N-type transistor. The second gate wiring is electrically connected to the drain of the first P-type transistor and the gate of the first N-type transistor.

5. A semiconductor integrated circuit device, which includes a standard cell as a capacitor unit. The semiconductor integrated circuit device is characterized in that: In the standard cell, a first region in which a first-conductivity-type transistor is formed and a second region in which a second-conductivity-type transistor is formed are formed adjacent to each other in a first direction. The standard cell includes: A first nanosheet portion, a second nanosheet portion, a first gate wiring, a first pad pair, a second gate wiring, a second pad pair In the first region, the first nanosheet portion is composed of one nanosheet extending in a second direction perpendicular to the first direction or two or more nanosheets arranged in the first direction. In the second region, the second nanosheet portion is composed of one nanosheet extending in the second direction or two or more nanosheets arranged in the first direction. The first gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the first nanosheet portion in the first direction and a third direction, the third direction being perpendicular to the first direction and the second direction. The first pad pair is respectively connected to two end portions of the nanosheets included in the first nanosheet portion in the second direction. The second gate wiring extends in the first direction and is formed so as to surround the outer peripheries of the nanosheets included in the second nanosheet portion in the first direction and the third direction. The second pad pair is respectively connected to two end portions of the nanosheets included in the second nanosheet portion in the second direction. The first power supply voltage is supplied to the first gate wiring and the second gate wiring, and a second power supply voltage different from the first power supply voltage is supplied to the first pad pair and the second pad pair. The first nanosheet portion and the second nanosheet portion face each other in the first direction, and the surface of the nanosheet closest to the second nanosheet portion among the nanosheets included in the first nanosheet portion on the side closer to the second nanosheet portion in the first direction is exposed from the first gate wiring, and the surface of the nanosheet closest to the first nanosheet portion among the nanosheets included in the second nanosheet portion on the side closer to the first nanosheet portion in the first direction is exposed from the second gate wiring.

6. The semiconductor integrated circuit device according to claim 5, wherein: Each of the nanosheets included in the first nanosheet portion and the second nanosheet portion is formed of a single sheet-like structure or a plurality of sheet-like structures that overlap when viewed from above.

7. The semiconductor integrated circuit device according to claim 5, wherein: The first gate wiring and the second gate wiring are arranged at the same position in the second direction, The semiconductor integrated circuit device includes a gate connection portion that is formed between the first gate wiring and the second gate wiring and connects the first gate wiring and the second gate wiring.

8. The semiconductor integrated circuit device according to claim 5, wherein: Including: A first local wiring and a second local wiring, The first local wiring extends in the first direction and connects one pad of the first pad pair and one pad of the second pad pair, The second local wiring extends in the first direction and connects the other pad of the first pad pair and the other pad of the second pad pair.

9. The semiconductor integrated circuit device according to claim 5, wherein: The first conductivity type is P-type, the second conductivity type is N-type, The first power supply voltage is higher than the second power supply voltage.

10. The semiconductor integrated circuit device according to claim 5, wherein: The first conductivity type is N-type, the second conductivity type is P-type, The first power supply voltage is lower than the second power supply voltage.

11. The semiconductor integrated circuit device according to claim 5, wherein: Including: A first power supply wiring, a second power supply wiring, and a fixed value output portion, The first power supply wiring extends in the second direction and supplies the first power supply voltage, The second power supply wiring extends in the second direction and supplies the second power supply voltage, The fixed value output portion is connected to the first power supply wiring and the second power supply wiring, and the fixed value output portion supplies the first power supply voltage to the first gate wiring and the second gate wiring, The fixed value output portion includes a first transistor and a second transistor, The first transistor is formed in the first region, and the source of the first transistor is connected to the first power supply wiring, The second transistor is formed in the second region, and the source of the second transistor is connected to the second power supply wiring, The first gate wiring and the second gate wiring are electrically connected to the drain of the first transistor and the gate of the second transistor.

12. The semiconductor integrated circuit device according to claim 11, wherein: The fixed value output portion supplies the second power supply voltage to the first pad pair and the second pad pair, The first pad pair and the second pad pair are electrically connected to the gate of the first transistor and the drain of the second transistor.

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