Low-precision neural network data feature amplification system and method

Abstract

A data feature augmentation system and method for a low-precision neural network. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used to receive an input signal and obtain a first signal according to the input signal. The first signal is related to the first leakage rate of the first sample-and-hold circuit. The first signal is different from the input signal by a time unit. The subtractor is used to subtract the input signal from the first signal to obtain a time difference signal. The input signal and the time difference signal are input into the low-precision neural network.

Description

Technical Field

[0001] The present invention relates to a data feature augmentation system and method, and particularly to a data feature augmentation system and method for a low-precision neural network. Background Art

[0002] Neural Networks (NN) can be applied in different fields, such as image recognition and speech recognition. In the application of neural networks, there is a large amount of computational workload, such as hundreds of millions of multiplication and addition operations, which requires high-cost related hardware to achieve the performance of neural networks. To solve the problem of hardware resource consumption caused by the above huge computational workload, currently, the precision of the neural network can be reduced to convert the original high-precision neural network into a low-precision neural network for operation, so as to reduce the computational workload.

[0003] Although this method can reduce the computational workload and thus reduce the hardware resource consumption, the prediction accuracy of the low-precision neural network will also be affected and greatly reduced. Therefore, how to reduce the computational workload of the neural network while improving the prediction accuracy has become one of the key points for the industry to strive for. Summary of the Invention

[0004] The present invention relates to a data feature augmentation system and method for a low-precision neural network, which uses time difference operation to augment the features of input data, and can ensure the prediction accuracy of the low-precision neural network.

[0005] According to an embodiment of the present invention, a data feature augmentation system for a low-precision neural network is proposed. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample and hold circuit and a subtractor. The first sample and hold circuit is used to receive an input signal and obtain a first signal according to the input signal. The first signal is related to the first leakage rate of the first sample and hold circuit. The first signal is different from the input signal by one time unit. The subtractor is used to subtract the input signal from the first signal to obtain a time difference signal. The input signal and the time difference signal are input into the low-precision neural network.

[0006] According to another embodiment of the present invention, a data feature augmentation method for a low-precision neural network is proposed. The data feature augmentation method includes the following steps. Receive an input signal and obtain a first signal according to the input signal. The first signal is related to the first leakage rate of the first sample and hold circuit. The first signal is different from the input signal by one time unit. Subtract the input signal from the first signal to obtain a time difference signal. The input signal and the time difference signal are input into the low-precision neural network.

[0007] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but it is not limited to the present invention. Description of the Drawings

[0008] Figure 1 Schematic diagrams showing a data feature amplification system, a low-precision neural network, and global pooling according to an embodiment of the present invention;

[0009] Figure 2 Schematic diagram showing a time difference unit according to an embodiment of the present invention;

[0010] Figure 3 Schematic diagram showing a method for amplifying data features of a low-precision neural network according to an embodiment of the present invention;

[0011] Figure 4 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0012] Figure 5 Schematic diagram showing a method for amplifying data features of a low-precision neural network according to an embodiment of the present invention;

[0013] Figure 6 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0014] Figure 7 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0015] Figure 8 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0016] Figure 9 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0017] Figure 10 Schematic diagram showing a method for amplifying data features of a low-precision neural network according to an embodiment of the present invention;

[0018] Figure 11 Schematic diagram showing a time difference unit according to another embodiment of the present invention;

[0019] Figure 12 Schematic diagram of a time difference unit according to another embodiment of the present invention;

[0020] Figure 13 Schematic diagram of a time difference unit according to another embodiment of the present invention; and

[0021] Figure 14 Schematic diagram of a data feature amplification system according to another embodiment of the present invention.

[0022] Wherein, reference numerals:

[0023] 100, 1100: Data feature amplification system

[0024] 110: Time difference unit

[0025] 111-1: First sample and hold circuit

[0026] 111-2: Second sample and hold circuit

[0027] 111-K: Kth sample and hold circuit

[0028] 112: Subtractor

[0029] 120,1120: First analog-to-digital converter

[0030] 130,1130: Second analog-to-digital converter

[0031] 200,1200: Low-precision neural network

[0032] 300,1300: Global pooling

[0033] 402,902,904: Switch

[0034] 702,1202,1204: Multiplexer

[0035] 1110-1: First time difference unit

[0036] 1110-2: Second time difference unit

[0037] C1,C1’: First coefficient

[0038] C2,C2’: Second coefficient

[0039] CK,CK’: Kth coefficient

[0040] S: Input signal

[0041] S1: First signal

[0042] S2: Second signal

[0043] SK: Kth signal

[0044] TDS: Time difference signal

[0045] S’,TDS’,TDS2’: Digital signal

[0046] TDS1: First time difference signal

[0047] TDS2: Second time difference signal

[0048] S110,S120,S210,S220,S230,S310,S320: Steps

[0049] N1, N2, N3: Endpoints Detailed implementation manners

[0050] The structural principle and working principle of the present invention will be specifically described below with reference to the accompanying drawings:

[0051] Please refer to Figure 1 , which shows a schematic diagram of a data feature amplification system 100, a low-precision neural network 200, and a global pooling 300 according to an embodiment of the present invention. The data feature amplification system 100 includes a time difference unit 110, and optionally includes a first analog-to-digital converter 120 and a second analog-to-digital converter 130. The first analog-to-digital converter 120 and the second analog-to-digital converter 130 are low-resolution analog-to-digital converters. The time difference unit 110 can receive input data, such as an input signal S, and output a time difference signal TDS. The input signal S and the time difference signal TDS are analog signals. The input signal S and the time difference signal TDS can be directly input into the low-precision neural network 200.

[0052] In an embodiment, before the input signal S and the time difference signal TDS are input into the low-precision neural network 200, they are first respectively input into the first analog-to-digital converter 120 and the second analog-to-digital converter 130. The first analog-to-digital converter 120 converts the input signal S into a corresponding digital signal S'. The second analog-to-digital converter 130 converts the time difference signal TDS into a corresponding digital signal TDS'. Then, the digital signals S' and TDS' are input into the low-precision neural network 200. The low-precision neural network 200 is, for example, a binarized neural network or a low-resolution neural network. Then, the output of the low-precision neural network 200 is input into the global pool 300 for global pooling operation.

[0053] In this way, the present invention can perform a time difference operation on the input signal S through the time difference unit 110 to obtain a time difference signal TDS to amplify the features of the input signal S, and use the input signal S and the time difference signal TDS as the input of the low-precision neural network 200 to improve the prediction accuracy of the low-precision neural network 200. In addition, if it is necessary to convert the input signal S and the time difference signal TDS into digital signals and then input them into the low-precision neural network 200, the present invention only needs to use low-resolution analog-to-digital converters, which can save hardware costs and will not affect the prediction accuracy of the low-precision neural network 200.

[0054] There are multiple implementation manners for the time difference unit 110 to obtain the time difference signal TDS according to the input signal S, which will be further described below.

[0055] Please refer to Figures 1 to 3 . Figure 2 Schematic diagram showing the time difference unit 110 according to an embodiment of the present invention. Figure 3 Schematic diagram showing a data feature amplification method of the low-precision neural network 200 according to an embodiment of the present invention. In one embodiment, the time difference unit 110 includes a first sample and hold circuit 111-1 and a subtractor 112, as Figure 2 shown.

[0056] Step S110, the first sample and hold circuit 111-1 receives the input signal S and obtains a first signal S1 according to the input signal S. The first signal S1 is related to the first leakage rate of the first sample and hold circuit 111-1 and the first signal S1 differs from the input signal S by one time unit. Specifically, the first sample and hold circuit 111-1 samples and holds the input signal S and controls the first leakage rate of the first sample and hold circuit 111-1 to obtain the first signal S1. The first signal S1 can be expressed as C1*[S-1], where [S-1] is a signal that differs from the input signal S by one time unit, and C1 is a first coefficient that is related to the first leakage rate and the first coefficient C1 ranges between 0.5 and 1. The first leakage rate is adjustable, that is, the magnitude of the first coefficient C1 can be determined by adjusting the first leakage rate. Among them, the leakage rate is related to the RC constant of the sample and hold circuit, and the leakage rate can be changed by adjusting the resistance value or capacitance value of the sample and hold circuit. The leakage rate is, for example, the ratio of the voltage after leakage to the voltage before leakage when the charge stored in the capacitor used to hold the sampled value in the sample and hold circuit leaks at a certain proportional value (about 50% to 100%) to make the sampled value output by the sample and hold circuit smaller.

[0057] Step S120, the subtractor 112 subtracts the input signal S from the first signal S1 to obtain a time difference signal TDS. The time difference signal TDS can be expressed as S-C1*[S-1].[[]END]]

[0058] Please refer to Figure 1 、 Figure 4 、 Figure 5 . Figure 4 Schematic diagram showing the time difference unit 110 according to another embodiment of the present invention. Figure 5Illustrate a data feature amplification method for a low-precision neural network 200 according to an embodiment of the present invention. In one embodiment, the time difference unit 110 includes a first sample-and-hold circuit 111-1, a second sample-and-hold circuit 111-2, and a subtractor 112, and the first sample-and-hold circuit 111-1 and the second sample-and-hold circuit 111-2 are connected in parallel, and a switch 402 is used to input the input signal S to either the first sample-and-hold circuit 111-1 or the second sample-and-hold circuit 111-2, as Figure 4 shown. The switch 402 can also be implemented using a multiplexer.

[0059] Step S210, the first sample-and-hold circuit 111-1 receives the input signal S and obtains a first signal S1 according to the input signal S. The first signal S1 is related to the first leakage rate of the first sample-and-hold circuit 111-1 and the first signal S1 differs from the input signal S by one time unit. The manner in which the first sample-and-hold circuit 111-1 obtains the first signal S1 is as described above and will not be elaborated here. The first signal S1 can be expressed as C1*[S-1], where [S-1] is a signal that differs from the input signal S by one time unit (for example, the first signal S1 is the value [S-1] one clock cycle before the current input signal S multiplied by C1), and C1 is a first coefficient related to the first leakage rate and the first coefficient C1 ranges from 0.5 to 1. The first leakage rate is adjustable, that is, the magnitude of the first coefficient C1 can be determined by adjusting the first leakage rate.

[0060] Step S220, the second sample-and-hold circuit 111-2 receives the input signal S and obtains a second signal S2 according to the input signal S. The second signal S2 is related to the second leakage rate of the second sample-and-hold circuit 111-2 and the second signal S2 differs from the input signal S by two time units. Specifically, the second sample-and-hold circuit 111-2 samples and holds the input signal S and controls the second leakage rate of the second sample-and-hold circuit 111-2 to obtain the second signal S2. The second signal S2 can be expressed as C2*[S-2], where [S-2] is a signal that differs from the input signal S by two time units (for example, the second signal S2 is the value [S-2] two clock cycles before the current input signal S multiplied by C2), and C2 is a second coefficient related to the second leakage rate and the second coefficient C1 ranges from 0.5 to 1. The second leakage rate is adjustable, that is, the magnitude of the second coefficient C2 can be determined by adjusting the second leakage rate.

[0061] Step S230, the subtractor 112 subtracts the input signal S from the first signal S1 and the second signal S2 to obtain a time difference signal TDS. The time difference signal TDS can be expressed as S-C1*[S-1]-C2*[S-2].

[0062] An example is given as follows. Assume that the input signal S is a continuously streaming audio signal. Please also refer to Table 1 below, which lists an example of the values of the input signal S, the first signal S1, and the second signal S2 at time points t1 to t3. At time point t1, the terminals N1 and N2 of the switch 402 are electrically connected, so that the second sampling and holding circuit 111-2 samples and holds the input signal S (at this time, the value of the input signal S is, for example, S(t1)). At time point t2 (one clock cycle after time point t1), the second sampling and holding circuit 111-2 outputs the second signal S2, and the value of the second signal S2 is C2*[S-1], that is, the value of S ([S-1]) one clock cycle before time point t2 multiplied by C2, for example, C2*S(t1)).

[0063] Also at time point t2, the switch 402 is switched so that the terminals N1 and N3 of the switch 402 are electrically connected, and the first sampling and holding circuit 111-1 samples and holds the input signal S. At time point t3 (two clock cycles after time point t1), the first sampling and holding circuit 111-1 outputs the first signal S1, and the value of the first signal S1 is = C1*[S-1], that is, the value of S ([S-1]) one clock cycle before time point t3 multiplied by C1, for example, C1*S(t2)). At time point t3, the second sampling and holding circuit 111-2 continues to output the previously held second signal S2, that is, C2*S(t1), which is the value of S ([S-2]) two clock cycles before time point t3 multiplied by C2.

[0064] At this time, at time point t3, the subtractor 112 receives the first signal S1 output by the sampling and holding circuit 111-1 (= C1*[S-1], for example, C1*S(t2)), the second signal S2 output by the second sampling and holding circuit 111-2 (= C2*[S-2], for example, C2*S(t1)), and the current input signal S (for example, S(t3)), and performs a subtraction operation to obtain the time difference signal TDS (TDS = S - C1*[S-1] - C2*[S-2], for example, S(t3) - C1*S(t2) - C2*S(t1).

[0065] Table 1

[0066]

[0067] Please refer to Figure 6 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. Although Figure 4The first sample-and-hold circuit 111-1 and the second sample-and-hold circuit 111-2 are connected in parallel. However, in another embodiment, the first sample-and-hold circuit 111-1 and the second sample-and-hold circuit 111-2 may also be connected in series to perform steps S210 to S230, as Figure 6 shown. Figure 6 The time-difference signal TDS obtained by the time-difference unit 110 of can be expressed as S-C1*[S-1]-C2*[S-2].

[0068] An example is given as follows. Assume that the input signal S is a continuously streaming audio signal. Please also refer to Table II below, which lists an example of the values of the input signal S, the first signal S1, and the second signal S2 at time points t4 to t6. For example, at time point t4, the first sample-and-hold circuit 111-1 samples and holds the input signal S (the value of the input signal S at this time is, for example, S(t4)). At time point t5 (one clock cycle after time point t4), the first sample-and-hold circuit 111-1 outputs the first signal S1, and the value of the first signal S1 is C1’*[S-1], that is, the value of S ([S-1]) one clock cycle before time point t5 multiplied by C1’, for example, C1’*S(t4)), where C1’ = C1. The first sample-and-hold circuit 111-1 also samples and holds the input signal S again (the value of the input signal S at this time is, for example, S(t5)). Also at time point t5, the second sample-and-hold circuit 111-2 also samples and holds the first signal S1 (= C1’*[S-1], for example, C1’*S(t4)).

[0069] At time point t6 (two clock cycles behind time point t4), the first sample-and-hold circuit 111-1 samples and holds the input signal S again (at this time, the value of the input signal S is, for example, S(t6)), and the first sample-and-hold circuit 111-1 outputs a first signal S1. The value of the first signal S1 is C1'*[S-1], that is, the value of S ([S-1]) one clock cycle before time point t6 multiplied by C1', for example, C1'*S(t5). It is also the result of multiplying the input signal S sampled at time point t5 by C1' after being output by the first sample-and-hold circuit 111-1. At the same time, at time point t6, the second sample-and-hold circuit 111-2 samples and holds the first signal S1 (for example, C1'*S(t5)), and the second sample-and-hold circuit 111-2 outputs a second signal S2. The value of the second signal S2 is C2'*[S1-1]=C2'*C1'*[S-2]. That is, the value of S1 ([S1-1]) one clock cycle before time point t6 multiplied by C2', for example, C2'*S1(t5), which is also the value of S ([S-2]) two clock cycles before time point t6 multiplied by C2'*C1', for example, C2'*C1'*S(t4).

[0070] Thus, at time point t6, the subtractor 112 can obtain the second signal S2 (=C2'*C1'*[S-2]=C2*[S-2], where C2'*C1'=C2) from the output terminal of the second sample-and-hold circuit 111-2, and can simultaneously obtain the first signal S1 (=C1'*[S-1]) from the output terminal of the first sample-and-hold circuit 111-2, and can simultaneously receive the current input signal S to perform a subtraction operation to obtain the value of the time difference signal TDS (TDS = S - C1'*[S-1] - C1'*C2'*[S-2] = S - C1*[S-1] - C2*[S-2]).

[0071] Table 2

[0072]

[0073] Please refer to Figure 7 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. In one embodiment, the time difference unit 110 includes a first sample-and-hold circuit 111-1, a second sample-and-hold circuit 111-2... a Kth sample-and-hold circuit 111-K and a subtractor 112, and the first sample-and-hold circuit 111-1, the second sample-and-hold circuit 111-2... the Kth sample-and-hold circuit 111-K are connected in parallel, and a multiplexer 702 is used to input the input signal S to the first sample-and-hold circuit 111-1, the second sample-and-hold circuit 111-2... and the Kth sample-and-hold circuit 111-K at different time points respectively, as Figure 7As shown. In this embodiment, the time difference signal TDS obtained by the time difference unit 110 can be expressed as S - C1*[S - 1] - C2*[S - 2] - … - CK*[S - K]. Where [S - 1] is the signal that is one time unit different from the input signal S, C1 is the first coefficient, which is related to the first leakage rate and the first coefficient C1 ranges from 0.5 to 1. [S - 2] is the signal that is two time units different from the input signal S, C2 is the second coefficient, which is related to the second leakage rate and the second coefficient C1 ranges from 0.5 to 1. [S - K] is the signal that is K time units different from the input signal S, CK is the Kth coefficient, which is related to the Kth leakage rate and the Kth coefficient ranges from 0.5 to 1. The first leakage rate, the second leakage rate …, the Kth leakage rate are adjustable, that is, the magnitudes of the first coefficient C1, the second coefficient C2 … and the Kth coefficient can be determined by respectively adjusting the first leakage rate, the second leakage rate …, the Kth leakage rate. Figure 7 The way the time difference unit 110 obtains the time difference signal TDS is similar to Figure 4 that of the time difference unit 110 described above, and will not be elaborated here.

[0074] Please refer to Figure 8 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. Although Figure 7 the first sample and hold circuit 111 - 1, the second sample and hold circuit 111 - 2 … and the Kth sample and hold circuit 111 - K are connected in parallel, in another embodiment, the first sample and hold circuit 111 - 1, the second sample and hold circuit 111 - 2 … and the Kth sample and hold circuit 111 - K can also be connected in series, as Figure 8 shown. Figure 8 The time difference signal TDS obtained by the time difference unit 110 can also be expressed as S - C1*[S - 1] - C2*[S - 2] - … - CK*[S - K].

[0075] Please refer to Figure 1 , Figure 9 , Figure 10 . Figure 9 shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. Figure 10Illustrate a data feature amplification method for a low-precision neural network 200 according to an embodiment of the present invention. In one embodiment, the time difference unit 110 includes a first sample and hold circuit 111-1, a second sample and hold circuit 111-2, and a subtractor 112. The first sample and hold circuit 111-1 and the second sample and hold circuit 111-2 are connected in parallel, and a switch 902 is used to input the input signal S to the first sample and hold circuit 111-1 or the second sample and hold circuit 111-2, and another switch 904 is used to input the output of the first sample and hold circuit 111-1 or the output of the second sample and hold circuit 111-2 to the subtractor 112, as Figure 9 shown. Hereinafter, an example is given in which the switch 902 inputs the input signal S to the second sample and hold circuit 111-2, and another switch 904 inputs the output of the second sample and hold circuit 111-2 to the subtractor 112. The above-mentioned switch 902 and switch 904 can also be implemented using a multiplexer.

[0076] Step S310, the second sample and hold circuit 111-2 receives the input signal S and obtains a second signal S2 according to the input signal S. The second signal S2 is related to the second leakage rate of the second sample and hold circuit 111-2 and the second signal S2 is two time units different from the input signal S. Specifically, the second sample and hold circuit 111-2 samples and holds the input signal S and controls the second leakage rate of the second sample and hold circuit 111-2 to obtain the second signal S2. The second signal S2 can be expressed as C2*[S - 2], where [S - 2] is a signal that is two time units different from the input signal S, and C2 is a second coefficient that is related to the second leakage rate and the second coefficient C2 ranges from 0.5 to 1. The second leakage rate is adjustable, that is, the magnitude of the second coefficient C2 can be determined by adjusting the second leakage rate.

[0077] Step S320, the subtractor 112 subtracts the input signal S from the second signal S2 to obtain a time difference signal TDS. The time difference signal TDS can be expressed as S - C2*[S - 2].

[0078] Please refer to Figure 11 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. Although Figure 9 the first sample and hold circuit 111-1 and the second sample and hold circuit 111-2 of Figure 11 are connected in parallel, in another embodiment, the first sample and hold circuit 111-1 and the second sample and hold circuit 111-2 can also be connected in series to perform steps S310 and S320, as Figure 11 shown. The time difference signal TDS obtained by the time difference unit 110 of can be expressed as S - C2*[S - 2], where C2 is, for example, equal to C1’*C2’.

[0079] Please refer to Figure 12 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. In one embodiment, the time difference unit 110 includes a first sample and hold circuit 111-1, a second sample and hold circuit 111-2,..., a Kth sample and hold circuit 111-K, and a subtractor 112. The first sample and hold circuit 111-1, the second sample and hold circuit 111-2,..., and the Kth sample and hold circuit 111-K are connected in parallel, and a multiplexer 1202 is used to input the input signal S to the first sample and hold circuit 111-1, the second sample and hold circuit 111-2,..., or the Kth sample and hold circuit 111-K, and another multiplexer 1204 is used to input the output of the first sample and hold circuit 111-1, the output of the second sample and hold circuit 111-2, or the output of the Kth sample and hold circuit 111-K to the subtractor 112, as Figure 12 shown. Hereinafter, taking the multiplexer 1202 to input the input signal S to the Kth sample and hold circuit 111-K, and another multiplexer 1204 to input the output of the Kth sample and hold circuit 111-K to the subtractor 112 as an example. In this embodiment, the time difference signal TDS obtained by the time difference unit 110 can be expressed as S - CK * [S - K], where [S - K] is a signal that is K time units different from the input signal S, and CK is the Kth coefficient, which is related to the Kth leakage rate and the Kth coefficient C1 ranges from 0.5 to 1. The Kth leakage rate is adjustable, that is, the magnitude of the Kth coefficient can be determined by adjusting the Kth leakage rate. Figure 12 The way the time difference unit 110 obtains the time difference signal TDS is similar to that of Figure 9 the time difference unit 110 described above, and will not be elaborated here.

[0080] Please refer to Figure 13 , which shows a schematic diagram of the time difference unit 110 according to another embodiment of the present invention. Although Figure 12 the first sample and hold circuit 111-1, the second sample and hold circuit 111-2,..., and the Kth sample and hold circuit 111-K are connected in parallel, in another embodiment, the first sample and hold circuit 111-1, the second sample and hold circuit 111-2,..., and the Kth sample and hold circuit 111-K can also be connected in series, as Figure 13 shown. Figure 13 The time difference signal TDS obtained by the time difference unit 110 of

[0081] The present invention can adjust the ratio of the time difference operation by adjusting the leakage rate of the sample and hold circuit to obtain the time difference signal. In this way, the prediction accuracy of the low-precision neural network can be improved.

[0082] Please refer to Figure 14 which shows a schematic diagram of a data feature amplification system 1100 according to another embodiment of the present invention. In one embodiment, the data feature amplification system 1100 includes two time difference units. The data feature amplification system 1100 includes a first time difference unit 1110-1, a second time difference unit 1110-2, and optionally includes a first analog-to-digital converter 1120 and a second analog-to-digital converter 1130. The first time difference unit 1110-1 and the second time difference unit 1110-2 are connected in series. The first time difference unit 1110-1 can receive input data, such as an input signal S, and output a first time difference signal TDS1. The input signal S and the first time difference signal TDS1 are analog signals. The first time difference signal TDS1 is input to the second time difference unit 1110-2. Then, the second time difference unit 1110-2 outputs a second time difference signal TDS2. The input signal S and the second time difference signal TDS2 can be directly input to the low-precision neural network 1200.

[0083] In one embodiment, before the input signal S and the second time difference signal TDS2 are input to the low-precision neural network 1200, they are first respectively input to the first analog-to-digital converter 1120 and the second analog-to-digital converter 1130. The first analog-to-digital converter 1120 converts the input signal S into a corresponding digital signal S'. The second analog-to-digital converter 1130 converts the second time difference signal TDS2 into a corresponding digital signal TDS2'. Then, the digital signals S' and TDS2' are input to the low-precision neural network 1200. The low-precision neural network 1200 is, for example, a binary neural network or a low-resolution neural network. Then, the output of the low-precision neural network 1200 is input to a global pooling (Global pool) 1300 for global pooling operation. The first time difference unit 1110-1 and the second time difference unit 1110-2 can Figure 2 , Figure 4 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 13 be implemented by any of the time difference units shown.

[0084] Although Figure 14 the data feature amplification system 1100 is taken as an example including two time difference units, the present invention is not limited thereto. The data feature amplification system 1100 may include more time difference units, and these time difference units are connected in series.

[0085] In this way, the present invention can perform a time difference operation on the input signal S by cascading multiple time difference units to obtain a time difference signal TDS2, so as to amplify the features of the input signal S, and use the input signal S and the time difference signal TDS2 as the inputs of the low-precision neural network, so as to improve the prediction accuracy of the low-precision neural network 1200. In addition, if it is necessary to convert the input signal S and the time difference signal TDS2 into digital signals and then input them into the low-precision neural network 1200, the present invention only needs to use a low-resolution analog-to-digital converter, which can save hardware costs and will not affect the prediction accuracy of the low-precision neural network 1200.

[0086] Of course, the present invention may also have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention. However, these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A data feature amplification system for a low-precision neural network, characterized in that, it includes: A first time difference unit, including: A first sample and hold circuit for receiving an input signal and obtaining a first signal according to the input signal, the first signal being related to the first leakage rate of the first sample and hold circuit and the first signal differing from the input signal by one time unit; and A subtractor for subtracting the input signal from the first signal to obtain a time difference signal; wherein the input signal and the time difference signal are input to the low-precision neural network.

2. The data feature amplification system according to claim 1, characterized in that, wherein the input signal, the first signal and the time difference signal are analog signals, and the data feature amplification system further includes: A first analog-to-digital converter; and A second analog-to-digital converter; wherein the first analog-to-digital converter and the second analog-to-digital converter are low-precision analog-to-digital converters, and before the input signal and the time difference signal are input to the low-precision neural network, the input signal and the time difference signal are respectively input to the first analog-to-digital converter and the second analog-to-digital converter.

3. The data feature amplification system according to claim 1, characterized in that, wherein the low-precision neural network is a binary neural network or a low-resolution neural network.

4. The data feature amplification system according to claim 1, characterized in that, wherein the first time difference unit further includes: A second sample and hold circuit for receiving the input signal and obtaining a second signal according to the input signal, the second signal being related to the second leakage rate of the second sample and hold circuit and the second signal differing from the input signal by two time units; wherein the subtractor is further configured to subtract the input signal from the first signal and the second signal to obtain the time difference signal.

5. The data feature amplification system according to claim 4, characterized in that, wherein the first sample and hold circuit and the second sample and hold circuit are connected in series.

6. The data feature amplification system according to claim 4, characterized in that, wherein the first sample and hold circuit and the second sample and hold circuit are connected in parallel.

7. The data feature amplification system according to claim 4, characterized in that, wherein the first leakage rate and the second leakage rate are adjustable.

8. The data feature amplification system according to claim 1, characterized in that, wherein the first time difference unit further includes: A second sample and hold circuit for receiving the input signal and obtaining a second signal according to the input signal, the second signal being related to the second leakage rate of the second sample and hold circuit and the second signal differing from the input signal by two time units; wherein the subtractor is further configured to subtract the input signal from the second signal to obtain the time difference signal.

9. The data feature amplification system according to claim 8, characterized in that, wherein the first sample and hold circuit and the second sample and hold circuit are connected in series.

10. The data feature amplification system according to claim 8, characterized in that, The first sampling and holding circuit and the second sampling and holding circuit are connected in parallel.

11. The data feature amplification system according to claim 1, wherein, further comprising: a second time difference unit, connected in series after the first time difference unit, for obtaining a second time difference signal according to the time difference signal.

12. A method for amplifying data features of a low-precision neural network, wherein, comprising: receiving an input signal, and obtaining a first signal according to the input signal, the first signal being related to the first leakage rate of the first sampling and holding circuit and the first signal differing from the input signal by a time unit; and subtracting the input signal from the first signal to obtain a time difference signal; wherein the input signal and the time difference signal are input to the low-precision neural network.

13. The data feature amplification method according to claim 12, wherein, the input signal, the first signal and the time difference signal are analog signals, and the data feature amplification method further comprises: before the input signal and the time difference signal are input to the low-precision neural network, the input signal and the time difference signal are respectively input to a first analog-to-digital converter and a second analog-to-digital converter, and the first analog-to-digital converter and the second analog-to-digital converter are low-precision analog-to-digital converters.

14. The data feature amplification method according to claim 12, wherein, the low-precision neural network is a binary neural network or a low-resolution neural network.

15. The data feature amplification method according to claim 12, wherein, further comprising: receiving the input signal, and obtaining a second signal according to the input signal, the second signal being related to the second leakage rate of the second sampling and holding circuit, and the second signal differing from the input signal by two time units; and subtracting the input signal from the first signal and the second signal to obtain the time difference signal.

16. The data feature amplification method according to claim 15, wherein, the first leakage rate and the second leakage rate are adjustable.

17. The data feature amplification method according to claim 12, wherein, further comprising: receiving the input signal, and obtaining a second signal according to the input signal, the second signal being related to the second leakage rate of the second sampling and holding circuit, and the second signal differing from the input signal by two time units; and subtracting the input signal from the second signal to obtain the time difference signal.

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