Pixel Circuit and Display Panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a driving transistor, a writing transistor, a first transistor, and a potential boosting unit. By boosting the gate potential of the driving transistor after the working cycles of the writing transistor and the first transistor in one frame, the emission brightness can be reduced during the light-emitting stage, thereby offsetting the brightness change caused by the threshold voltage drift of the driving transistor due to multiple writings of the writing transistor.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a pixel circuit and a display panel. Background Art

[0002] When the pixel circuit is in the low-frequency operating mode and within one frame time, the data signal can be written to the gate of the driving transistor during the first operating cycle of the corresponding transistor. However, during the subsequent other operating cycles within the same frame, the data signal can only be written to one or two poles of the driving transistor other than the gate. With the continuous writing of the data signal in this way, the three-terminal voltages of the driving transistor will change. Affected by the hysteresis characteristic, the threshold voltage (Vth) of the driving transistor will shift, and ultimately the luminous brightness during the first operating cycle is inconsistent with the luminous brightness during the subsequent other operating cycles within the same frame. This brightness difference will cause regular changes in brightness, and further present serious flicker. Summary of the Invention

[0003] This application provides a pixel circuit and a display panel to alleviate the technical problem of the threshold voltage drift of the driving transistor in the low-frequency operating mode.

[0004] In a first aspect, this application provides a pixel circuit, which includes a driving transistor, a writing transistor, a first transistor, and a potential boosting unit. One of the source / drain of the writing transistor is connected to one of the source / drain of the driving transistor, the other of the source / drain of the writing transistor is connected to the data line, and the gate of the writing transistor is connected to the first control line; one of the source / drain of the first transistor is connected to the other of the source / drain of the driving transistor, the other of the source / drain of the first transistor is connected to the gate of the driving transistor, and the gate of the first transistor is connected to the gate of the writing transistor; the potential boosting unit is connected to the gate of the driving transistor and is used to boost the gate potential of the driving transistor after the operating cycles of the writing transistor and the first transistor in one frame.

[0005] In some embodiments, the potential boosting unit includes a composite capacitor. One end of the composite capacitor is connected to the gate of the driving transistor, and the other end of the composite capacitor is connected to the second control line.

[0006] In some embodiments, the composite capacitor includes a parasitic capacitor and a first capacitor. One end of the parasitic capacitor is connected to the gate of the driving transistor, and the other end of the parasitic capacitor is connected to the second control line; one end of the first capacitor is connected to the gate of the driving transistor, and the other end of the first capacitor is connected to the second control line.

[0007] In some of these embodiments, the driving transistor is a P-channel thin-film transistor, and the channel type of the writing transistor is the same as that of the first transistor; the first control line is used to transmit a first control signal, and the first control signal has at least one pulse during one operating cycle of the writing transistor and / or the first transistor.

[0008] In some of these embodiments, the pixel circuit further includes a first light-emitting control transistor, a second light-emitting control transistor, a light-emitting device, and a first initialization transistor. One of the source / drain electrodes of the first light-emitting control transistor is connected to the positive power supply line, and the other of the source / drain electrodes of the first light-emitting control transistor is connected to one of the source / drain electrodes of the driving transistor. The gate of the first light-emitting control transistor is connected to the light-emitting control line; one of the source / drain electrodes of the second light-emitting control transistor is connected to the other of the source / drain electrodes of the driving transistor, and the gate of the second light-emitting control transistor is connected to the light-emitting control line; the anode of the light-emitting device is connected to the other of the source / drain electrodes of the second light-emitting control transistor, and the cathode of the light-emitting device is connected to the negative power supply line; one of the source / drain electrodes of the first initialization transistor is connected to the anode of the light-emitting device, the other of the source / drain electrodes of the first initialization transistor is connected to the first initialization line, and the gate of the first initialization transistor is connected to the second control line.

[0009] In some of these embodiments, the pixel circuit further includes a storage capacitor and a second initialization transistor. One end of the storage capacitor is connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the positive power supply line; one of the source / drain electrodes of the second initialization transistor is connected to the gate of the driving transistor, and the other of the source / drain electrodes of the second initialization transistor is connected to the second initialization line. The gate of the second initialization transistor is connected to the third control line; wherein, in one frame, the operating cycle of the second initialization transistor is earlier than that of the writing transistor and / or the first transistor; the third control line is used to transmit a third control signal, and the third control signal has at least one pulse during one operating cycle of the second initialization transistor.

[0010] In some of these embodiments, the operating phases of the pixel circuit in one frame include an initialization phase, a writing phase, a potential boosting phase, and a light-emitting phase that are sequentially performed; the writing transistor and the first transistor operate in the writing phase, and the potential boosting unit operates in the potential boosting phase.

[0011] In some of these embodiments, the first initialization transistor operates in the potential boosting phase.

[0012] In some of these embodiments, the second initialization transistor operates in the initialization phase, and the first light-emitting control transistor and the second light-emitting control transistor operate in the light-emitting phase.

[0013] In a second aspect, the present application provides a display panel, which includes a plurality of pixel circuits in at least one of the above embodiments.

[0014] In the pixel circuit and the display panel provided by the present application, after the writing transistor and the first transistor complete their operating cycles in one frame, the potential boosting unit boosts the gate potential of the driving transistor, which can reduce the emission brightness during the light-emitting stage, thereby offsetting the brightness change caused by the threshold voltage drift of the driving transistor due to multiple writings of the writing transistor.

[0015] Moreover, the gates of the writing transistor and the first transistor share the same first control line, which can reduce the number of signal lines required for the pixel circuit and is beneficial to improving the aperture ratio of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0017] Figure 1 Schematic diagram of brightness difference caused by switching from high-frequency display to low-frequency display in the related art.

[0018] Figure 2 Schematic structural diagram of the pixel circuit provided by the embodiment of the present application.

[0019] Figure 3 For Figure 2 the timing diagram of the pixel circuit shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0021] Figure 1Schematic diagram of the brightness difference caused by the high-frequency display switching to the low-frequency display in the related art. The vertical axis represents brightness with the unit of nit, and the horizontal axis represents time, with the unit of second (s). At the corresponding resolution, the time of 1 frame at a refresh rate of 10 Hz is equivalent to the time of 12 frames at a refresh rate of 120 Hz. However, data signals of each frame can be written to the gate of the driving transistor at a refresh rate of 120 Hz. At a refresh rate of 10 Hz, data signals are only written to the gate of the driving transistor within the first 120 Hz frame time. In the subsequent 11 120 Hz frame times at a refresh rate of 10 Hz, data signals are not written to the gate of the driving transistor but are written to the source or drain of the driving transistor, resulting in Figure 1 a difference in brightness between the first 120 Hz frame time at a refresh rate of 10 Hz and the subsequent 11 120 Hz frame times as shown by the dashed box in Figure 1 . This brightness difference will cause the brightness to change regularly, and then present serious flicker.

[0022] In view of the technical problem of the threshold voltage drift of the driving transistor T1 in the low-frequency operating mode mentioned above, this embodiment provides a pixel circuit. Please refer to Figure 2 、 Figure 3 ,as shown in Figure 2 , the pixel circuit includes a driving transistor T1, a writing transistor T2, and a first transistor T3. One of the source / drain of the writing transistor T2 is connected to one of the source / drain of the driving transistor T1. The other of the source / drain of the writing transistor T2 is connected to the data line. The gate of the writing transistor T2 is connected to the first control line. One of the source / drain of the first transistor T3 is connected to the other of the source / drain of the driving transistor T1. The other of the source / drain of the first transistor T3 is connected to the gate of the driving transistor T1. The gate of the first transistor T3 is connected to the gate of the writing transistor T2.

[0023] It can be understood that the gates of the writing transistor T2 and the first transistor T3 share the same first control line, which can reduce the number of signal lines required for the pixel circuit and is beneficial to improving the aperture ratio of the display panel.

[0024] It should be noted that the channel types of the writing transistor T2 and the first transistor T3 are the same, and the writing transistor T2 and the first transistor T3 can be kept open or closed synchronously under the drive of the first control line.

[0025] In one embodiment, the pixel circuit further includes a potential boosting unit 10, which is connected to the gate of the driving transistor T1 and is used to boost the gate potential of the driving transistor T1 after the working periods of the writing transistor T2 and the first transistor T3 in one frame.

[0026] It can be understood that for the pixel circuit provided in this embodiment, after the potential lifting unit 10 lifts the gate potential of the driving transistor T1 after the working cycles of the writing transistor T2 and the first transistor T3 in one frame, the emission brightness can be reduced during the emission stage, thereby offsetting the brightness change caused by the threshold voltage drift of the driving transistor T1 due to multiple writings of the writing transistor T2.

[0027] Meanwhile, since the potential lifting unit 10 lifts the gate potential of the driving transistor T1 after the working cycles of the writing transistor T2 and the first transistor T3 in one frame, during the working cycles of the writing transistor T2 and the first transistor T3, the pulse amplitude of the data signal Data transmitted in the data line can be lower than before, that is, this reduces the charging voltage (VGMP) of the data signal Data at 0 gray level.

[0028] In one embodiment, the potential lifting unit 10 includes a composite capacitor Cboost. One end of the composite capacitor Cboost is connected to the gate of the driving transistor T1, and the other end of the composite capacitor Cboost is connected to the second control line.

[0029] It should be noted that the composite capacitor Cboost can be the parasitic capacitance between the second control line and the gate of the driving transistor T1. During the process of the signal potential in the second control line switching from a low potential to a high potential, it can further lift the gate potential of the driving transistor T1, thereby reducing the conduction angle of the driving transistor T1, reducing the emission current flowing through the driving transistor T1, and reducing the emission brightness.

[0030] In one embodiment, the composite capacitor Cboost includes a parasitic capacitance and a first capacitor. One end of the parasitic capacitance is connected to the gate of the driving transistor T1, and the other end of the parasitic capacitance is connected to the second control line; one end of the first capacitor is connected to the gate of the driving transistor T1, and the other end of the first capacitor is connected to the second control line.

[0031] It should be noted that since the parasitic capacitance objectively exists during the manufacturing process of the pixel circuit or the display panel and is inevitable, but its size is often difficult to control. Therefore, in this embodiment, a first capacitor with a controllable capacitance is added to further enhance the coupling effect between the second control line and the gate of the driving transistor T1, making the gate potential of the driving transistor T1 more stable.

[0032] In one embodiment, the pixel circuit further includes at least one of a first light-emitting control transistor T5, a second light-emitting control transistor T6, a light-emitting device D1, and a first initialization transistor T7. One of the source / drain of the first light-emitting control transistor T5 is connected to the positive power supply line, the other of the source / drain of the first light-emitting control transistor T5 is connected to one of the source / drain of the driving transistor T1, and the gate of the first light-emitting control transistor T5 is connected to the light-emitting control line. One of the source / drain of the second light-emitting control transistor T6 is connected to the other of the source / drain of the driving transistor T1, and the gate of the second light-emitting control transistor T6 is connected to the light-emitting control line. The anode of the light-emitting device D1 is connected to the other of the source / drain of the second light-emitting control transistor T6, and the cathode of the light-emitting device D1 is connected to the negative power supply line. One of the source / drain of the first initialization transistor T7 is connected to the anode of the light-emitting device D1, the other of the source / drain of the first initialization transistor T7 is connected to the first initialization line, and the gate of the first initialization transistor T7 is connected to the second control line.

[0033] It should be noted that the light-emitting device D1 can be one of an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode.

[0034] Among them, the first initialization line can reset the anode potential of the light-emitting device D1 through the first initialization transistor T7.

[0035] By sharing the same light-emitting control line for the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6, the number of signal lines required for the pixel circuit can be reduced, and thus the aperture ratio of the display panel can be improved.

[0036] In one embodiment, the pixel circuit further includes a storage capacitor Cst and a second initialization transistor T4. One end of the storage capacitor Cst is connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is connected to the positive power supply line; one of the source / drain of the second initialization transistor T4 is connected to the gate of the driving transistor T1, the other of the source / drain of the second initialization transistor T4 is connected to the second initialization line, and the gate of the second initialization transistor T4 is connected to the third control line.

[0037] It should be noted that the second initialization line can reset the gate potential of the driving transistor T1 through the second initialization transistor T4.

[0038] In one embodiment, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first initialization transistor T7, and the driving transistor T1 can be, but are not limited to, P-channel thin-film transistors, and specifically can also be low-temperature polycrystalline silicon thin-film transistors, so as to improve the dynamic performance of the pixel circuit. The writing transistor T2, the second initialization transistor T4, and the first transistor T3 can be, but are not limited to, N-channel thin-film transistors, and specifically can also be indium gallium zinc oxide thin-film transistors, so as to reduce the gate leakage current of the driving transistor T1.

[0039] In one embodiment, the first control line is used to transmit a first control signal, and the first control signal can be a scan signal Nscan(n). The second control line is used to transmit a second control signal, and the second control signal can be a scan signal Pscan. The third control line is used to transmit a third control signal, and the third control signal can be a scan signal Nscan(n - 1). The positive power supply line is used to transmit a positive power supply signal VDD, and the negative power supply line is used to transmit a negative power supply signal VSS. The potential of the positive power supply signal VDD is higher than the potential of the negative power supply signal VSS. The first initialization line is used to transmit a first initialization signal Vi_Ano. The second initialization line is used to transmit a second initialization signal Vi_G. The light-emitting control line is used to transmit a light-emitting control signal EM.

[0040] Wherein, in one frame, the working cycle of the second initialization transistor T4 is earlier than the working cycles of the writing transistor T2 and / or the first transistor T3; the third control signal has at least one pulse in one working cycle of the second initialization transistor T4.

[0041] Wherein, the first control signal has at least one pulse in one working cycle of the writing transistor T2 and / or the first transistor T3.

[0042] In one embodiment, as Figure 2 、 Figure 3 shown, the working phases of the pixel circuit in one frame include the following phases that are carried out successively:

[0043] Initialization phase S1: The light-emitting control signal EM is at a high potential, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in the off state; the scan signal Nscan(n - 1) has one or more pulses, and the second initialization transistor T4 is turned on once during the duration of each pulse. When there are multiple pulses, the second initialization signal Vi_G can reset the gate of the driving transistor T1 multiple times, further improving the reset effect. The scan signal Nscan(n) is at a low potential, and the writing transistor T2 and the first transistor T3 are both in the off state. The scan signal Pscan is at a high potential, and the first initialization transistor T7 is in the off state.

[0044] Writing stage S2: The light-emitting control signal EM is at a high potential, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in the off state; the scan signal Nscan(n - 1) is at a low potential, and the second initialization transistor T4 is in the off state. The scan signal Nscan(n) has one or more pulses, and the writing transistor T2 and the first transistor T3 are in the on state during each pulse duration. Each time the writing transistor T2 and the first transistor T3 are turned on, it will affect Figure 2 the potentials of point A, point B, and point Q in , resulting in unstable three-terminal voltages of the driving transistor T1 during the process of switching from a high-frequency display screen to a low-frequency (such as 10 Hz or 1 Hz, etc.) display screen, and causing a change in the conduction angle of the driving transistor T1. The scan signal Pscan is at a high potential, and the first initialization transistor T7 is in the off state.

[0045] Potential elevation stage S3: The light-emitting control signal EM is at a high potential, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in the off state; both the scan signal Nscan(n - 1) and the scan signal Nscan(n) are at low potentials, and the writing transistor T2, the first transistor T3, and the second initialization transistor T4 are in the off state. The scan signal Pscan switches from a low potential to a high potential, and the first initialization transistor T7 turns on to initialize the anode potential of the light-emitting device D1, and the gate potential of the driving transistor T1, that is, the potential of point Q, is elevated, which can compensate for the threshold voltage drift of the driving transistor T1 during the process of switching from a high-frequency display screen to a low-frequency (such as 10 Hz or 1 Hz, etc.) display screen caused by the potential changes of point A and point B, and further can maintain the light-emitting current flowing through the driving transistor T1.

[0046] Light-emitting stage S4: The light-emitting control signal EM is at a low potential, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in the on state; both the scan signal Nscan(n - 1) and the scan signal Nscan(n) are at low potentials, and the writing transistor T2, the first transistor T3, and the second initialization transistor T4 are in the off state. The scan signal Pscan is at a high potential, the first initialization transistor T7 is off, the driving transistor T1 is on, the light-emitting current flows through the driving transistor T1, and the light-emitting device D1 starts to emit light.

[0047] Among them, it is assumed that 1H = 1 second / (refresh frequency / number of rows) = frame time / number of rows, where the number of rows is the number of rows of sub-pixels in the display panel. The time interval between two adjacent pulses of the scan signal Nscan(n - 1) or the scan signal Nscan(n) should be greater than 1H to ensure the writing time for each row. At the same time, the time interval between the end moment of the working cycle of the scan signal Nscan(n - 1) and the start moment of the working cycle of the scan signal Nscan(n) should be greater than 1H, which can ensure that there is a time interval between the working cycle of the first transistor T3 and the working cycle of the second initialization transistor T4 without overlap, ensuring the normal operation of the pixel circuit.

[0048] In one embodiment, this embodiment provides a display panel, which includes a plurality of pixel circuits in at least one of the above embodiments.

[0049] It can be understood that for the display panel provided in this embodiment, after the working cycles of the writing transistor T2 and the first transistor T3 are written in one frame by the potential lifting unit 10, the gate potential of the driving transistor T1 is lifted, which can reduce the emission brightness during the emission stage, thereby offsetting the brightness change caused by the threshold voltage drift of the driving transistor T1 due to multiple writings of the writing transistor T2, and further facilitating the improvement of the brightness uniformity of the display panel.

[0050] Moreover, the gates of the writing transistor T2 and the first transistor T3 share the same first control line, which can reduce the number of signal lines required for the pixel circuit and is beneficial to improving the aperture ratio of the display panel.

[0051] In the above embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0052] The pixel circuit and the display panel provided in the embodiments of the present application have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized in that, Comprising: A driving transistor, which is a P-channel thin film transistor; A writing transistor, one of the source / drain of the writing transistor is connected to one of the source / drain of the driving transistor, the other of the source / drain of the writing transistor is connected to a data line, and the gate of the writing transistor is connected to a first control line; A first transistor, one of the source / drain of the first transistor is connected to the other of the source / drain of the driving transistor, the other of the source / drain of the first transistor is connected to the gate of the driving transistor, and the gate of the first transistor is connected to the gate of the writing transistor; A second light-emitting control transistor, one of the source / drain of the second light-emitting control transistor is connected to the other of the source / drain of the driving transistor, and the gate of the second light-emitting control transistor is connected to a light-emitting control line; A light-emitting device, the anode of the light-emitting device is connected to the other of the source / drain of the second light-emitting control transistor, and the cathode of the light-emitting device is connected to a negative power supply line; A first initialization transistor, one of the source / drain of the first initialization transistor is connected to the anode of the light-emitting device, the other of the source / drain of the first initialization transistor is connected to a first initialization line, and the gate of the first initialization transistor is connected to a second control line; A potential boosting unit, which is connected between the gate of the driving transistor and the second control line, and is used to boost the gate potential of the driving transistor after the writing transistor and the first initialization transistor are sequentially turned on in a frame and before the light-emitting device emits light.

2. The pixel circuit according to claim 1, characterized in that, The potential boosting unit includes a composite capacitor, one end of the composite capacitor is connected to the gate of the driving transistor, and the other end of the composite capacitor is connected to the second control line.

3. The pixel circuit according to claim 2, wherein The composite capacitor includes: A parasitic capacitor, one end of the parasitic capacitor is connected to the gate of the driving transistor, and the other end of the parasitic capacitor is connected to the second control line; A first capacitor, one end of the first capacitor is connected to the gate of the driving transistor, and the other end of the first capacitor is connected to the second control line.

4. The pixel circuit according to claim 2, wherein The channel type of the writing transistor is the same as that of the first transistor; the first control line is used to transmit a first control signal, and the first control signal has at least one pulse in one working cycle of the writing transistor and / or the first transistor.

5. The pixel circuit according to claim 2, wherein The pixel circuit further includes: A first light-emitting control transistor, one of the source / drain of the first light-emitting control transistor is connected to a positive power supply line, the other of the source / drain of the first light-emitting control transistor is connected to one of the source / drain of the driving transistor, and the gate of the first light-emitting control transistor is connected to a light-emitting control line.

6. The pixel circuit according to claim 5, wherein The pixel circuit further includes: A storage capacitor, one end of the storage capacitor is connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the positive power supply line; and A second initialization transistor, one of the source / drain electrodes of the second initialization transistor is connected to the gate of the driving transistor, the other of the source / drain electrodes of the second initialization transistor is connected to a second initialization line, and the gate of the second initialization transistor is connected to a third control line; Wherein, in one frame, the working period of the second initialization transistor is earlier than that of the writing transistor and / or the first transistor; the third control line is used to transmit a third control signal, and the third control signal has at least one pulse in a working period of the second initialization transistor.

7. The pixel circuit according to claim 6, wherein The working phases of the pixel circuit in one frame include an initialization phase, a writing phase, a potential boosting phase, and a light emitting phase that are sequentially performed one after another; The writing transistor and the first transistor operate in the writing phase, and the potential boosting unit operates in the potential boosting phase.

8. The pixel circuit according to claim 7, wherein The first initialization transistor operates in the potential boosting phase.

9. The pixel circuit according to claim 8, wherein The second initialization transistor operates in the initialization phase, and the first light emitting control transistor and the second light emitting control transistor operate in the light emitting phase.

10. A display panel, characterized in that, Comprising a plurality of pixel circuits according to any one of claims 1 to 9.

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