A testing method, system and storage medium for a storage chip

Abstract

The present invention discloses a test method for a storage chip, which at least includes: providing a chip to be tested and configuring a test unit on the chip to be tested; writing preset information into the chip to be tested and reading it out to obtain storage data to be verified; processing the storage data to be verified through the test unit to obtain trigger data, and accumulating part of the trigger data to obtain the cumulative check information of the chip to be tested; performing clustering processing on multiple pieces of cumulative check information to obtain the clustering center data of the multiple pieces of cumulative check information, and obtaining comparison information according to the clustering center data and the address data of the chip to be tested; and comparing the comparison information with the cumulative check information. If the comparison information and the cumulative check information are inconsistent, the chip to be tested is treated as a defective chip. The present invention provides a test method, system and storage medium for a storage chip, which can detect defective chips at low cost and high efficiency.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a test method, system, and storage medium for a storage chip. Background Art

[0002] During the manufacturing process of a storage chip, defective products may occur due to process limitations. To ensure that errors occurring in the chip are within a controllable range during use, after the chip is packaged, it is also necessary to perform package testing on the chip to confirm the structure and electrical functions of the manufactured semiconductor components, so as to ensure that the semiconductor components meet customer requirements.

[0003] In the case of high requirements for chip yield, if the quality of registers and random access memories (RAMs) does not meet the standards, it will have random and uncontrollable effects on the device. Summary of the Invention

[0004] The purpose of the present invention is to provide a test method, system, and storage medium for a storage chip, which can detect defective chips at low cost and high efficiency.

[0005] To solve the above technical problems, the present invention is implemented through the following technical solutions:

[0006] The present invention provides a test method for a storage chip, which at least includes:

[0007] Providing a chip to be tested, and configuring a test unit on the chip to be tested;

[0008] Writing preset information to the chip to be tested and reading it out to obtain storage data to be verified;

[0009] Processing the storage data to be verified through the test unit to obtain trigger data, and accumulating part of the trigger data to obtain the cumulative check information of the chip to be tested;

[0010] Performing clustering processing on multiple pieces of the cumulative check information to obtain the clustering center data of the multiple pieces of cumulative check information, and obtaining comparison information based on the clustering center data and the address data of the chip to be tested; and

[0011] Comparing the comparison information with the cumulative check information, and if the comparison information is inconsistent with the cumulative check information, treating the chip to be tested as a defective chip.

[0012] In an embodiment of the present invention, the step of writing the preset information to the chip to be tested includes:

[0013] Writing odd-type preset information to the registers and storage blocks of the chip to be tested and reading it out; and

[0014] Reset the chip under test, write even-type preset information to the register and the storage block, and then read it out.

[0015] In an embodiment of the present invention, the step of obtaining the trigger data includes:

[0016] When writing the odd-type preset information, invert the storage data to be verified; and

[0017] Set the last bit data of the inverted storage data to be verified as the trigger data.

[0018] In an embodiment of the present invention, the step of obtaining the trigger data includes: when writing the even-type preset information, set the last bit data of the storage data to be verified as the trigger data.

[0019] In an embodiment of the present invention, the step of obtaining the cumulative sum check information includes:

[0020] Accumulate the trigger data to obtain a cumulative sum data; and

[0021] Establish a mapping relationship between the cumulative sum data and the address data of the chip under test to obtain the cumulative sum check information.

[0022] In an embodiment of the present invention, the step of obtaining the cluster center data includes:

[0023] Obtain the average value of multiple pieces of the cumulative sum data; and

[0024] Obtain the cumulative sum data with the smallest difference from the average value, and use the cumulative sum data as the cluster center data.

[0025] In an embodiment of the present invention, the condition for accumulating the trigger data is: if the trigger data corresponds to a high-level signal, the test unit accumulates once until the trigger data is traversed.

[0026] In an embodiment of the present invention, the step of processing the storage data to be verified includes:

[0027] Set the last bit data of the storage data to be verified as the trigger data, and remove the last data of the storage data to be verified;

[0028] Set padding data, and set the first bit data of the storage data to be verified as the padding data to obtain verification data; and

[0029] Store the verification data and the device address information of the chip under test.

[0030] In an embodiment of the present invention, after obtaining the control information, a mapping relationship table is established between the control information and the preset information, and the mapping relationship table is stored in the test unit.

[0031] The present invention discloses a test system for a storage chip, including:

[0032] A configuration module for configuring a test unit on a chip under test;

[0033] A read-write module for writing preset information to and reading out the chip under test to obtain stored data to be verified;

[0034] A statistics module for processing the stored data to be verified through the test unit to obtain trigger data and verification data, and accumulating the trigger data to obtain the cumulative verification information of the chip under test;

[0035] A clustering module for clustering a plurality of the cumulative verification information to obtain clustering center data of the plurality of the cumulative verification information, and obtaining control information according to the clustering center data and the address data of the chip under test; and

[0036] A comparison module for comparing the control information and the cumulative verification information, and if the control information and the cumulative verification information are inconsistent, treating the chip under test as a defective chip.

[0037] The present invention discloses a computer-readable storage medium storing computer instructions, which when executed by a processor implement the test method for a storage chip as described in the present invention.

[0038] As described above, the present invention provides a test method, system and storage medium for a storage chip, which can quickly eliminate unqualified chips caused by physical damage of registers and memories, thereby improving the yield rate of chips at the time of factory shipment. Moreover, according to the test method and system provided by the present invention, without adding external packaging test circuits, it can also ensure low consumption and less occupation of chip resources, with extremely low test data redundancy, thereby saving test costs. According to the test method and system provided by the present invention, the test circuit area is extremely small, reaching 2% - 50% of the original test circuit area of the chip, while the test rate can be increased by at least 10 times, greatly reducing the hardware cost and test time cost of the chip. The test method and system for a storage chip provided by the present invention are applicable to chips with different storage information and initial states, have extremely high versatility, and can be started and stopped at any time, with high test efficiency.

[0039] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. Description of the Drawings

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0041] Figure 1 It is a flowchart of the test method for the test chip described in the present invention.

[0042] Figure 2 It is a schematic structural diagram of the chip to be tested.

[0043] Figure 3 It is a flowchart of step S20.

[0044] Figure 4 It is a flowchart of step S23.

[0045] Figure 5 It is a flowchart from step S24 to step S26.

[0046] Figure 6 It is a flowchart of step S30.

[0047] Figure 7 It is a schematic structural diagram of the test system described in the present invention.

[0048] Figure 8 It is a structural principle block diagram of an electronic device.

[0049] Figure 9 It is a structural principle block diagram of a computer-readable storage medium.

[0050] In the figure: 1, chip to be tested; 10, storage unit; 20, test unit; 201, read / write unit; 202, statistical unit; 203, accumulator; 204, data buffer; 205, address offset unit; 206, check enable unit; 207, reset unit; 30, register; 40, memory; 401, storage block; 50, processor; 60, storage device; 70, computer instruction; 701, computer-readable storage medium; 100, test system; 101, configuration module; 102, read / write module; 103, statistical module; 104, clustering module; 105, comparison module. Detailed implementation manners

[0051] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0052] A storage chip is a specific application of the concept of an embedded system chip in the storage industry. Storage chip products are widely used in various electronic devices, such as household appliances, mobile phones, smart terminal devices, smart home devices, and various industrial tools. When the chip is applied to the aerospace, vehicle-mounted, and military fields, extremely high requirements are also placed on registers and random access memories. In a chip, a register is a small storage area where data can be stored, used to temporarily store the data and operation results involved in operations. When the chip is operating, the register will directly affect the function call. A random access memory (RAM) can directly exchange data with a central processing unit (CPU) and is used to store a large amount of data information. When the chip is operating, the random access memory will affect the accuracy of data storage and exchange in the chip. After the chip is packaged, according to the packaging test method provided by the present invention, it can be used for the function test of the registers and random access memories in the chip, so as to screen out defective chips, so that the chips can be applied to fields with high yield requirements such as aerospace, vehicle-mounted, and military.

[0053] Please refer to Figures 1 to 3 As shown, the present invention provides a test method for a storage chip. The packaging test method can test the registers and random access memories in the storage chip, including step S10 of providing a chip to be tested and configuring a test unit on the chip to be tested.

[0054] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, in step S10, a test unit 20 is configured on the chip under test 1. Among them, the chip under test 1 includes a storage unit 10, and the storage unit 10 includes a plurality of registers 30 and a memory 40. Among them, the register 30 can be a basic register or a shift register. The memory 40 can be a random access memory, and the memory 40 includes a plurality of memory blocks 401. The test unit 20 includes a read / write unit 201, a statistical unit 202, an accumulator 203, a data buffer 204, and an address offset unit 205. The register 30 and the memory block 401 are electrically connected to the read / write unit 201, and the stored data in the register 30 and the memory block 401 can be retrieved through the read / write unit 201. The read / write unit 201 is electrically connected to the statistical unit 202, and the read / write unit 201 transmits the stored data to be verified to the statistical unit 202, and the statistical unit 202 processes the data to form verification data. The statistical unit 202 is electrically connected to the accumulator 203 and the data buffer 204, and the statistical unit 202 transmits the processed stored data to the accumulator 203 or the data buffer 204. The accumulator 203 processes the verification data to form cumulative verification information, or the statistical unit 202 directly stores the verification data in the data buffer 204. The accumulator 203 is electrically connected to the data buffer 204, and the verification data and the device address information of the register 30 or the memory block 401 are stored in the buffer module 204. The data buffer 204 is electrically connected to the address offset unit 205, and the address offset unit 205 is electrically connected to the read / write unit 201. The address offset unit 205 retrieves the device address information from the data buffer 204 and sequentially retrieves the register 30 and the memory block 401 according to the device address information.

[0055] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, the device address information includes the physical addresses and logical addresses of register 30 and storage block 401. In this embodiment, the address offset unit 205 can sequentially retrieve the stored data in register 30 and storage block 401 according to the physical address. On the chip under test 1, register 30 and storage block 401 have unique physical and logical addresses. A physical address comparison table of register 30 and storage block 401 is established in the address offset unit 205. During the test process, the stored data in register 30 and storage block 401 is sequentially retrieved according to the physical address comparison table. In another embodiment of the present invention, the address offset unit 205 can also sequentially retrieve register 30 and storage block 401 according to the logical addresses of register 30 and storage block 401. A logical address comparison table of register 30 and storage block 401 is set in the address offset unit 205. Among them, the number of registers 30 is, for example, n, and the number of storage blocks 401 is, for example, k. Specifically, numbers are set for register 30 and storage block 401, such as the first register, the second register, the third register to the nth register, and the (n + 1)th storage block, the (n + 2)th storage block to the (n + k)th storage block, etc. When setting the numbers, the present invention does not limit the order of the numbers. It is also possible to first set numbers for storage block 401, such as the first storage block, the second storage block to the kth storage block, and then set numbers for register 30, such as the (k + 1)th register, the (k + 2)th register to the (k + n)th register, etc. According to the numbers of register 30 and storage block 401, logical addresses are set for register 30 and storage block 401 to reduce the time spent on address retrieval and enable the address offset unit 205 to quickly retrieve the next device. In the present invention, register 30 and storage block 401 are in a serial test relationship. Different registers 30 and different storage blocks 401 are in a serial test relationship, occupying less circuit resources and enabling systematic traceability of test information.

[0056] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, the test unit 20 includes a check enable unit 206 and a reset unit 207. Among them, the check enable unit 206 is electrically connected to the read / write unit 201 and the statistics unit 202 to activate the read / write function of the read / write unit 201 and the statistics function of the statistics unit 202. The reset unit 207 is electrically connected to the read / write unit 201, the statistics unit 202, the data buffer 204, and the check enable unit 206. After each round of testing is completed, the read / write unit 201, the statistics unit 202, the data buffer 204, and the check enable unit 206 are reset by the reset unit 207 to facilitate the next round of testing.

[0057] Please refer to Figure 1As shown, in an embodiment of the present invention, when the chip under test 1 is shipped upstream, it already has pre-stored information internally. Therefore, in this embodiment, different preset information is written to the chip under test 1. Specifically, in step S20 of the test method for the storage chip, preset information is written to the chip under test and read out to obtain the storage data to be verified. The test unit processes the storage data to be verified to obtain trigger data and verification data, and sums up the trigger data to obtain the sum verification information of the chip under test. Among them, step S20 includes steps S21 to S24.

[0058] S21. Write preset information to the register and the storage block.

[0059] S22. Read out the storage data to be verified from the storage unit in sequence according to the address order of the register and the storage block.

[0060] S23. Process the storage data to be verified to obtain verification data and trigger data.

[0061] S24. Process the verification data and the trigger data.

[0062] S25. Determine whether the register and the storage block have been traversed. If the storage data in the register and the storage block has not been completely read, return to step S22. If the register and the storage block have been traversed, execute step S26.

[0063] S26. Obtain and record the sum verification information of the storage device.

[0064] Please refer to Figures 2 to 4As shown, in an embodiment of the present invention, in step S21, there are various types of preset information written to the register 30 and the memory block 401. In this embodiment, the written preset information includes odd-type preset information and even-type preset information. Among them, in the odd-type preset information, the number of odd bits is greater than or equal to the number of even bits. Taking a 16-bit binary number as an example, when the number of odd bits of the preset information is greater than or equal to, for example, 8 bits, the odd-type preset information is written to the storage unit 10. When the number of odd bits of the preset information is less than, for example, 8 bits, the even-type preset information is written to the storage unit 10. Specifically, the odd-type preset information is written to the register 30 and the memory block 401 to obtain the first check data. After the register 30 and the memory block 401 are traversed, the register 30 and the memory block 401 are reset, and then the even-type preset information is written to the register 30 and the memory block 401 to obtain the second check data. After the register 30 and the memory block 401 are traversed, the register 30 and the memory block 401 are reset to make the chip under test 1 return from the test state to the normal working state. In this embodiment, in step S21, the odd-type preset information is, for example, all 1s, and the even-type preset information is, for example, all 0s. Among them, all 1s or all 0s means writing 1 or 0 to each bit of the register 30 or the memory block 401. Among them, the register 30 is, for example, 16-bit or 32-bit. In this embodiment, the odd-type preset information is, for example, 16-bit 1s or 32-bit 1s, and the even-type preset information is, for example, 16-bit 0s or 32-bit 0s. In step S22, the address offset unit 205 sequentially retrieves the register 30 and the memory block 401 according to the device address information of the register 30 and the memory block 401. When the corresponding register 30 or memory block 401 is retrieved, the read / write unit 201 reads the storage data to be checked from the retrieved register 30 or memory block 401 and sends the read storage data to be checked to the statistical unit 202. In step S23, the statistical unit 202 processes the storage data to be checked to obtain the check data. Specifically, step S23 includes steps S231 to S235.

[0065] S231. Determine whether the preset information written to the storage unit in step S21 is odd-type preset information. If it is odd-type preset information, execute step S232. If it is not odd-type preset information, execute step S233.

[0066] S232. Invert the storage data to be checked.

[0067] S233. Obtain the last data of the storage data to be checked and use the last bit data as the trigger data.

[0068] S234. Remove the last bit data of the storage data to be checked and fill in the first bit data of the storage data to be checked to obtain the check data.

[0069] S235. Send the trigger data to the accumulator and send the verification data to the data buffer.

[0070] Please refer to Figures 2 to 4 As shown, in an embodiment of the present invention, preset information is written into the storage unit 10. According to the device address information sent by the address offset unit 205 to the read / write unit 201, the read / write unit 201 reads the storage data to be verified from the corresponding register 30 or storage block 401 and sends the storage data to be verified to the statistical unit 202. In step S231, the statistical unit 202 determines whether the preset information written into the storage unit 10 is odd-type preset information. If it is odd-type preset information, in step S232, each bit of the storage data to be verified is inverted. Specifically, the preset information is binary data, the data in the preset information is 1 or 0, data 1 is inverted to data 0, and data 0 is inverted to data 1. In step S233, the last bit of the storage data to be verified is used as the trigger data. In step S234, the last bit of the storage data to be verified is removed, and padding data is set, and the first bit of the storage data to be verified is set as the padding data to obtain the verification data. In step S235, the trigger data is obtained by the accumulator 203, and the verification data and the device address information of the corresponding device are stored in the data buffer 204. Among them, the verification data and the device address information are stored in the data buffer 204 correspondingly for data traceability.

[0071] Please refer to Figures 2 to 4As shown, in an embodiment of the present invention, when the written preset information is of odd type, taking the data to be verified and stored as 11011110 as an example, the data to be verified and stored 11011110 is inverted to obtain the data 00100001. The last bit data of the data 00100001 is 1, so the trigger data is 1. In step S234, the last bit data of the data to be verified and stored is removed, and the first bit data of the data to be verified and stored is filled in to obtain the verification data. Wherein, the filled data is, for example, 0. Taking the data 00100001 as an example, the last bit data 1 is removed to form the data 0010000, and then the filled data 0 is added to the first bit of the data 0010000 to obtain the verification data 00010000. Among them, the trigger data 1 is transmitted to the accumulator 203, and the verification data 00010000 is transmitted to the data buffer 204. When the written preset information is of even type, taking the data to be verified and stored as 11011110 as an example, the trigger data is 0, and the formed verification data is 01101111. Then the trigger data 0 is sent to the accumulator 203, and the verification data 01101111 is sent to the data buffer 204. In this embodiment, in step S21, the odd-type preset information is, for example, all 1s, such as 11111111, which is inverted to obtain 00000000, the trigger data is 0, and the verification data is 00000000. The even-type preset information is, for example, all 0s, such as 00000000, then the trigger data is 0, and the verification data is 00000000. In the case of normal reading, the consistency of the data is very high, so the efficiency of selecting abnormal devices is high, and the test data redundancy is low.

[0072] Please refer to Figures 2 to 5 As shown, in an embodiment of the present invention, in step S24, the verification data and the trigger data are processed to obtain the cumulative check information. The accumulator 203 receives the trigger data, sets the cumulative condition, and obtains the cumulative check information corresponding to the verification data according to the cumulative condition and the trigger data. Specifically, step S24 includes steps S241 to S243.

[0073] S241. Receive the trigger data sequentially according to the order of the device address information.

[0074] S242. Determine whether the trigger data corresponds to a high level. If the trigger data corresponds to a high level, execute step S243. If the trigger data does not correspond to a high level, execute step S25.

[0075] S243. The accumulator counts once.

[0076] Please refer to Figure 1 、 Figure 2 and Figure 5As shown, in an embodiment of the present invention, in step S241, the statistical unit 202 sends the trigger data to the accumulator 203, and the accumulator 203 receives the trigger data. In step S242, it is determined whether the trigger data corresponds to a high level. Specifically, when the trigger data is, for example, 1, the statistical unit 202 sends a clock signal with a high level to the accumulator 203. When the trigger data is, for example, 0, the statistical unit 202 sends a clock signal with a low level to the accumulator 203. In step S243, when the accumulator 203 receives a high-level clock signal, the accumulator 203 counts once. If the trigger data corresponds to a low-level signal, step S25 is executed to determine whether the registers 30 and the memory block 401 have been traversed until the accumulator 203 finishes processing the stored data of all the storage devices to be tested on the chip 1 to be tested. By combining the sum data in the accumulator 203 and the address data corresponding to the chip 1 to be tested, the sum check information is obtained. In step S26, the accumulator 203 sends the sum check information to the data buffer 204. During the actual test process, the number of hardware defects in the register 30 or the memory block 401 is limited. Therefore, the data compression degree of the sum check information obtained according to the present invention is high and the data volume is small. Among them, the number of bits of the data buffer 204 is, for example, 32 bits, which is sufficient to store the sum check information. If the stored data overflows, the sum check information retained in the data buffer 204 is, for example, 0xFFFFFFFF, and the sum check information is no longer updated.

[0077] Please refer to Figure 2 , Figure 4 and Figure 5As shown in the figure, in an embodiment of the present invention, in step S25, the address offset unit 205 retrieves the device address information from the data buffer 204. Specifically, the data buffer 204 stores multiple pieces of check data and device address information, and among them, the device address information is arranged in the order of numbers. The address offset unit 205 includes a starting address and an ending address. The starting address is the first device address for starting the test, and the ending address is the last device address during the test. The jump address can be the address linked to the read / write unit 201. Moreover, the starting address, jump address, and ending address of the address offset unit 205 can be pre-programmed in the firmware of the chip under test 1. The data buffer 204 can send an address offset signal to the chip under test 1. Each time an address offset signal is received, the address offset unit 205 can automatically jump once until the ending address is triggered. In other embodiments of the present invention, the address offset unit 205 can retrieve the device address information from the last block of the data buffer 204 or retrieve the device address information according to the number, so as to know the currently called register 30 or memory block 401. By comparing the device address information with the address look-up table, it can be known whether the current storage device is the last storage device. If it is not the last storage device, the address offset unit 205, according to the address look-up table, retrieves the device address information of the next storage device and sends the device address information to be retrieved to the read / write unit 201, and the read / write unit 201 reads the next storage device. If it is the last storage device, the reading ends.

[0078] Please refer to Figure 1 、 Figure 2 and Figure 6 As shown in the figure, in an embodiment of the present invention, according to the cumulative check information, it is determined how to process the chip under test 1. Among them, the package test method includes step S30, clustering the cumulative check information of multiple chips under test to obtain the clustering center data of multiple pieces of cumulative check information, and obtaining the comparison information according to the clustering center data and the address data of the chip under test. Specifically, step S30 includes steps S31 to S35.

[0079] S31. Sequentially obtain the cumulative check information of the chips under test.

[0080] S32. Obtain the average value of multiple pieces of cumulative check information.

[0081] S33. Obtain the cumulative check information with the smallest difference from the average value, and use the cumulative check information as the clustering center data.

[0082] S34. Determine whether the cumulative check information has been obtained completely. If not, return to step S31.

[0083] S35. Use the clustering center data as the control information, and establish a mapping relationship table between the control information and the preset information.

[0084] Please refer to Figure 1 , Figure 2 and Figure 6 As shown in the figures, in an embodiment of the present invention, in step S31, for example, there are m chips under test 1 in the same batch. For example, the m chips under test 1 can be synchronously tested or separately tested. In this embodiment, if the m chips under test 1 are synchronously tested, then in step S32, calculate the average value of the cumulative check information of the multiple chips under test 1. For example, when writing odd-type preset information to the chips under test 1, the cumulative check information of the multiple chips under test 1 are 4, 0, 4, 2, 10, 0, 4 respectively, and the average value is 4. In step S33, calculate the difference between the average value and the cumulative check information, and use the value of the cumulative check information with the smallest difference from the average value as the clustering center data. In this embodiment, the clustering center data is, for example, 4, so the control information is, for example, 4. In step S35, the control information corresponding to the odd-type preset information is, for example, 4. This embodiment is applicable to the large-scale synchronous testing of the chips under test 1, such as being applied to the factory testing of chips. In another embodiment of the present invention, the values of the chips under test 1 can be tested sequentially. Among them, in step S34, determine whether the cumulative check information has been obtained completely. If the cumulative check information has been obtained completely, then execute step S35 to obtain the control information. In step S34, if the cumulative check information has not been obtained completely, then return to step S31 to obtain the cumulative check information of the next chip under test 1. When the test unit 20 obtains the cumulative check information of the next chip under test 1, the clustering center data of the multiple cumulative check information that has been obtained can be calculated through the test unit 20, so as to improve the working efficiency of the test unit 20 in a limited circuit area. This embodiment is applicable to the small-scale testing of the chips under test 1, and can switch from the working state of the chips under test 1 to the test state at any time, with high test efficiency.

[0085] Please refer to Figure 1 , Figure 2 and Figure 6As shown, in an embodiment of the present invention, the written odd-type preset information is, for example, all 1s, and the written even-type preset information is, for example, all 0s. If there are no hardware defects in register 30 and memory block 401, the output trigger data should be 0, and the sum check information of the chip under test 1 is 0. In step S32, the average value of the sum check information of multiple chips under test 1 is, for example, 0. Therefore, in step S33, the cluster center data is, for example, 0, and the comparison information is, for example, 0. Among them, by writing odd-type preset information, the first comparison information is obtained. For example, when writing all 1s, the first comparison information is 0. By writing even-type preset information, the second comparison information is obtained. For example, when writing all 0s, the second comparison information is 0. In this embodiment, when there are hardware defects in register 30 and memory block 401, the obtained sum check information is greater than or equal to 1. In this embodiment, the mapping relationship table of the comparison information and the preset information obtained during the large-batch testing of the chips can be stored in the test unit 20, where the comparison information can be, for example, 0. When the chip under test 1 is, for example, 1 or 2, after obtaining the sum check information of the chip under test 1, the sum check information and the comparison information can be directly compared to quickly confirm whether there are device defects in the chip under test 1.

[0086] Please refer to Figure 1 、 Figure 2 and Figure 6 As shown, in an embodiment of the present invention, the package testing method includes step S40 of comparing the comparison information and the sum check information. When the comparison information and the sum check information are inconsistent, the chip under test is treated as a scrap chip. After obtaining the mapping relationship table of the comparison information and the preset information. For the chip under test 1, when writing odd-type preset information, compare the first comparison information and the sum check information of the chip under test 1. If the information is consistent, the chip under test 1 is a normal chip, and the chip under test 1 can continue to be used or the chip under test 1 can be warehoused for management. If the information is inconsistent, there are hardware defects in the chip under test 1, and the chip under test 1 is treated as a scrap chip. Among them, the comparison information includes the cluster center data and the address data of the chip under test 1. When detecting the sum check information, first match the address data of the chip under test 1, where the address data of the chip under test 1 can be the physical address of the chip under test 1 on the test bench or the logical address preset during the testing process of the chip under test 1, which is used to identify the corresponding chip under test 1. Then, according to the mapping relationship table, judge the comparison information corresponding to the written preset information, and compare the obtained sum check information with the comparison information.

[0087] Please refer to Figures 1 to 6As shown, in an embodiment of the present invention, in step S30, to reduce accidental errors, when the preset information is not written, the pre-stored information of the chip under test 1 is read out. The last bit data of the pre-stored information is used as the trigger data and sent to the accumulator 203 to obtain the accumulated data. The accumulated check information is obtained by synthesizing the accumulated data and the address data of the chip under test 1. Similarly, the clustering center data of multiple accumulated check information is obtained, and the reference information is obtained by synthesizing the clustering center data and the address data of the chip under test 1. The reference information and the accumulated check information are compared. If the reference information and the accumulated check information are inconsistent, the chip under test 1 is processed as a defective chip. Taking, for example, 3 registers 30 and 1 storage block 401 as an illustration, the pre-stored information includes, for example, 11100011, 10001111, 00001100, 00000000. The trigger data of the pre-stored information 11100011 is 1, and the check data is 01110001. The trigger data of the pre-stored information 10001111 is 1, and the check data is 01000111. The trigger data of the pre-stored information 00001100 is 0, and the check data is 00000110. The trigger data of the pre-stored information 00000000 is 0, and the check data is 00000000. Therefore, the accumulated data in this instance is 2. If the reference information is 2, the chip under test 1 can be warehoused for management. If the reference information is not 2, the chip under test 1 is processed as a defective chip.

[0088] Please refer to Figures 1 to 6 As shown, in an embodiment of the present invention, the check enable unit 206 sends an enable signal to the read / write unit 201. The read / write unit 201 writes odd-type preset information to all the registers 30 and the storage block 401 in the storage unit 10, and then reads out the storage data to be checked in the registers 30 and the storage block 401. The check enable unit 206 sends an enable signal to the statistical unit 202. The statistical unit 202 obtains the storage data to be checked and obtains the trigger data and the check data. The check data and the device address information are sent to the data buffer 204 for storage, and the data buffer 204 sends an address offset signal to the address offset unit 205 to enable the read / write unit 201 to read the registers 30 and the storage block 401 in address order. The trigger data is sent to the accumulator 203, and the accumulated check information is obtained through the accumulator 203. After the accumulated check information is obtained, the reset unit 207 sends a reset signal to reset the read / write unit 201, the check enable unit 206, the data buffer 204, and the statistical unit 202, so as to facilitate writing even-type preset information or returning the chip under test 1 to the working state. Among them, the enable signal is, for example, a high-level signal. Specifically, such as enable signal 1.

[0089] Please refer to Figures 1 to 6As shown, in an embodiment of the present invention, when the reset unit 207 sends a reset signal to the read-write unit 201, the check enable unit 206 continuously sends an enable signal to the read-write unit 201, thereby invalidating the written information, resetting the read-write unit 201, and resetting the storage unit 10, and the chip under test 1 returns to the working state. Before sending a reset signal to the statistical unit 202, the reset unit 207 sends a reset signal to the check enable unit 206, which can be specifically embodied as stopping the check enable unit 206 from sending the enable signal. The reset unit 207 sends a reset signal to the statistical unit 202, which is specifically embodied as stopping the statistical unit 202 from working. When the reset unit 207 sends a reset signal to the data buffer 204, the check enable unit 206 has stopped sending the enable signal. After receiving the reset signal, the internal cached data of the data buffer 204 is cleared. Specifically, the check information obtained by the present invention can be compressed to as low as, for example, 1 bit at the lowest, with a very high compression ratio, which can effectively save the storage space of the data buffer 204, is beneficial to reducing test data redundancy and circuit resource consumption, and improves the test efficiency and the application rate of the circuit area of the chip under test 1.

[0090] Please refer to Figure 1 , Figure 2 and Figure 7 As shown, the present invention provides a test system 100 for a storage chip. The test system 100 includes a configuration module 101, a read-write module 102, a statistical module 103, a clustering module 104, and a comparison module 105. The configuration module 101 is used to configure the test unit 20 on the chip under test 1. The read-write module 102 is used to write preset information to the chip under test 1 and read it out to obtain the storage data to be checked. The statistical module 103 is used to process the storage data to be checked through the test unit 20, thereby obtaining trigger data and check data, and accumulating the trigger data to obtain the cumulative check information of the chip under test 1. The clustering module 104 is used to perform clustering processing on multiple cumulative check information, obtain the clustering center data of multiple cumulative check information, and obtain comparison information according to the clustering center data and the address data of the chip under test 1. The comparison module 105 is used to compare the comparison information and the cumulative check information. If the comparison information and the cumulative check information are inconsistent, the chip under test 1 is treated as a defective chip.

[0091] Please refer to Figure 8As shown in the figure, the present invention also provides an electronic device, which includes a processor 50 and a storage device 60. The storage device 60 stores program instructions, and the processor 50 runs the program instructions to implement the above-mentioned test method for the storage chip. The processor 50 can be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it can also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; the storage device 60 may include a random access memory (RAM for short), and may also include a non-volatile memory, such as at least one disk memory. The storage device 60 can also be an internal memory of the random access memory (RAM) type. The processor 50 and the storage device 60 can be integrated into one or more independent circuits or hardware, such as: an application specific integrated circuit (ASIC). It should be noted that when the computer program in the above-mentioned storage device 60 can be implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium of a computer. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.

[0092] Please refer to Figure 9As shown in the figure, the present invention also provides a computer-readable storage medium 701, which stores computer instructions 70 for causing the computer to execute the above-mentioned test method for the storage chip. The computer-readable storage medium 701 can be an electronic medium, a magnetic medium, an optical medium, an electromagnetic medium, an infrared medium, or a semiconductor system or a propagation medium. The computer-readable storage medium 701 can also include a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and an optical disk. The optical disk can include a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-RW), and a digital versatile disc (DVD).

[0093] The present invention discloses a test method, system, and storage medium for a storage chip. A test unit is configured on the chip to be tested, and the memory and registers of the chip to be tested are read and written through the test unit. Specifically, the test unit writes preset information to the chip to be tested, reads the storage data to be verified from the chip to be tested, and then processes the storage data to be verified by the test unit to obtain trigger data for obtaining the cumulative check information and check data for data storage backup. Among them, the trigger data of all registers and storage blocks in the chip to be tested are accumulated to obtain the cumulative check information. And the cumulative check information of multiple chips to be tested is clustered to obtain reference information. The cumulative check information is compared with the reference information. When the cumulative check information is inconsistent with the reference information, the chip to be tested is treated as a defective chip.

[0094] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A test method for a storage chip, characterized in that, it at least includes: providing a chip under test and configuring a test unit on the chip under test; writing preset information into the chip under test and reading it out to obtain storage data to be verified; processing the storage data to be verified through the test unit to obtain trigger data, and accumulating part of the trigger data to obtain the cumulative check information of the chip under test; performing clustering processing on multiple pieces of the cumulative check information to obtain the clustering center data of the multiple pieces of the cumulative check information, and obtaining comparison information based on the clustering center data and the address data of the chip under test; and comparing the comparison information and the cumulative check information, and if the comparison information and the cumulative check information are inconsistent, treating the chip under test as a defective chip.

2. The test method for a storage chip according to claim 1, characterized in that, the step of writing the preset information into the chip under test includes: writing odd-type preset information into the register and storage block of the chip under test and reading it out; and resetting the chip under test and writing even-type preset information into the register and the storage block and reading it out.

3. The test method for a storage chip according to claim 2, characterized in that, the step of obtaining the trigger data includes: when writing the odd-type preset information, inverting the storage data to be verified; and setting the last bit data of the inverted storage data to be verified as the trigger data.

4. The test method for a storage chip according to claim 2, characterized in that, the step of obtaining the trigger data includes: when writing the even-type preset information, setting the last bit data of the storage data to be verified as the trigger data.

5. The test method for a storage chip according to claim 1, characterized in that, the step of obtaining the cumulative check information includes: accumulating the trigger data to obtain cumulative data; and establishing a mapping relationship between the cumulative data and the address data of the chip under test to obtain the cumulative check information.

6. The test method for a storage chip according to claim 5, characterized in that, the step of obtaining the clustering center data includes: obtaining the average value of multiple pieces of the cumulative data; and obtaining the cumulative data with the smallest difference from the average value and using the cumulative data as the clustering center data.

7. The test method for a storage chip according to claim 1, characterized in that, the condition for accumulating the trigger data is: if the trigger data corresponds to a high-level signal, the test unit accumulates once until the trigger data is traversed.

8. The test method for a storage chip according to claim 1, characterized in that, the step of processing the storage data to be verified includes: setting the last bit data of the storage data to be verified as the trigger data and removing the last data of the storage data to be verified; setting padding data and setting the first bit data of the storage data to be verified as the padding data to obtain verification data; and storing the verification data and the device address information of the chip under test.

9. A test method for a storage chip according to claim 1, characterized in that, after obtaining the comparison information, a mapping relation table is established between the comparison information and the preset information, and the mapping relation table is stored in the test unit.

10. A test system for a storage chip, characterized in that, comprising: a configuration module for configuring a test unit on a chip under test; a read-write module for writing preset information to and reading from the chip under test to obtain storage data to be verified; a statistics module for processing the storage data to be verified through the test unit to obtain trigger data and verification data, and accumulating the trigger data to obtain the cumulative verification information of the chip under test; a clustering module for performing clustering processing on multiple pieces of the cumulative verification information to obtain clustering center data of the multiple pieces of the cumulative verification information, and obtaining comparison information according to the clustering center data and the address data of the chip under test; and a comparison module for comparing the comparison information and the cumulative verification information, and if the comparison information and the cumulative verification information are inconsistent, treating the chip under test as a defective chip.

11. A computer-readable storage medium, characterized in that, the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the test method for the storage chip according to any one of claims 1 to 9 is implemented.

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