Memory address determination method and electronic device

Abstract

The present disclosure provides a memory address determination method and electronic device. The method includes: determining a first physical address set corresponding to each storage body of the memory to be tested; sequentially using multiple first feature functions in a first preset feature function set and multiple physical addresses in each first physical address set to perform bitwise AND operations to determine an array mapping function corresponding to the memory to be tested; determining a second physical address set corresponding to each storage body according to the array mapping function; determining a third physical address set corresponding to each storage body row in the second physical address set corresponding to each storage body; sequentially using multiple second feature functions in a second preset feature function set and each physical address in a third physical address set to perform bitwise AND operations to determine a row address mapping function corresponding to the third physical address set. The embodiment of the present disclosure can measure the mapping relationship between the physical address of the memory and the storage unit position of the memory.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a memory address determination method and electronic device. Background Art

[0002] In modern computer systems, in order to improve memory access efficiency and protect memory data, memory controller manufacturers generally deliberately hide the mapping relationship between system physical addresses and memory addresses. The physical address cannot be used to determine where the storage unit corresponding to the memory access event is located in the memory, nor can the relationship between physical addresses be known.

[0003] However, in integrated circuit manufacturing, there is an urgent need to know the mapping relationship between the system physical address and the memory address in some scenarios, such as failed storage unit location analysis (when a storage unit corresponding to a physical address is found to be failed during testing, the back-end technicians need to perform technical analysis on the failed storage unit, and at this time, it is necessary to find the specific location of the failed unit) or system row hammer test. In related technologies, oscilloscopes, logic analyzers and other instruments are usually used to assist in testing the correspondence between the physical address and the memory address of the storage unit, which is inefficient.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a memory address determination method and an electronic device, which are used to overcome the problem of low efficiency in the process of determining the correspondence between physical addresses and memory addresses, at least to a certain extent.

[0006] According to a first aspect of an embodiment of the present disclosure, a memory address determination method is provided, comprising: determining a first physical address set corresponding to each storage body of the memory to be tested according to whether the access time for consecutively accessing two physical addresses exceeds a preset time length, the first physical address set including multiple physical addresses belonging to the same storage body; sequentially using multiple first feature functions in a first preset feature function set to perform bitwise AND operations with multiple physical addresses in each of the first physical address sets to determine a mapping function set corresponding to the memory to be tested; determining an array mapping function corresponding to the memory to be tested according to the mapping function set; determining a second physical address set corresponding to each of the storage bodies according to the array mapping function, the second physical address set including multiple physical addresses belonging to the same storage body; determining a third physical address set corresponding to each storage body row in the second physical address set corresponding to each of the storage bodies according to whether the access time for consecutively accessing two physical addresses exceeds the preset time length, the third physical address set including multiple physical addresses belonging to the same storage unit row.

[0007] In an exemplary embodiment of the present disclosure, based on whether the access time for continuously accessing two physical addresses exceeds a preset time length, determining the first physical address set corresponding to each storage body of the memory to be tested includes: randomly determining a first physical address, and recording the first physical address in a first physical address set corresponding to the first storage body; randomly determining a second physical address, and performing a continuous access test on the first physical address and the second physical address; when the access time of the continuous access test exceeds a preset time length, recording the second physical address in the first physical address set corresponding to the first storage body, and when the access time does not exceed the preset time length, recording the second physical address in the first physical address set corresponding to the second storage body.

[0008] In an exemplary embodiment of the present disclosure, based on whether the access time for continuously accessing two physical addresses exceeds a preset time length, the method of determining the first physical address set corresponding to each storage body of the memory to be tested also includes: when the first physical address set corresponding to multiple storage bodies is not an empty set, randomly determining a third physical address, and performing the continuous access test on the third physical address and each physical address in the first physical address set respectively; when the access time of any continuous access test exceeds the preset time length, counting the third physical address into the first physical address set corresponding to another physical address in the continuous access test; when the access time of all the continuous access tests does not exceed the preset time length, counting the third physical address into a first physical address set corresponding to a new storage body; repeating the above steps until the physical addresses in the first physical address set corresponding to each storage body reach the first preset value.

[0009] In an exemplary embodiment of the present disclosure, when the access time of any continuous access exceeds the preset time length, counting the third physical address into the first physical address set corresponding to another physical address in the continuous access test includes: when the number of physical addresses in the first physical address set corresponding to the other physical address does not reach a first preset value, counting the third physical address into the first physical address set corresponding to the other physical address; otherwise, discarding the third physical address.

[0010] In an exemplary embodiment of the present disclosure, when the access time of all the continuous accesses does not exceed the preset time length, counting the third physical address into a first physical address set corresponding to a new storage body includes: when the access time of all the continuous accesses does not exceed the preset time length, re-selecting a physical address that is continuously accessed with the third physical address in each of the first physical address sets, and re-performing a continuous access test; when it is determined for the second time that the access time of all the continuous accesses does not exceed the preset time length, judging whether the number of non-empty storage bodies in the first physical address set is equal to the total number of storage bodies corresponding to the memory to be tested; if so, re-selecting a physical address that is continuously accessed with the third physical address in each of the first physical address sets, and re-performing a continuous access test; if not, counting the third physical address into a first physical address set corresponding to a new storage body.

[0011] In an exemplary embodiment of the present disclosure, the sequential use of multiple first feature functions in the first preset feature function set and multiple physical addresses in each of the first physical address sets to perform bitwise AND operations to determine the mapping function set corresponding to the memory to be tested includes: performing a bitwise AND operation on one of the first feature functions and one of the physical addresses to determine the number of bits equal to 1 in the calculation result, and when the number of bits is an odd number, recording the first feature function and the physical address as a first type of mapping, and when the number of bits is an even number, recording the first feature function and the physical address as a second type of mapping; when one of the first feature functions and each physical address in the first physical address set are both the first type of mapping or are both the second type of mapping, determining that the first feature function and the first physical address set have mapping consistency; when one of the first feature functions and the first physical address set corresponding to each storage body have the mapping consistency, recording the first feature function into the mapping function set corresponding to the memory to be tested.

[0012] In an exemplary embodiment of the present disclosure, the physical address and the first characteristic function are both M-bit binary numbers, and any two of the first characteristic functions are completely different. The sequential use of multiple first characteristic functions in the first preset characteristic function set and multiple physical addresses in each of the first physical address sets to perform bitwise AND operations to determine the mapping function set corresponding to the memory to be tested includes: determining multiple characteristic function groups in the first preset characteristic function set, the number of bits of the first characteristic function equal to 1 in the same characteristic function group is the same, and the number of bits of the first characteristic function equal to 1 in different characteristic function groups is different; in the characteristic function group that is not currently tested, setting the characteristic function group with the least number of bits equal to 1 as the characteristic function group to be tested; determining a first characteristic function to be tested in the characteristic function group to be tested, performing a bitwise AND operation on the first characteristic function to be tested and multiple physical addresses in each of the first physical address sets, and then re-determining another first characteristic function to be tested in the characteristic function group to be tested for operation until all the first characteristic functions corresponding to the characteristic function group to be tested are completed; and re-determining the characteristic function group to be tested until each of the characteristic function groups is completed.

[0013] In an exemplary embodiment of the present disclosure, determining the array mapping function corresponding to the memory to be tested according to the mapping function set includes: using Gaussian elimination method to operate on the mapping function set to obtain the array mapping function, and the array mapping function includes multiple linearly independent first characteristic functions.

[0014] In an exemplary embodiment of the present disclosure, the array mapping function includes X first characteristic functions, 2 X =m, m is the number of storage bodies in the memory to be tested, and the determining of the second physical address set corresponding to each storage body according to the array mapping function includes: randomly determining a plurality of target physical addresses; performing a bitwise AND operation on the i-th first characteristic function in the array mapping function and the target physical address, and when the number of bits that are 1 in the operation result is an odd number, recording the i-th bit of the array address of the target physical address as 1, and when the number of bits that are 1 in the operation result is an even number, recording the i-th bit of the array address of the target physical address as 0, 1≤i≤X; performing a bitwise AND operation on each of the first characteristic functions in the array mapping function and the target physical address to determine the array address of the target physical address; determining the array addresses corresponding to the plurality of target physical addresses, and recording the target physical addresses with the same array address as the second physical address set corresponding to one of the storage bodies.

[0015] In an exemplary embodiment of the present disclosure, determining the third physical address set corresponding to each storage body row in the second physical address set corresponding to each storage body according to whether the access time for continuously accessing two physical addresses exceeds a preset time length includes: randomly selecting a fourth physical address in the second physical address set corresponding to the storage body to be tested, and recording the fourth physical address in the third physical address set corresponding to the first storage cell row in the storage body to be tested; randomly determining a fifth physical address in the second physical address set corresponding to the storage body to be tested, and performing a continuous access test on the fourth physical address and the fifth physical address; when the access time does not exceed the preset time length, recording the fifth physical address in the third physical address set corresponding to the first storage cell row; when the access time of the continuous access test exceeds the preset time length, recording the fifth physical address in the third physical address set corresponding to the second storage cell row; performing the above-mentioned continuous access test on each physical address in the second physical address set corresponding to the storage body to be tested to determine the third physical address set corresponding to each storage cell row in the storage body.

[0016] In an exemplary embodiment of the present disclosure, the sequential use of multiple second characteristic functions in the second preset characteristic function set and each physical address in the third physical address set to perform a bitwise AND operation to determine the row address mapping function corresponding to the third physical address set includes: performing a bitwise AND operation on one of the second characteristic functions and each physical address in the third physical address set to obtain multiple operation results; when the operation results of the second characteristic function and each physical address in the third physical address set are the same, determining that the second characteristic function is the row address mapping function corresponding to the third physical address set; when any one of the operation results is different from the other operation results, re-determining another second characteristic function for operation.

[0017] In an exemplary embodiment of the present disclosure, the physical address and the second characteristic function are both M-bit binary numbers, the bit width of the row address of the memory to be tested is P, and in the second characteristic function, except for the lowest six bits, P bits are 1.

[0018] In an exemplary embodiment of the present disclosure, it also includes: randomly determining multiple groups of physical addresses, each group of physical addresses includes two different physical addresses; performing multiple continuous access tests on each group of physical addresses, and recording the median or average value of the access time of the multiple continuous access tests as the continuous access duration corresponding to each group of physical addresses; obtaining the statistical distribution of multiple continuous access durations corresponding to the multiple groups of physical addresses; and determining the preset duration based on the statistical distribution.

[0019] In an exemplary embodiment of the present disclosure, performing multiple consecutive access tests on each group of the physical addresses includes: executing a cache line clear instruction after each consecutive access test.

[0020] In an exemplary embodiment of the present disclosure, determining the memory address corresponding to an access event according to an array mapping function and a row address mapping function includes: determining a physical address corresponding to the access event; determining a target array address corresponding to the physical address according to the physical address and the array mapping function; determining a target row address in the target array address corresponding to the physical address according to the physical address and the row address mapping function; and setting the target array address and the target row address as the memory address corresponding to the access event.

[0021] According to a second aspect of the present disclosure, there is provided an electronic device, comprising: a memory to be tested; and a processor coupled to the memory to be tested, the processor being configured to execute a memory address determination method as described in any one of the above items based on instructions stored in the memory, so as to determine an array mapping function and a row address mapping function between a physical address of the processor and a storage unit of the memory to be tested.

[0022] The disclosed embodiment determines whether two physical addresses are located in the same array and the same row of the same array according to whether the access time of consecutively accessing the two physical addresses exceeds a preset time length, and can respectively determine the physical address set corresponding to each storage body and each row in the memory, and then determine the array mapping function and the row address mapping function of the memory to be tested according to the relationship between these physical address sets and the characteristic function, and then determine the memory address corresponding to each access event (including failed access events) according to the array mapping function and the row address mapping function. This can overcome the inefficient process of locating the memory address by using instruments such as oscilloscopes and logic analyzers in the related art, and improve the efficiency of memory testing.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0025] Figure 1 is a flowchart of a method for determining a memory address in an exemplary embodiment of the present disclosure.

[0026] Figure 2 This is a schematic diagram of the row conflict phenomenon that occurs during memory access.

[0027] Figure 3 It is a schematic diagram of determining conditions for determining occurrence of row conflicts in one embodiment of the present disclosure.

[0028] Figure 4 It is a schematic diagram of the statistical distribution of a large number of physical addresses to access time in one embodiment of the present disclosure.

[0029] Figure 5A and Figure 5B is a flowchart of step S1 in one embodiment of the present disclosure.

[0030] Figure 6 It is a sub-flow chart of step S2 in one embodiment of the present disclosure.

[0031] Figure 7 Schematic diagram of Gaussian elimination method in one embodiment of the present disclosure.

[0032] Figure 8 It is a sub-flow chart of step S5 in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0034] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0035] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0036] Figure 1 is a flowchart of a method for determining a memory address in an exemplary embodiment of the present disclosure.

[0037] refer to Figure 1 , the memory address determination method 100 may include:

[0038] Step S1, determining a first physical address set corresponding to each storage body of the memory to be tested according to whether the access time of continuously accessing two physical addresses exceeds a preset time length, wherein the first physical address set includes multiple physical addresses belonging to the same storage body;

[0039] Step S2, sequentially using a plurality of first characteristic functions in the first preset characteristic function set and a plurality of physical addresses in each of the first physical address sets to perform a bitwise AND operation, so as to determine a mapping function set corresponding to the memory to be tested;

[0040] Step S3, determining the array mapping function corresponding to the memory to be tested according to the mapping function set;

[0041] Step S4, determining a second physical address set corresponding to each of the storage bodies according to the array mapping function, wherein the second physical address set includes a plurality of physical addresses belonging to the same storage body;

[0042] Step S5, determining a third physical address set corresponding to each storage unit row in the second physical address set corresponding to each storage unit according to whether the access time of continuously accessing two physical addresses exceeds the preset time length, wherein the third physical address set includes multiple physical addresses belonging to the same storage unit row;

[0043] Step S6, sequentially using a plurality of second characteristic functions in the second preset characteristic function set and each physical address in the third physical address set to perform a bitwise AND operation to determine a row address mapping function corresponding to the third physical address set;

[0044] Step S7: determining a memory address corresponding to an access event according to the array mapping function and the row address mapping function.

[0045] The disclosed embodiment determines whether two physical addresses are located in the same array and the same row of the same array according to whether the access time of consecutively accessing the two physical addresses exceeds a preset time length, and can respectively determine the physical address set corresponding to each storage body and each row in the memory, and then determine the array mapping function and the row address mapping function of the memory to be tested according to the relationship between these physical address sets and the characteristic function, and then determine the memory address corresponding to each access event (including failed access events) according to the array mapping function and the row address mapping function. This can overcome the inefficient process of locating the memory address by using instruments such as oscilloscopes and logic analyzers in the related art, and improve the efficiency of memory testing.

[0046] Next, each step of the memory address determination method 100 is described in detail.

[0047] In step S1, according to whether the access time of continuously accessing two physical addresses exceeds a preset time length, a first physical address set corresponding to each storage body of the memory to be tested is determined, wherein the first physical address set includes multiple physical addresses belonging to the same storage body.

[0048] The storage array of DRAM (Dynamic Random Access Memory) consists of multiple banks, each of which includes multiple rows and columns of storage cells. Each bank corresponds to a row buffer, which is used to amplify signals and cache data for storage cells. When the memory controller accesses one or some storage cells in a row of DRAM, all storage cells in the row will be opened (activated), and the amplified signals in the storage cells will be stored in the row buffer so that the data in the row buffer can be read and written back to the storage cells after reading. When the memory controller accesses different rows of the same bank, it first reads the data of the previously accessed row through the row memory, then writes the data of the previously accessed row back to the storage cells of the previously accessed row, opens the row to be accessed later, amplifies the data in the storage cells of the later accessed row, and temporarily stores them in the row buffer for reading. This access process involves an extra wait for the row buffer contents to be written back to the storage unit of the previously accessed row, which increases the memory access time and is therefore called a row conflict.

[0049] Figure 2 This is a schematic diagram of the row conflict phenomenon that occurs during memory access.

[0050] refer to Figure 2When accessing a pair of memory addresses such as {addr_0, addr_1} continuously, after accessing the first address, the second address is accessed, and the following three situations may occur:

[0051] 201. The second address and the first address belong to the same row of the same storage bank 21, and use the same row buffer 21A. The data corresponding to the second access happens to be in the row buffer 21A, so there is no row conflict, and the access speed is very fast.

[0052] 202. The second address and the first address belong to different storage banks 21 and 22, and are accessed using different row buffers 21A and 22A. No row conflict occurs, and the access speed is very fast.

[0053] 203. The second address and the first address belong to different rows of the same storage body 21 and use the same row buffer 21A. The data in the row buffer needs to be written back to the storage unit of the row corresponding to the first address first, and then a row of storage units corresponding to the second address is opened and its content is read into the row buffer 21A. The access speed is slow and a row conflict occurs.

[0054] The inventor of the present application proposed a method for determining a memory address in the present application based on the above-mentioned DRAM access characteristics.

[0055] First, before doing actual testing, you can determine the conditions under which a row conflict occurs.

[0056] Figure 3 It is a schematic diagram of determining conditions for determining occurrence of row conflicts in one embodiment of the present disclosure.

[0057] refer to Figure 3 In one embodiment, the method 100 further includes:

[0058] Step S01, randomly determining multiple groups of physical addresses, each group of physical addresses including two different physical addresses;

[0059] Step S02, performing multiple continuous access tests on each group of physical addresses, and recording the median or average value of the access time of the multiple continuous access tests as the continuous access duration corresponding to each group of physical addresses;

[0060] Step S03, obtaining a statistical distribution of multiple continuous access durations corresponding to multiple groups of physical addresses;

[0061] Step S04, determining a preset duration according to statistical distribution.

[0062] In the embodiment shown in step S02, first, a pair of physical addresses (the physical address in the present disclosure is the system physical address used by the processor to access the storage / memory) can be randomly selected, and accessed r times continuously, and the access time of the pair of physical addresses is obtained by taking the median or the average. Then repeat this step p times to obtain the distribution of access time of m pairs of addresses. In order to ensure the accuracy of the result, the values ​​of r and p can be appropriately larger, such as r=40000, p=100000. In order to ensure that the memory access can be successfully operated to the DRAM, rather than the cache operation in the system, a cache line clear (clflush) instruction must be followed after each physical address is accessed. Access time measurement can be achieved through instructions such as rdtscp.

[0063] By plotting the obtained access time statistics in the graph, we can get the statistical distribution of access time for a large number of physical addresses. Figure 4 shown.

[0064] Depend on Figure 4 It can be seen that the access time intervals of a large number of physical address pairs can be divided into two clusters: the right cluster represents row conflicts during continuous access, so the access time is relatively long, and the left cluster represents continuous access devices without row conflicts, so the access time is relatively short. According to this statistical distribution, you can choose a value in the middle, such as Figure 3 The value 260ms in is used as the access time judgment threshold for judging whether row conflicts occur in continuous access, that is, the preset time length in steps S1 and S5.

[0065] according to Figure 3 The conditions for determining the occurrence of a row conflict obtained in the illustrated embodiment can determine a large number of physical addresses of different rows corresponding to the same memory bank.

[0066] Figure 5A and Figure 5B is a flowchart of step S1 in one embodiment of the present disclosure.

[0067] Figure 5A The sub-process of step S1 corresponding to the case where all first physical address sets are empty sets is shown. Figure 5B The sub-process of step S1 corresponding to the case where at least one first physical address set is not an empty set is shown. Figure 5A and Figure 5B The processes shown cooperate together to form the specific operation of step S1.

[0068] refer to Figure 5A In one embodiment, when all first physical address sets are empty, step S1 may include:

[0069] Step S11, randomly determining a first physical address, and recording the first physical address into a first physical address set corresponding to a first storage body;

[0070] Step S12, randomly determining a second physical address, and performing a continuous access test on the first physical address and the second physical address;

[0071] Step S13, determine whether the access time of the continuous access test exceeds the preset time length. If so, go to step S14 to record the second physical address into the first physical address set corresponding to the first storage body; if not, go to step S15 to record the second physical address into the first physical address set corresponding to the second storage body.

[0072] refer to Figure 5B In one embodiment, when the first physical address sets corresponding to the plurality of storage bodies are not empty sets, step S1 may include:

[0073] Step S16, randomly determining a third physical address, and performing a continuous access test on the third physical address and a physical address in each of the first physical address sets;

[0074] Step S17, determine whether the access time of any continuous access test exceeds the preset time length. If so, go to step S18 to count the third physical address into the first physical address set corresponding to another physical address in the continuous access test. If not, go to step S19 to count the third physical address into the first physical address set corresponding to a new storage body.

[0075] The above steps are repeated until the physical addresses in the first physical address set corresponding to each storage body reach the first preset value.

[0076] Wherein, step S18 further comprises:

[0077] Step S181, determine whether the number of physical addresses in the first physical address set corresponding to another physical address reaches a first preset value. If so, proceed to step S182 to count the third physical address into the first physical address set corresponding to another physical address. Otherwise, proceed to step S183 to discard the third physical address.

[0078] Step S19 further comprises:

[0079] Step S191, reselecting a physical address that is continuously accessed with the third physical address in each first physical address set, and re-performing a continuous access test;

[0080] Step S192, secondly determining whether the access time of any continuous access test exceeds the preset time length, if yes, proceeding to step S18; otherwise, proceeding to step S193;

[0081] Step S193, determine whether the number of storage bodies in the first physical address set that are not empty is equal to the total number of storage bodies corresponding to the memory to be tested. If so, return to step S191 to reselect a physical address that is continuously accessed with the third physical address in each first physical address set, and re-perform the continuous access test; otherwise, enter step S194 to count the third physical address into a first physical address set corresponding to a new storage body.

[0082] The purpose of limiting the number of addresses in each first physical address set in step S18 is to reduce the amount of computation in subsequent calculation of characteristic functions.

[0083] In step S19, a physical address that is continuously accessed with the third physical address is reselected in each first physical address set, and the continuous access test is re-performed. This is because when the access time of the continuous access does not exceed the preset time length, there are two situations. One situation is that the third physical address is not the address corresponding to the storage body that is not empty in the first physical address set, that is, the third physical address set corresponds to another new storage body; the other situation is that the physical address in the currently selected first physical address set has a physical address that is located in the same storage body and the same row as the third physical address. In order to avoid the second situation, when the access time of all continuous accesses does not exceed the preset time length, a batch of addresses can be reselected in the first physical address set and tested again.

[0084] If the access time of all the second consecutive accesses does not exceed the preset time length, and the first physical address set corresponding to the storage body is empty, it is highly likely that the third physical address set corresponds to a new storage body. Figure 5B In the illustrated embodiment, it is determined that the third physical address set corresponds to a new storage body only when the access time of two consecutive accesses does not exceed the preset time. In other embodiments of the present disclosure, it can be set that the third physical address set corresponds to a new storage body only when the access time of more consecutive accesses is determined to be less than the preset time.

[0085] If the number of non-empty first physical address sets is equal to the number of storage bodies, it means that the third physical address does not correspond to a new storage body, and there are still physical addresses in the same row as the third physical address in the batch of physical addresses compared this time. It is necessary to reselect a batch of physical addresses for testing until the physical addresses in the same row but different rows as the third physical address are determined, and the storage body corresponding to the third physical address set is determined.

[0086] It should be noted that although the setting of step S191 can prevent the third physical address and the physical addresses in the same storage body and row from being located in different first physical address sets to a certain extent, in order to further ensure that each first physical address set corresponds to a different storage body and prevent the use of physical addresses corresponding to the same storage body and the same row to generate multiple first physical address sets, in step S16 and step S191, when continuous access tests are performed on the third physical address and a physical address in each first physical address set respectively (assuming that the number of first physical address sets is x), after obtaining the test time of x continuous access tests, it is also possible to determine whether the access time of any continuous access test exceeds the preset duration.

[0087] Among these x access times, if there is only one access time that exceeds the preset duration, it can be determined that the third physical address corresponds to the storage body of another physical address in the access time; if two or more access times exceed the preset duration, it means that the third physical address corresponds to multiple first physical address sets at the same time, and the multiple first physical address sets belong to the same storage body and need to be merged; if no access time exceeds the preset duration, it can be determined that the access time of all continuous accesses does not exceed the preset duration, and at this time, step S19 or step S193 can be entered for the next step of processing.

[0088] Similarly, in Figure 5A In step S14, before recording the second physical address into the first physical address set corresponding to the second storage body, a physical address can be selected again from the first physical address set for a continuous access test to prevent the physical address during the first continuous access test from corresponding to the same storage body and the same row as the second physical address.

[0089] pass Figure 5A and Figure 5B The process shown can find a certain number of physical addresses for each storage body, generate the first physical address set corresponding to each storage body, and facilitate the subsequent induction of the regularity of the physical address corresponding to this storage body, thereby obtaining the physical address characteristic function of this storage body. Among them, the number of storage bodies in the memory module particles can refer to the JEDEC specification, for example, there are 16 storage bodies in the 8GbX8 specification memory.

[0090] Assuming that the number of storage banks in the memory to be tested is m, at the end of step S1, m first physical address sets can be obtained, which are:

[0091] m=Channels*(DIMMs / Channel)*(Ranks / DIMM)*(Banks / rank) (1)

[0092] Among them, Banks / rank is the number of memory banks in each rank (memory bank row) in the memory to be tested, Ranks / DIMM is the number of ranks in each DIMM (Dual In-line Memory Module), DIMMs / Channel is the number of DIMMs in each Channel, and Channels is the number of Channels in the memory to be tested.

[0093] The above m value can be used in step S193 as a basis for judgment.

[0094] In step S2, a plurality of first characteristic functions in the first preset characteristic function set are sequentially used to perform a bitwise AND operation with a plurality of physical addresses in each of the first physical address sets to determine a mapping function set corresponding to the memory to be tested.

[0095] After determining a plurality of physical addresses corresponding to a storage body (ie, a first physical address set), features may be extracted from the plurality of physical addresses.

[0096] In the art, a mapping function (Func-mask) is usually used to map memory addresses to physical addresses. For a memory address, it is calculated with the mapping function, and the calculation result is the physical address corresponding to the memory address. The goal of the embodiment of the present disclosure is to find the unknown mapping function.

[0097] It can be determined that the mapping function has a common effect on memory addresses with common points (such as the same memory bank, the same row). After analysis, it is found that after multiple memory addresses with common points are calculated by the mapping function, the multiple physical addresses obtained have parity consistency, that is, the number of bits of 1 in the physical address is all odd, or all even. In addition, the mapping function and the physical address are binary numbers with the same number of bits.

[0098] Based on the above analysis, the inventor of the present application sets up a method for finding a mapping function set corresponding to a first physical address set in step S2.

[0099] In the disclosed embodiment, in step S2, a first preset characteristic function set may be first obtained. The first preset characteristic function includes a plurality of different first characteristic functions, each of which is an M-bit binary number corresponding to the physical address, where M is a positive integer greater than or equal to 1. Each first characteristic function may be a mapping function in a mapping function set corresponding to a storage body.

[0100] After performing a bitwise AND operation on a first characteristic function and a physical address, determine the number of bits in the calculation result that are equal to 1. When the number of bits is an odd number, record the first characteristic function and the physical address as a first-type mapping, and when the number of bits is an even number, record the first characteristic function and the physical address as a second-type mapping. For example, the calculation result "10011010" of the 8-bit first characteristic function and the 8-bit physical address has an even number of 1s, and the corresponding first characteristic function and physical address are recorded as the second-type mapping. The calculation result "00011000" has an odd number of 1s, and the corresponding first characteristic function and physical address are recorded as the first-type mapping.

[0101] According to the above settings, a first characteristic function can be selected and calculated with each physical address in a first physical address set. If the first characteristic function and each physical address in the first physical address set are all first-type mappings or all second-type mappings, it can be determined that the first characteristic function and the first physical address set (i.e., the storage body) have mapping consistency, that is, the first characteristic function has the characteristics of the mapping function of the storage body.

[0102] Next, the first physical address set can be replaced for calculation. When the first characteristic function has mapping consistency with the first physical address set corresponding to each storage body, it means that the first characteristic function has the characteristics of the mapping function of each storage body and is a member of the mapping function set of the memory to be tested. At this time, the first characteristic function can be recorded in the mapping function set corresponding to the memory to be tested.

[0103] It should be noted that the types of mapping consistency (the number of bits whose calculation result is equal to 1 is an odd number or an even number) between the same first characteristic function and different storage bodies are not necessarily the same. For example, if the number of bits whose calculation result is equal to 1 between a first characteristic function and each physical address in the first physical address set of the first storage body is an odd number, and the number of bits whose calculation result is equal to 1 between the first characteristic function and each physical address in the first physical address set of the second storage body is an even number, then the first characteristic function has mapping consistency with the first storage body, and the first characteristic function also has mapping consistency with the second storage body.

[0104] Of course, if a first characteristic function does not have mapping consistency with each physical address in any first physical address set, then the first characteristic function must not be the mapping function of the memory to be tested. A first characteristic function can be reselected from the first preset characteristic function set for calculation until multiple first characteristic functions that meet the above requirements are obtained, forming a mapping function set corresponding to the memory to be tested.

[0105] In one embodiment of the present disclosure, since other characteristics of the mapping function are not known in advance, only the number of bits of the mapping function is known to be equal to M, which is the same as the number of binary bits of the physical address. The number of first characteristic functions in the first preset characteristic function set is huge. At this time, the order in which the first characteristic functions participate in the calculation can be set according to their own characteristics.

[0106] In one embodiment, a plurality of characteristic function groups in a first preset characteristic function set may be first determined, the first characteristic function in the same characteristic function group having the same number of bits equal to 1, and the first characteristic functions in different characteristic function groups having different numbers of bits equal to 1. Then, in the characteristic function group that is not currently being tested, the characteristic function group with the least number of bits equal to 1 is set as the characteristic function group to be tested. Next, a first characteristic function to be tested is determined in the characteristic function group to be tested, and after performing a bitwise AND operation on the first characteristic function to be tested and a plurality of physical addresses in each first physical address set, another first characteristic function to be tested is re-determined in the characteristic function group to be tested for operation, until all the first characteristic functions corresponding to the characteristic function group to be tested have completed the operation, and the characteristic function group to be tested is re-determined until each characteristic function group has completed the operation.

[0107] When describing the above process as a flow chart, it can be set that the number of bits whose first characteristic function in a characteristic function group Gi is equal to 1 is i.

[0108] Figure 6 It is a sub-flow chart of step S2 in one embodiment of the present disclosure.

[0109] refer to Figure 6 In one embodiment, step S2 may include:

[0110] Step S21, determine multiple characteristic function groups G1~GN in the first preset characteristic function set, where N is a preset value, N can be equal to the effective number of bits W of the memory physical address, N can also be less than W, and the effective number of bits W of the memory physical address is generally less than the bit width M of the memory physical address.

[0111] Step S22, set i=0.

[0112] Step S23, control i=i+1.

[0113] Step S24, select a first characteristic function in Gi to participate in the calculation, calculate the mapping consistency with the physical address in each first physical address set, and the calculation result includes adding the first characteristic function to the mapping function set or discarding the first characteristic function. After calculating a first characteristic function, enter step S25.

[0114] Step S25, determine whether all the first characteristic functions in the characteristic function group Gi participate in the calculation. If not, return to step S24 and reselect a first characteristic function in Gi to participate in the calculation. If yes, enter step S26.

[0115] Step S26, determine whether i is equal to N, that is, determine whether all first characteristic functions in all characteristic function groups have been calculated. If not, return to step S23 to add 1 to i and select the next characteristic function group. If yes, end step S2.

[0116] For example, the physical addresses in a first physical address set are:

[0117] 1100 0001 1011 1001 1100 1100 0111 1011,

[0118] When i=16, the first characteristic functions in G16 all have 16 bits set to 1, and one of the first characteristic functions is:

[0119] 1111 1111 1111 1111 0000 0000 0000 0000,

[0120] The first characteristic function is bitwise ANDed with the above physical address to obtain the calculation result:

[0121] 1100 0001 1011 1001 0000 0000 0000 0000,

[0122] Among the calculation results, 8 bits are 1, the number of bits that are 1 is an even number, and the first characteristic function and the physical address are a second type of mapping.

[0123] If the number of bits of 1 in the calculation results of the first characteristic function and all the physical addresses in the first physical address set is an even number, that is, they are all second-type mappings, it means that there is mapping consistency between the first characteristic function and the first physical address set. Otherwise, the first characteristic function is discarded.

[0124] If the first characteristic function has mapping consistency with each first physical address set, the first characteristic function is added to the mapping function set; otherwise, the first characteristic function is discarded.

[0125] In the embodiment shown in FIG5 , a 64-bit binary physical address (M=64) is used as an example for explanation. Generally speaking, there are 33 to 34 bits (W) corresponding to address bits in the 64-bit (M) physical address. At this time, setting the N value to less than 33, for example, 30 (N) can obtain a mapping function set that meets the requirements of the next step of calculation.

[0126] In step S3, the array mapping function corresponding to the memory to be tested is determined according to the mapping function set.

[0127] In the mapping function combination obtained in step S2, there may be multiple linearly related first eigenfunctions. Therefore, in step S3, Gaussian elimination method can be used to operate on the mapping function set to obtain an array mapping function, which includes multiple linearly independent first eigenfunctions.

[0128] Figure 7 Schematic diagram of Gaussian elimination method in one embodiment of the present disclosure.

[0129] refer to Figure 7 The mapping function set 71 includes 13 first characteristic functions 711 determined in step S2. After Gaussian elimination method, an array mapping function 72 is obtained. The array mapping function 72 includes 4 linearly independent first characteristic functions 711.

[0130] The array mapping function 72 is the array mapping function of the memory to be tested. By using the array mapping function to calculate multiple memory addresses with common points in the memory to be tested, multiple physical addresses with common characteristics can be obtained. Similarly, by using the array mapping function to calculate the physical addresses of the same memory body, the memory addresses obtained also have the same characteristics, which are the memory address characteristics of the memory body, also known as array address encoding.

[0131] In step S4, a second physical address set corresponding to each of the storage bodies is determined according to the array mapping function, wherein the second physical address set includes a plurality of physical addresses belonging to the same storage body.

[0132] In step S4, firstly, a plurality of target physical addresses may be randomly determined, and then the i-th first characteristic function in the array mapping function is bitwise ANDed with the target physical address. When the number of bits that are 1 in the operation result is an odd number, the i-th bit of the array address code of the target physical address is recorded as 1. When the number of bits that are 1 in the operation result is an even number, the i-th bit of the array address code of the target physical address is recorded as 0. 1≤i≤X, where X is the number of the first characteristic functions in the array mapping function, and there are 2 X =m, where m is the number of memory banks in the memory to be tested.

[0133] Assume that a target physical address is: 1100 0001 1011 1001 1100 1100 0111 1011, and the first first characteristic function in the array mapping function is: 1111 1111 1111 1111 0000 0000 0000 0000, and the result of the bitwise AND operation of the two is 8 bits are 1, then the first bit of the array address code of the target physical address is 0.

[0134] Next, each first characteristic function in the array mapping function is bitwise ANDed with the target physical address to determine the array address code of the target physical address. According to the calculation result of a target physical address and the i-th first characteristic function Func-mask-i, the i-th bit of the array address code Adbank of the target physical address is determined.

[0135] For example, assuming X=4, the array mapping function includes 4 first characteristic functions, and the bitwise AND operation results of the target physical address with the first, second, third, and fourth first characteristic functions are an even number of 1s, an even number of 1s, an odd number of 1s, and an odd number of 1s, respectively. Then the array address encoding of the target physical address is (0, 0, 1, 1).

[0136] According to the above process, array address codes corresponding to multiple target physical addresses are determined, and target physical addresses with the same array address codes are recorded as a second physical address set corresponding to a storage body. Each second physical address set includes multiple target physical addresses corresponding to the same storage body.

[0137] In this step, the multiple target physical addresses in the second physical address set may include the physical addresses in the first physical address set corresponding to the storage body. However, in order to make the number of target physical addresses corresponding to each storage body meet the subsequent calculation requirements of all row address mapping functions of each storage body, the selection range of the target physical address can be expanded, that is, a large number of target physical addresses can be randomly generated, so that the number of target physical addresses in the second physical address set corresponding to the same storage body is much larger than the number of physical addresses in the first physical address set.

[0138] In step S5, based on whether the access time for continuously accessing two physical addresses exceeds the preset time length, a third physical address set corresponding to each storage body row is determined in the second physical address set corresponding to each storage body, and the third physical address set includes multiple physical addresses belonging to the same storage unit row.

[0139] For each storage body, it can be set as the storage body to be tested during calculation. Next, a fourth physical address (also called a base address) can be randomly selected from the second physical address set corresponding to the storage body to be tested, and the fourth physical address can be recorded in the third physical address set corresponding to the first storage unit row in the storage body to be tested; a fifth physical address can be randomly determined in the second physical address set corresponding to the storage body to be tested, and a continuous access test is performed on the fourth physical address and the fifth physical address; when the access time does not exceed the preset time length, the fifth physical address is recorded in the third physical address set corresponding to the first storage unit row; when the access time of the continuous access test exceeds the preset time length, the fifth physical address is recorded in the third physical address set corresponding to the second storage unit row. According to the above logic, the above continuous access test is performed on each physical address in the second physical address set corresponding to the storage body to be tested to determine the third physical address set corresponding to each storage unit row in the storage body.

[0140] Converting the above logic into a flow chart, the total number of storage bodies can be set to m, a storage body Bi with serial number i corresponds to the second physical address set Adi, the number of target physical addresses in the second physical address set Adi is Qi, and the serial number of the target physical address is j.

[0141] Figure 8 It is a sub-flow chart of step S5 in one embodiment of the present disclosure.

[0142] refer to Figure 8 In one embodiment, step S5 may include:

[0143] Step S501, set i=1.

[0144] Step S502, setting j=1.

[0145] Step S503, setting the i-th memory bank Bi as the memory bank Bi to be tested, and setting the value of Qi according to the number of physical addresses in the second physical address set ADi corresponding to the memory bank Bi to be tested.

[0146] Step S504, determine whether j is equal to 1, if so, go to step S505, otherwise, go to step S506.

[0147] Step S505: randomly select a physical address A1 in ADi and record it into the third physical address set corresponding to the first storage unit row in the memory bank to be tested.

[0148] Step S506, randomly determine a fifth physical address Aj in ADi, select a fourth physical address in each third physical address set that is not an empty set, and perform a continuous access test on the fifth physical address Aj and each fourth physical address respectively.

[0149] Step S507, determine whether the access time exceeds the preset time length, if not, proceed to step S508, if yes, proceed to step S509.

[0150] Step S508: record the fifth physical address Aj into a third physical address set corresponding to a new storage unit row.

[0151] Step S509: record the fifth physical address Aj into the third physical address set of the storage unit row where the fourth physical address corresponding to the access time is located.

[0152] Step S510, determine whether j is equal to Qi, if so, go to step S511, otherwise, go to step S512 to add 1 to j and then return to step S506.

[0153] Step S511, determine whether i is equal to m, if not, go to step S513 to add 1 to i and then return to step S502, if yes, end step S5.

[0154] exist Figure 8 In the illustrated embodiment, since each physical address in the second physical address set corresponding to the same storage body to be tested corresponds to the same storage body, if the continuous access time of two physical addresses exceeds the preset time length, it means that the two physical addresses are located in different rows; if it does not exceed the preset time length, it means that the two physical addresses are located in the same row.

[0155] Therefore, after Figure 8 In the illustrated embodiment, a physical address set corresponding to each row of each memory bank, ie, a third physical address set, can be obtained, and then a row address mapping function can be extracted for each memory bank.

[0156] In step S6, a plurality of second characteristic functions in the second preset characteristic function set are sequentially used to perform a bitwise AND operation with each physical address in the third physical address set to determine a row address mapping function corresponding to the third physical address set.

[0157] Since some bits in the physical address can be combined to indicate the row address of the DRAM particle, in this step, the second preset feature function set can be determined first. The second preset feature function set includes multiple second feature functions, and each second feature function satisfies the conditions for becoming a row address mapping function of the memory to be tested. First, each second feature function is an M-bit binary number. Secondly, when the bit width of the row address of the memory to be tested is P, in the second feature function, except for the lowest six bits (the lowest six bits are used as the encoding of the cache line address), P bits are 1. According to the JEDEC specification, the number of rows of a memory particle of a certain specification is fixed. For example, the number of rows of a DDR4 DRAM particle of 8Gb XB specification is 65536 (216), so a width of 16 bits is occupied in the physical address to indicate the particle row address, P = 16.

[0158] Next, each second characteristic function may be used to perform calculations with a physical address in a third physical address set corresponding to a row of storage cells in a storage body to determine whether the second characteristic function is a row mapping function corresponding to the third physical address set.

[0159] The row mapping function corresponding to the third physical address set has the same effect on each physical address in the third physical address set. Therefore, in one embodiment, a second characteristic function can be bitwise ANDed with each physical address in a third physical address set to obtain multiple operation results. When the operation results of the second characteristic function and each physical address in the third physical address set are the same, the second characteristic function is determined to be the row address mapping function corresponding to the third physical address set; when any operation result is different from other operation results, another second characteristic function is re-determined for operation.

[0160] According to the above process, the array mapping function and the row mapping function corresponding to each storage bank and each storage bank row can be determined, and then the physical address and the memory address can be matched.

[0161] In step S7, the memory address corresponding to the access event is determined according to the array mapping function and the row address mapping function.

[0162] Access time includes read events and write events. Each memory access event performed by the processor corresponds to one or more physical addresses.

[0163] In one embodiment, the physical address corresponding to the access event can be first determined, and then the target array address corresponding to the physical address can be determined according to the physical address and the array mapping function, and the determination method is to perform a bitwise AND operation; next, the target row address in the target array address corresponding to the physical address can be determined according to the physical address and the row address mapping function, and the determination method is also to perform a bitwise AND operation. Finally, the target array address and the target row address are set as the memory address corresponding to the access event.

[0164] Through the method provided by the embodiment of the present disclosure, the memory address corresponding to each physical address can be quickly determined, that is, which storage bank and which row of storage units are currently being accessed, and then when an access failure occurs, the faulty storage unit can be quickly located. At the same time, in memory production tests such as row hammer tests, the method provided by the embodiment of the present disclosure can also greatly improve the test efficiency.

[0165] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided, the electronic device comprising: a memory to be tested; and a processor coupled to the memory to be tested, the processor being configured to execute a memory address determination method such as any one of the above based on instructions stored in the memory to determine an array mapping function and a row address mapping function between a physical address of the processor and a storage unit of the memory to be tested.

[0166] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0167] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of the present specification.

[0168] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0169] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A method for determining a memory address, characterized in that: include: Determine, according to whether the access time of continuously accessing two physical addresses exceeds a preset time length, a first physical address set corresponding to each storage body of the memory to be tested, wherein the first physical address set includes multiple physical addresses belonging to the same storage body; Sequentially use a plurality of first characteristic functions in the first preset characteristic function set and a plurality of physical addresses in each of the first physical address sets to perform a bitwise AND operation to determine a mapping function set corresponding to the memory to be tested; Determine the array mapping function corresponding to the memory to be tested according to the mapping function set; Determine a second physical address set corresponding to each of the storage bodies according to the array mapping function, wherein the second physical address set includes a plurality of physical addresses belonging to the same storage body; According to whether the access time of continuously accessing two physical addresses exceeds the preset time length, determining a third physical address set corresponding to each storage bank row in the second physical address set corresponding to each storage bank, wherein the third physical address set includes multiple physical addresses belonging to the same storage unit row; Sequentially use a plurality of second characteristic functions in the second preset characteristic function set to perform a bitwise AND operation with each physical address in the third physical address set to determine a row address mapping function corresponding to the third physical address set; A memory address corresponding to an access event is determined according to the array mapping function and the row address mapping function.

2. The memory address determination method according to claim 1, wherein: According to whether the access time of continuously accessing two physical addresses exceeds a preset time length, determining the first physical address set corresponding to each storage bank of the memory to be tested includes: Randomly determine a first physical address, and record the first physical address into a first physical address set corresponding to the first storage body; Randomly determine a second physical address, and perform a continuous access test on the first physical address and the second physical address; When the access time of the continuous access test exceeds the preset duration, the second physical address is recorded in the first physical address set corresponding to the first storage body; when the access time does not exceed the preset duration, the second physical address is recorded in the first physical address set corresponding to the second storage body.

3. The memory address determination method according to claim 2, wherein: According to whether the access time of continuously accessing two physical addresses exceeds a preset time length, the step of determining the first physical address set corresponding to each storage bank of the memory to be tested further includes: When the first physical address sets corresponding to the plurality of storage bodies are not empty sets, randomly determining a third physical address, and performing the continuous access test on the third physical address and each physical address in the first physical address set respectively; When the access time of any continuous access test exceeds the preset time length, the third physical address is counted into the first physical address set corresponding to another physical address in the continuous access test; When the access time of all the continuous access tests does not exceed the preset time length, counting the third physical address into a first physical address set corresponding to a new storage body; The above steps are repeated until the physical addresses in the first physical address set corresponding to each storage bank reach the first preset value.

4. The memory address determination method according to claim 3, wherein: When the access time of any continuous access exceeds the preset time length, counting the third physical address into the first physical address set corresponding to another physical address in the continuous access test comprises: When the number of physical addresses in the first physical address set corresponding to the other physical address does not reach a first preset value, the third physical address is counted into the first physical address set corresponding to the other physical address; otherwise, the third physical address is discarded.

5. The memory address determination method according to claim 3, characterized in that: When the access time of all the continuous accesses does not exceed the preset time length, counting the third physical address into a first physical address set corresponding to a new storage body includes: When the access time of all the continuous accesses does not exceed the preset time length, reselecting a physical address that is continuously accessed with the third physical address in each of the first physical address sets, and re-performing a continuous access test; When it is determined for the second time that the access time of all the continuous accesses does not exceed the preset time length, determining whether the number of storage bodies in the first physical address set that are not empty is equal to the number of all storage bodies corresponding to the memory to be tested; If yes, reselect a physical address that is continuously accessed with the third physical address in each of the first physical address sets, and re-perform a continuous access test; If not, the third physical address is counted into a first physical address set corresponding to a new storage body.

6. The memory address determination method according to claim 1, wherein: The sequentially using a plurality of first characteristic functions in the first preset characteristic function set and a plurality of physical addresses in each of the first physical address sets to perform a bitwise AND operation to determine a mapping function set corresponding to the memory to be tested includes: Performing a bitwise AND operation on a first characteristic function and a physical address to determine the number of bits in the calculation result that is equal to 1, and when the number of bits is an odd number, recording the first characteristic function and the physical address as a first type of mapping, and when the number of bits is an even number, recording the first characteristic function and the physical address as a second type of mapping; When the first characteristic function and each physical address in the first physical address set are both the first type of mapping or are both the second type of mapping, determining that the first characteristic function and the first physical address set have mapping consistency; When the first characteristic function and the first physical address set corresponding to each storage body have the mapping consistency, the first characteristic function is recorded in the mapping function set corresponding to the memory to be tested.

7. The memory address determination method according to claim 1 or 6, characterized in that: The physical address and the first characteristic function are both M-bit binary numbers, any two of the first characteristic functions are completely different, and the sequential use of multiple first characteristic functions in the first preset characteristic function set and multiple physical addresses in each first physical address set to perform bitwise AND operations to determine the mapping function set corresponding to the memory to be tested includes: Determine a plurality of characteristic function groups in the first preset characteristic function set, wherein the number of bits of the first characteristic function equal to 1 in the same characteristic function group is the same, and the number of bits of the first characteristic function equal to 1 in different characteristic function groups is different; Among the feature function groups that are not currently being tested, the feature function group with the least number of bits equal to 1 is set as the feature function group to be tested; Determine a first characteristic function to be tested in the characteristic function group to be tested, perform a bitwise AND operation on the first characteristic function to be tested and a plurality of physical addresses in each of the first physical address sets, and then determine another first characteristic function to be tested in the characteristic function group to be tested to perform the operation, until all the first characteristic functions corresponding to the characteristic function group to be tested have completed the operation; The characteristic function groups to be tested are re-determined until the operation of each characteristic function group is completed.

8. The memory address determination method according to claim 1, wherein: Determining the array mapping function corresponding to the memory to be tested according to the mapping function set comprises: The mapping function set is operated using Gaussian elimination method to obtain the array mapping function, wherein the array mapping function includes a plurality of linearly independent first eigenfunctions.

9. The memory address determination method according to claim 1, wherein: The array mapping function includes X first characteristic functions, 2 X =m, where m is the number of storage banks in the memory to be tested, and determining the second physical address set corresponding to each storage bank according to the array mapping function includes: Randomly determine multiple target physical addresses; Performing a bitwise AND operation on the i-th first characteristic function in the array mapping function and the target physical address, and when the number of bits that are 1 in the operation result is an odd number, recording the i-th bit of the array address of the target physical address as 1, and when the number of bits that are 1 in the operation result is an even number, recording the i-th bit of the array address of the target physical address as 0, 1≤i≤X; Performing a bitwise AND operation on each of the first characteristic functions in the array mapping function and the target physical address to determine an array address of the target physical address; Array addresses corresponding to the multiple target physical addresses are determined, and target physical addresses having the same array address are recorded as the second physical address set corresponding to one of the storage bodies.

10. The memory address determination method according to claim 1, wherein: Determining the third physical address set corresponding to each memory bank row in the second physical address set corresponding to each memory bank according to whether the access time of continuously accessing two physical addresses exceeds a preset time length comprises: Randomly select a fourth physical address in the second physical address set corresponding to the memory bank to be tested, and record the fourth physical address into the third physical address set corresponding to the first memory cell row in the memory bank to be tested; Randomly determine a fifth physical address in the second physical address set corresponding to the storage body to be tested, and perform a continuous access test on the fourth physical address and the fifth physical address; When the access time does not exceed the preset time length, recording the fifth physical address into a third physical address set corresponding to the first storage unit row; When the access time of the continuous access test exceeds a preset time length, recording the fifth physical address into a third physical address set corresponding to the second storage unit row; The above-mentioned continuous access test is performed on each physical address in the second physical address set corresponding to the memory bank to be tested, so as to determine a third physical address set corresponding to each memory cell row in the memory bank.

11. The memory address determination method according to claim 1, wherein: The step of sequentially using a plurality of second characteristic functions in the second preset characteristic function set and each physical address in the third physical address set to perform a bitwise AND operation to determine a row address mapping function corresponding to the third physical address set comprises: Performing a bitwise AND operation on one of the second characteristic functions and each physical address in the third physical address set to obtain a plurality of operation results; When the operation results of the second characteristic function and each physical address in the third physical address set are the same, determining that the second characteristic function is a row address mapping function corresponding to the third physical address set; When any one of the calculation results is different from the other calculation results, another second characteristic function is re-determined for calculation.

12. The memory address determination method according to claim 1 or 11, characterized in that: The physical address and the second characteristic function are both M-bit binary numbers, the bit width of the row address of the memory to be tested is P, and in the second characteristic function, except for the lowest six bits, P bits are 1.

13. The memory address determination method according to claim 1, wherein: Also includes: Randomly determine multiple groups of physical addresses, each group of physical addresses includes two different physical addresses; Perform multiple continuous access tests on each group of physical addresses, and record the median or average value of the access time of the multiple continuous access tests as the continuous access duration corresponding to each group of physical addresses; Obtaining a statistical distribution of a plurality of continuous access durations corresponding to the plurality of groups of physical addresses; The preset duration is determined according to the statistical distribution.

14. The memory address determination method according to claim 13, wherein: The performing of multiple continuous access tests on each group of the physical addresses comprises: After each of the consecutive access tests, a cache line clear instruction is executed.

15. The memory address determination method according to claim 1, wherein: Determining the memory address corresponding to the access event according to the array mapping function and the row address mapping function comprises: Determining a physical address corresponding to the access event; Determine a target array address corresponding to the physical address according to the physical address and the array mapping function; Determine a target row address in the target array address corresponding to the physical address according to the physical address and the row address mapping function; The target array address and the target row address are set as memory addresses corresponding to the access event.

16. An electronic device, characterized in that: include: Memory to be tested; as well as A processor coupled to the memory to be tested, the processor being configured to execute the memory address determination method as described in any one of claims 1 to 15 based on instructions stored in the memory to determine an array mapping function and a row address mapping function between a physical address of the processor and a storage unit of the memory to be tested.

Images