Integrated circuit devices, apparatuses, and manufacturing methods

Abstract

Provided are an integrated circuit device, an apparatus, and a manufacturing method to configure a circuit in a manner overlapping a connection pad to achieve a small area, and to achieve appropriate lead-out wiring to electrically connect the connection pad and the circuit. The integrated circuit device includes a connection pad having a shape with a long side direction and a short side direction; a circuit that overlaps the connection pad when viewed from above and is electrically connected to the connection pad; lead-out wiring that is led out from an outer edge of the connection pad on the long side side in the short side direction of the connection pad; and a via group that electrically connects the lead-out wiring and wiring of the circuit, which does not overlap the connection pad when viewed from above.

Description

Technical Field

[0001] This invention relates to integrated circuit devices, equipment, and manufacturing methods. Background Technology

[0002] Integrated circuit devices are provided with connection pads for external connections. For example, Patent Document 1 discloses a method in which the connection pad, which is provided along the side edge of the integrated circuit device, is formed into a rectangle having a long side that is in the direction of ultrasonic vibration when the lead wires are joined. In Patent Document 1, a connection pad shape corresponding to the lead wire joining connection portion that is approximately elliptical in the direction of ultrasonic vibration when viewed from above is provided, thereby achieving miniaturization of the integrated circuit device.

[0003] Patent Document 1: Japanese Patent Application Publication No. 6-333974

[0004] However, in the structure of Patent Document 1, where the circuit is configured to overlap with the connecting plate when viewed from above, no method is proposed for leading appropriate wiring to the circuit. Summary of the Invention

[0005] One aspect of this disclosure relates to an integrated circuit device comprising: a connection disk having a shape having a long side direction and a short side direction; a circuit that overlaps with and is electrically connected to the connection disk in a top view; lead-out wiring that extends from the outer edge of the long side of the connection disk along the short side direction; and a via group that electrically connects the lead-out wiring to the wiring of the circuit, and does not overlap with the connection disk in a top view.

[0006] Another aspect of this disclosure relates to a method of manufacturing an apparatus comprising an integrated circuit device and a package housing the integrated circuit device. The method includes: a manufacturing step of the integrated circuit device; and a mounting step of mounting the integrated circuit device onto the package. In the manufacturing step, a connection pad having a shape having a long side direction and a short side direction is formed on the active surface of the integrated circuit device; a circuit that overlaps with the connection pad in plan view and is electrically connected to the connection pad; lead-out wiring extending from the outer edge of the long side of the connection pad along the short side direction; and a via group electrically connecting the lead-out wiring to the wiring of the circuit, which does not overlap with the connection pad in plan view. In the mounting step, a bump is formed on the connection pad of the integrated circuit device, and the integrated circuit device is configured such that the active surface faces the surface of the package. Terminals disposed on the surface of the package are connected to the bump formed on the connection pad by ultrasonic bonding with the long side direction of the connection pad as the vibration direction. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of the connection disk area of ​​the integrated circuit device in this embodiment.

[0008] Figure 2 This is a top view of the connection disk area of ​​the integrated circuit device in this embodiment.

[0009] Figure 3 This is an example of the layout configuration for the input connection disk.

[0010] Figure 4 This is an example of the layout configuration for the output connection disk.

[0011] Figure 5 This is an example of the layout configuration of the ground connection panel.

[0012] Figure 6 This is a layout configuration example for routing multiple lead-out wires from the connection panel.

[0013] Figure 7 This is an explanatory diagram of the protrusions formed on the connecting disc.

[0014] Figure 8 This is an illustration of the problems in ultrasonic bonding.

[0015] Figure 9 This is a diagram illustrating a construction example of a connecting disk.

[0016] Figure 10 This is a structural example of the integrated circuit device in this embodiment.

[0017] Figure 11 This is an example of the structure of a reference voltage generation circuit.

[0018] Figure 12 This is another example of the structure of a reference voltage generation circuit.

[0019] Figure 13 This is an example of the layout configuration of an integrated circuit device.

[0020] Figure 14 This is a construction example of the oscillator used in this embodiment.

[0021] Figure 15 This is a manufacturing process diagram of the manufacturing method of this embodiment.

[0022] Label Explanation

[0023] 2: Connecting pad; 3: Passivation film; 4: Oscillator; 5: Lead-out wiring; 6: Through-hole group; 7: Wiring; 8: Circuit; 9: Second lead-out wiring; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18: External terminal; 19: External terminal; 20: Integrated circuit device; 21: ESD protection circuit; 22: I / O circuit; 30: Oscillator circuit; 50: Output circuit; 52: Output buffer circuit; 60: Power supply circuit; 62: Reference voltage generation circuit; 64: Regulator; 70: Logic circuit; 80: Temperature compensation circuit; 90: Temperature sensor circuit; 91: Connecting pad metal; 92, 93, 94: Conductive layer; ALA~ALE: Metal layer; BMP: Bump; BP1, BP2, BP3: Bipolar transistor; CKQ: Clock signal; DI1, DI2, DI3: Diode; DL: Long side direction; DR, DR1, DR2, DR3, DR4: Direction; DS: Short side direction; EDL, EDS: Outer edge; OE: Output enable signal; OSC: Oscillation signal; PCK: Clock connection pad; PGND: Ground connection pad; PI: Input connection pad; POE: Output enable connection pad; PQ: Output connection pad; PVDD: Power connection pad; PX1: Connection pad; PX2: Connection pad; RD1~RD3, RE1, RE2: Resistors; SD1~SD4: Edge; SF: Surface; TD1~TD3, TE1~TE5: Transistor; TM: Terminal; TCK, TGND, TOE, TVDD: External terminals; VB: Bias voltage; VCP: Temperature compensation voltage; VDD: Power supply voltage; VREF: Reference voltage; VT: Temperature detection voltage. Detailed Implementation

[0024] The embodiments will now be described. Furthermore, the embodiments described below do not unduly limit the scope of the claims. Also, not all structures described in these embodiments are necessarily essential structural elements.

[0025] 1. Wiring out of the connector plate

[0026] Figure 1 A cross-sectional view of the connection disk area of ​​the integrated circuit device 20 in this embodiment is shown. Figure 2 A top view of the connection pad area is shown. The integrated circuit device 20 of this embodiment includes a connection pad 2, lead-out wiring 5, and via group 6. (As shown...) Figure 2As shown, the connecting disk 2 is a connecting disk with a shape having both a long side and a short side. For example, when the connecting disk 2 is quadrilateral, it becomes a rectangle with both a long side and a short side. Furthermore, the shape of the connecting disk 2 is not limited to a rectangle; for example, it can be any shape that contains an ellipse or an oblong shape, such as a hexagon, an octagon, or other polygons with five or more sides, or a roughly elliptical shape. For example, the corners of the connecting disk 2 can be chamfered to reduce stress concentration at the corners. Additionally, the area of ​​the connecting disk 2 is the area of ​​the metal layer constituting the connecting disk 2 that is exposed on the active surface of the integrated circuit device 20. For example, in... Figure 1 In this structure, the connecting disk 2 is composed of an uppermost metal layer ALE, such as aluminum. Furthermore, the area of ​​the opening portion exposed from the oxide film, i.e., the passivation film 3, formed in a manner that covers the metal layer ALE, becomes the area of ​​the connecting disk 2.

[0027] Moreover, in Figure 1 , Figure 2 In the circuit, a circuit 8 is provided that overlaps with and is electrically connected to the connecting disk 2 when viewed from above. Circuit 8 is, for example, a functional circuit with a defined function. The circuit is, for example, composed of multiple circuit elements. These circuit elements are active components such as transistors or passive components such as resistors and capacitors. For example, in… Figure 1 In this circuit, circuit 8 includes an N-type transistor formed in a P-type well PWL and a P-type transistor formed in an N-type well NWL. Additionally, Figure 1 This diagram schematically illustrates the configuration relationship between the connecting disk 2 and the circuit 8. In reality, the layout area of ​​the transistors and other components in the circuit 8 is sufficiently small relative to the layout area of ​​the connecting disk 2, and the required number of transistors and other circuit elements constituting the circuit 8 are arranged below the connecting disk 2.

[0028] In addition, looking down is Figure 1 A top view in the direction DR, for example, a top view viewed from a direction perpendicular to the semiconductor substrate constituting the integrated circuit device 20. For example... Figure 2 As shown, the circuit 8 is arranged to overlap with the connector 2 when viewed from above. For example, when the direction DR toward the semiconductor substrate is set to downward, the circuit 8 is arranged below the connector 2. Furthermore, the connector 2 and the circuit 8 are electrically connected via lead-out wiring 5, via groups of vias 6, etc. In this way, by arranging the circuit 8 to overlap with the connector 2 when viewed from above, the layout area of ​​the integrated circuit device 20 can be reduced.

[0029] In addition, such as Figure 2 As shown, the lead-out wiring 5 is a wiring that extends from the outer edge EDL of the long side of the connecting disk 2 along the short side direction DS. For example, in Figure 2In this context, the outer edge EDL is the outer edge along the long side direction DL of the connecting disk 2, and the outer edge EDS is the outer edge along the short side direction DS of the connecting disk 2. When the connecting disk 2 is rectangular, the outer edge EDL on the long side is the long side of the connecting disk 2, and the long side direction DL is along the direction of the long side. Similarly, the outer edge EDS on the short side is the short side of the connecting disk 2, and the short side direction DS is along the direction of the short side. Furthermore, as... Figure 1 As shown, the lead-out wiring 5 is composed of a metal layer ALE of the same layer as the connecting plate 2. For example, the lead-out wiring 5 is a wiring that extends from the metal layer ALE of the connecting plate 2 along the short side direction DS of the connecting plate 2.

[0030] The via group 6 electrically connects the lead-out wiring 5 to the wiring 7 of the circuit 8. Furthermore, the via group 6 is arranged in a manner that does not overlap with the connecting pad 2 when viewed from above. For example, the via group 6, which electrically connects the lead-out wiring 5 and wiring 7, is not positioned below the connecting pad 2, but rather below the lead-out wiring 5 extending from the outer edge EDL of the connecting pad 2 along the short side direction DS. For example, in... Figure 1 , Figure 2 The integrated circuit device 20 has five metal layers ALA to ALE. The metal layers ALA to ALE are, for example, aluminum or an aluminum alloy. Furthermore, the number of metal layers is not limited to five; it can be four or less, or six or more. The via group 6 includes multiple vias connecting these metal layers. These vias, also known as via wiring, are formed by vias and metal plugs. For example, the via group 6 includes vias connecting metal layer ALE to metal layer ALD, vias connecting metal layer ALD to metal layer ALC, and vias connecting metal layer ALC to metal layer ALB, etc. These multiple vias are arranged below the lead-out wiring 5, for example, along direction DR. Through the via group 6 containing these multiple vias, the metal layer ALE constituting the lead-out wiring 5 is electrically connected to the metal layer ALB constituting the wiring 7. Moreover, one end of the wiring 7 is connected to a via in the via group 6, and the other end is electrically connected to the circuit 8. For example, the other end of the wiring 7 is connected to a circuit element constituting the circuit 8. For example, wiring 7 is electrically connected to the drain, source, or gate of a transistor (as a circuit element), or one end of a resistor or capacitor (as a passive element). Furthermore, in Figure 1 The diagram shows wiring 7 made of metal layer ALB, but wiring that electrically connects via group 6 to circuit 8 can also be made of other metal layers such as metal layer ALA, ALC, etc.

[0031] As described above, in this embodiment, the circuit 8 is arranged to overlap with the connecting plate 2 when viewed from above. This allows for efficient utilization of the area of ​​the connecting plate 2 to arrange the circuit 8, thus enabling a reduction in the area of ​​the integrated circuit device 20. Specifically, by arranging the circuit 8 within the area of ​​the connecting plate 2, compared to arranging the circuit 8 outside the area of ​​the connecting plate 2, the area of ​​the integrated circuit device 20 can be reduced by an amount corresponding to the area of ​​the circuit 8. Furthermore, since the connecting plate 2 has a shape with both a long side and a short side, even when a force is applied along the long side of the connecting plate 2 during the installation of the integrated circuit device 20, defects such as short circuits and broken wires can be suppressed. For example, in the case of ultrasonic bonding as described later during installation, by aligning the vibration direction of the ultrasonic waves with the long side of the connecting plate 2, short circuits caused by ultrasonic vibration can be suppressed. Moreover, in this embodiment, a lead wire 5 is led out from the outer edge EDL of the long side of the connecting plate 2 along the short side direction DS, and this lead wire 5 is electrically connected to the wiring 7 of the circuit 8 using the through-hole group 6. Thus, even when a force is applied along the long side of the connector pad 2 during the installation of the integrated circuit device 20, the risk of short circuits, broken wires, etc., caused by damage to the lead-out wiring 5 and the via group 6 can be suppressed. Therefore, an integrated circuit device 20 can be provided that can suppress damage to the lead-out wiring 5 and the via group 6 used to electrically connect the connector pad 2 and the circuit 8, with the circuit 8 arranged in a manner overlapping the connector pad 2. That is, the integrated circuit device 20 can be miniaturized by arranging the circuit 8 in a manner overlapping the connector pad 2, and appropriate lead-out wiring 5 for electrically connecting the connector pad 2 and the circuit 8 can be achieved. In addition, as a comparative example of this embodiment, a method of providing a via directly below the connector pad 2 and connecting the connector pad 2 and the circuit 8 via the via can also be considered. However, if a via is provided directly below the connector pad 2, problems such as peeling of the metal layer ALE of the connector pad 2 and damage to the via may occur. In this regard, in this embodiment, the via group 6 is provided in a position that does not overlap with the connector pad 2 when viewed from above, thus preventing such problems from occurring.

[0032] In addition, such as Figure 1 As shown, wiring 7 is a wiring on a metal layer ALB that is lower than the metal layer ALE of the connector 2. Wiring 7 partially overlaps with the connector 2 when viewed from above. By providing wiring 7 in this manner, the lead-out wiring 5 from the connector 2 is connected to one end of wiring 7 via via group 6, and the other end of wiring 7 is connected to circuit 8. This allows for electrical connection between the connector 2 and the circuit elements of circuit 8, which is configured to overlap with the connector 2. Therefore, by configuring circuit 8, which is electrically connected to the connector 2, to overlap with the connector 2 when viewed from above, the area of ​​the integrated circuit device 20 can be reduced.

[0033] In addition, Figure 1 In this configuration, wiring 7 is a wiring on a metal layer ALB that is spaced at least one level away from the metal layer ALE of the connector 2. For example, wiring 7 of circuit 8 is not formed by the metal layer ALD directly below the metal layer ALE of the connector 2, but rather by the metal layer ALB that is spaced at least one level away from the metal layer ALE of the connector 2. Furthermore, in... Figure 1 In this embodiment, wiring 7 is formed by metal layer ALB, but it can also be formed by metal layers ALC or ALA that are spaced one or more layers away from metal layer ALE of the connector 2. For example, if wiring 7 of circuit 8 is formed by metal layer ALD directly below metal layer ALE of connector 2, wiring 7 may be damaged during installation or when load is applied to connector 2, potentially resulting in defects such as wire breakage. In this regard, if wiring 7 of circuit 8 is formed by metal layers ALB, ALC, or ALA that are spaced one or more layers away from metal layer ALE of connector 2, defects caused by damage to wiring 7 can be prevented, and reliability can be improved. For example, in this embodiment, the lead-out wiring 5 from connector 2 is electrically connected to wiring 7 using multiple through holes of through-hole group 6. Therefore, wiring 7 of circuit 8 can be formed by metal layers ALB, ALC, or ALA that are spaced one or more layers away from metal layer ALE of connector 2.

[0034] In addition, such as Figure 2 As shown, the lead-out wiring 5 has a shape where the long side direction DL of the connecting plate 2 is the long side direction. For example, the lead-out wiring 5 has a shape where the long side direction DL of the connecting plate 2 is the long side direction and the short side direction DS of the connecting plate 2 is the short side direction. For example, in Figure 2 In the diagram, the long side direction DL of the connecting plate 2 is vertical in the plane of the paper, and the short side direction DS of the connecting plate 2 is horizontal in the plane of the paper, making the connecting plate 2 longer in the vertical direction than in the horizontal direction. Similarly, the lead-out wiring 5 is also longer in the vertical direction than in the horizontal direction. This allows a shorter horizontally oriented lead-out wiring 5 to be drawn from the outer edge EDL of the long side of the connecting plate 2, and connected to the wiring 7 of the circuit 8 via the via group 6. Furthermore, by extending the vertical length of the lead-out wiring 5, the number of vias provided in the area of ​​the lead-out wiring 5 can be increased, thereby improving electrostatic discharge resistance and reducing wiring impedance.

[0035] In addition, such as Figure 2 As shown, the through-hole group 6 has multiple through holes arranged along the long side of the lead-out wiring 5. For example, in Figure 2In this circuit, multiple rows of vias are arranged along the long side of the lead-out wiring 5; specifically, three rows of vias are provided. However, the number of rows in a via group is not limited to three; it can be one row or four or more. By arranging multiple vias in the via group 6 along the long side of the lead-out wiring 5, the number of via groups 6 used to electrically connect the lead-out wiring 5 to the wiring 7 of the circuit 8 can be increased. This improves electrostatic discharge resistance and reduces wiring impedance, thereby enhancing the reliability of the integrated circuit device 20.

[0036] In addition, such as Figure 2 As shown in A1 and A2, the lead-out wiring 5 has a chamfered corner shape when viewed from above. For example, as shown in A1 and A2, the lead-out wiring 5, by chamfering the corners, becomes... Figure 2 It is roughly rectangular in shape on the paper, with the longitudinal direction as the longer side and the transverse direction as the shorter side. Figure 2 In the diagram, the upper right corner shown in A1 and the lower right corner shown in A2 are chamfered. By making the corners of the lead-out wiring 5 chamfered in this way, for example, when static electricity is applied to the connection pad 2, it is possible to suppress the accumulation of charge at the corners, which could cause damage due to overheating. As a result, the reliability of the integrated circuit device 20 can be improved.

[0037] In addition, for example Figure 3 As shown, the connector 2 in this embodiment is an input connector PI that receives input signals. The circuit 8, arranged to overlap with the input connector PI when viewed from above, is an I / O circuit 22 that receives input signals from the input connector PI. The I / O circuit 22 includes an input buffer circuit that receives and buffers the input signals, and a circuit that outputs the buffered input signals to the integrated circuit device 20. Thus, the input signals received from the input connector PI can be input to the I / O circuit 22 via the lead-out wiring 5, the via group 6, and the wiring 7. Furthermore, the input connector PI has a shape having both a long side direction and a short side direction, and the lead-out wiring 5 extends from the outer edge EDL of the long side of the input connector PI. Therefore, even when forces act along the long side direction of the input connector PI, such as when mounting the integrated circuit device 20, it is possible to suppress short circuits and other defects, or damage to the lead-out wiring 5 and the via group 6. Furthermore, since the area of ​​the input connection pad PI can be effectively utilized to configure the I / O circuit 22, the integrated circuit device 20 can be made smaller compared to the case where the I / O circuit 22 is configured outside the area of ​​the input connection pad PI. Additionally, Figure 3 In the circuit, an electrostatic discharge protection circuit 21 or a power stabilizing capacitor is also provided, which overlaps with the input connection pad PI when viewed from above. This allows for further miniaturization of the integrated circuit device 20, which effectively utilizes the area of ​​the input connection pad PI.

[0038] In addition, for example Figure 4 As shown, the connection disk 2 in this embodiment is the output connection disk PQ that outputs the output signal. Furthermore, the circuit 8, arranged to overlap with the output connection disk PQ when viewed from above, is an output buffer circuit 52 that outputs the output signal to the output connection disk PQ. The output buffer circuit 52, for example, buffers the output signal from the internal circuitry of the integrated circuit device 20 and outputs it to the output connection disk PQ. In this way, the output signal from the output buffer circuit 52 can be output from the output connection disk PQ via wiring 7, via group 6, and lead-out wiring 5. Moreover, the output connection disk PQ has a shape having both a long side direction and a short side direction, and the lead-out wiring 5 is led out from the outer edge EDL of the long side of the output connection disk PQ. Therefore, even when forces act along the long side direction of the output connection disk PQ, such as during the installation of the integrated circuit device 20, it is possible to suppress defects such as short circuits or damage to the lead-out wiring 5 and via group 6. In addition, since the output buffer circuit 52 can be configured in an area of ​​the output connection disk PQ effectively, the integrated circuit device 20 can be miniaturized. Furthermore, when the output buffer circuit 52 outputs an output signal such as a high-frequency clock signal, the output buffer circuit 52 becomes a noise source. Regarding this, in Figure 4 In this configuration, since the output connection pad PQ is arranged to cover the output buffer circuit 52, which is a noise source, the metal layer of the output connection pad PQ becomes a shielding layer, which can suppress the noise source from affecting other circuits of the integrated circuit device 20. Therefore, it is also possible to suppress the performance degradation of the integrated circuit device 20 due to noise from the output buffer circuit 52.

[0039] In addition, for example Figure 5 As shown, the connection pad 2 in this embodiment is a ground connection pad PGND. Furthermore, the circuit 8, arranged to overlap with the ground connection pad PGND when viewed from above, is a reference voltage generation circuit 62 that generates a reference voltage. The reference voltage generation circuit 62 generates, for example, a reference voltage that remains constant even when the power supply voltage or temperature changes. For example, the reference voltage generation circuit 62 generates a reference voltage used to generate at least one of a bias current, a bias voltage, or a regulated power supply voltage. For example, the integrated circuit device 20 has an analog circuit, and the reference voltage generation circuit 62 generates a reference voltage used to generate the bias current or bias voltage of the analog circuit. Furthermore, the integrated circuit device 20 has a regulator that, based on the reference voltage generated by the reference voltage generation circuit 62, generates a regulated power supply voltage that is a constant voltage obtained by stepping down the power supply voltage, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20. If using... Figure 5Such a layout allows the ground voltage supplied to the ground pad PGND to be supplied to the reference voltage generation circuit 62 via the lead-out wiring 5, via group 6, and wiring 7. Furthermore, the ground pad PGND has a shape with both a long side and a short side, and the lead-out wiring 5 is led out from the outer edge EDL of the long side of the ground pad PGND. Therefore, even when a force is applied along the long side of the ground pad PGND, short circuits in the wiring and damage to the lead-out wiring 5 can be suppressed. In addition, since the reference voltage generation circuit 62 can be configured using the area of ​​the ground pad PGND effectively, the integrated circuit device 20 can be miniaturized. Furthermore, in Figure 5 In this circuit, the ground connection pad PGND is configured to cover the reference voltage generation circuit 62. Therefore, the metal layer of the ground connection pad PGND acts as a shielding layer, which can suppress noise from other circuits in the integrated circuit device 20 from being superimposed on the reference voltage generated by the reference voltage generation circuit 62. Thus, the reference voltage generation circuit 62 can generate a low-noise reference voltage and also suppress the performance degradation of the integrated circuit device 20 caused by noise superimposed on the reference voltage.

[0040] In addition, Figure 6 In the integrated circuit device 20, in addition to the lead-out wiring 5 extending from the outer edge EDL of the long side of the connector 2 along the short side direction DS, it also includes a second lead-out wiring 9 extending from the outer edge EDS of the short side of the connector 2 along the long side direction DL. Furthermore, the second lead-out wiring 9 is made of a metal layer ALE of the same layer as the connector 2. For example, in a power connector that is supplied with a power supply voltage, sometimes the power supply voltage supplied to the power connector is supplied to each circuit of the integrated circuit device 20 through multiple lead-out wirings. In such a power connector, etc., as... Figure 6 As shown, a second lead wire 9 can also be provided, extending from the outer edge EDS of the short side of the connector 2. This is because, in this case, the lead wire 5 and the second lead wire 9 supply power voltages of the same potential to each circuit of the integrated circuit device 20, and therefore, it is believed that even if a force or the like is applied along the long side of the connector, the possibility of adverse conditions is relatively small.

[0041] Next, the defects caused by ultrasonic bonding during the installation of integrated circuit device 20 will be explained. Figure 7 In this embodiment, a bump BMP is formed on the connector pad 2 of the integrated circuit device 20. This bump BMP is, for example, called a stud bump, and is used, for example, in flip-chip mounting of the integrated circuit device 20. In the stud bump, a ball is formed at the end of a wire such as a gold wire. After pressing the ball onto the upper surface of the connector pad 2 using heat or ultrasonic vibration, the wire is cut. Thus, as... Figure 7As shown, gold bumps or other bumps (BMPs) can be formed near the center of the connector pad 2. Then, the integrated circuit device 20 with the BMPs formed on the connector pad 2 is described later. Figure 14 As shown, it is flip-mounted onto the mounting surface SF of the package 15. Specifically, the integrated circuit device 20 is configured such that the other end of the bump BMP contacts the terminal TM formed on the surface SF of the package 15, and the terminal TM, formed of gold or the like, is bonded to the other end of the bump BMP by ultrasonic vibration.

[0042] However, if ultrasonic bonding using such ultrasonic vibrations is performed, then as Figure 8 As shown, sometimes the following situation occurs: the protrusion BMP formed on the connecting disk 2 extends out of the area of ​​the connecting disk 2 in the direction of ultrasonic vibration. When this happens, Figure 8 At point B1, the overflowing bump BMP and Figure 1 When the passivation film 3 comes into contact with the metal contact pad 2, which is softer than the passivation film 3, it produces cracks. While the force generated by ultrasonic vibration is applied to the metal contact pad 2, which is softer than the passivation film 3, the force will cause cracks. Furthermore, the metal of the contact pad 2 can come into contact with other wiring through the cracks, leading to short circuits and other defects. To prevent such defects from occurring, in this embodiment, as... Figure 8 As shown in B2, the connecting plate 2 is shaped such that the direction of ultrasonic vibration is along its long side. Specifically, the connecting plate 2 is shaped like a rectangle, for example, with the direction of ultrasonic vibration along its long side. In this way, even if the shape of the bump BMP becomes elliptical when viewed from above due to ultrasonic vibration, the protrusion of the bump BMP from the connecting plate 2 can be suppressed, and defects such as short circuits in the wiring caused by cracks as described above can be prevented.

[0043] On the other hand, in the method of arranging the circuit 8 in a manner that overlaps with the connecting plate 2, lead-out wiring 5 and through-hole group 6 are required for electrically connecting the connecting plate 2 and the circuit 8. However, if the lead-out wiring 5 from the connecting plate 2 is led out from the outer edge EDS of the short side of the connecting plate 2, stress is applied to the lead-out wiring 5 and through-hole group 6 due to ultrasonic vibration, which may cause defects such as short circuits and broken wires. Therefore, in this embodiment, the following method is adopted: the connecting plate 2 is configured to have a shape with a long side direction and a short side direction, and the lead-out wiring 5 is led out from the outer edge EDL of the long side of the connecting plate 2, and the lead-out wiring 5 is electrically connected to the wiring 7 of the circuit 8 using through-hole group 6. In this way, even if the long side direction of the connecting plate 2 is the vibration direction of ultrasonic vibration, stress caused by the ultrasonic vibration can be prevented from being applied to the lead-out wiring 5 and through-hole group 6, thereby preventing defects such as short circuits and broken wires.

[0044] As mentioned above, in Figure 7 , Figure 8 In this configuration, the connecting plate 2 becomes a connecting plate electrically connected to an external terminal via a bump BMP. Furthermore, the bump BMP and the terminal are ultrasonically bonded. Moreover, the long side direction DL of the connecting plate 2 is aligned with the direction of ultrasonic vibration during ultrasonic bonding. In other words, the long side direction DL of the connecting plate 2 is the long side direction of the bump BMP. This allows for the suppression of... Figure 8 As shown, the BMP protrusions extend beyond the area of ​​the connector 2, which can cause short circuits and other defects. In addition, the lead-out wiring 5 extends from the outer edge EDL of the long side of the connector 2, thus suppressing the stress caused by the ultrasonic vibration of the ultrasonic bonding process on the lead-out wiring 5 and the through-hole group 6, and preventing short circuits, wire breaks, and other defects.

[0045] Furthermore, the above description illustrates an example of a short circuit or other adverse condition caused by ultrasonic vibration in the cylindrical bump, but this embodiment is not limited to this. For example, ultrasonic vibration is also used in wire bonding. In this case, it is also effective to set the long side direction DL of the connector 2 to the direction of ultrasonic vibration and to lead the lead wire 5 out from the outer edge EDL of the long side of the connector 2. In addition, the bump BMP can be a bump other than a cylindrical bump. When stress is applied along a predetermined direction by a method other than ultrasonic bonding, it is also effective to set the long side direction of the connector 2 to the predetermined direction and to lead the lead wire 5 out from the outer edge EDL of the long side of the connector 2. Furthermore, the phenomenon of the bump BMP protruding from the area of ​​the connector 2 may also be caused by forming the bump BMP on the connector 2 using ultrasonic bonding.

[0046] Furthermore, the construction of the connecting disk 2 is not limited to Figure 1 The structure shown can be implemented in various ways. Figure 9 This is a cross-sectional view showing another construction example of connecting disk 2. Figure 9In this design, conductive layers 92, 93, and 94, formed for example by electroplating, are formed on the metal 91 of the connecting pad. Conductive layer 92 is formed of a material with good adhesion to the metal 91 of the connecting pad, which is made of aluminum or an aluminum alloy, such as nickel or a nickel alloy. Conductive layer 92 has a thickness of, for example, 2 μm to 10 μm. By increasing the thickness of conductive layer 92 in this way, even when a large load is applied when attaching bumps or bonding wires to the connecting pad 2, the load is less likely to be transmitted to the underside of the connecting pad 2. Therefore, it is possible to prevent malfunctions in the circuit 8 located below the connecting pad 2 due to the increased weight during the attachment of bumps or bonding wires. Conductive layer 93 is located between conductive layer 92 and conductive layer 94, improving the adhesion between conductive layers 92 and 94, and functions as a barrier layer to prevent diffusion of conductive layer 92 into conductive layer 94. Conductive layer 93 is formed of a material with good adhesion to both conductive layers 92 and 94, such as palladium or a palladium alloy. Furthermore, the conductive layer 93 can be provided as needed, and can be omitted, for example, if the conductive layer 92 and conductive layer 94 have good adhesion. The conductive layer 94 functions as a connection layer with the bump or bonding wire. The conductive layer 94 is formed of a material with low contact resistance to the bump or bonding wire, such as gold or a gold alloy. By using... Figure 9 The connection plate 2 with such a structure provides added weight during installation when the bump or bonding wire is attached to the connection plate 2, which can protect the circuit 8 under the connection plate, and can attach the bump or bonding wire with lower contact resistance, thereby simplifying installation and improving reliability.

[0047] 2. Integrated circuit device

[0048] Next, a specific example of the integrated circuit device 20 of this embodiment will be described. Figure 10 This diagram illustrates a structural example of the integrated circuit device 20 according to this embodiment. Furthermore, the integrated circuit device 20 is not limited to... Figure 10 The structure can be modified in various ways, such as omitting some of its structural elements or adding other structural elements. Furthermore, the following description primarily uses the case of an oscillator 4 in this embodiment, which is equipped with an integrated circuit device 20, as an example; however, the device in this embodiment is not limited to the oscillator 4.

[0049] Figure 10The integrated circuit device 20 includes an oscillation circuit 30. Furthermore, the integrated circuit device 20 may include an output circuit 50, a power supply circuit 60, a logic circuit 70, a temperature compensation circuit 80, a temperature sensor circuit 90, a power connection pad PVDD, a ground connection pad PGND, a clock connection pad PCK, an output enable connection pad POE, and connection pads PX1 and PX2 for connecting the oscillator. Additionally, as an example of the device in this embodiment, the oscillator 4 includes an oscillator 10 and the integrated circuit device 20. The oscillator 10 is electrically connected to the integrated circuit device 20. For example, the oscillator 10 and the integrated circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps in a package that houses the oscillator 10 and the integrated circuit device 20.

[0050] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented, for example, using a quartz resonator or similar vibrating plate. For instance, the oscillator 10 can be implemented using a quartz resonator with a shearing angle of AT or SC, a tuning fork type quartz resonator, or a double tuning fork type quartz resonator. For example, the oscillator 10 can be an oscillator built into a temperature-compensated quartz oscillator (TCXO) without a thermostatic bath, or an oscillator built into a thermostatically controlled quartz oscillator (OCXO) with a thermostatic bath. Alternatively, the oscillator 10 can be an oscillator built into an SPXO (Simple Packaged Crystal Oscillator). Furthermore, the oscillator 10 of this embodiment can also be implemented using various vibrating plates, such as those other than shearing type, tuning fork type, or double tuning fork type, or piezoelectric resonators made of materials other than quartz. For example, as the oscillator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro ElectroMechanical Systems) oscillator formed using a silicon substrate as a silicon oscillator can also be used.

[0051] Integrated circuit device 20, for example, is an IC (Integrated Circuit) manufactured by semiconductor process, which is a semiconductor chip on a semiconductor substrate on which circuit elements are formed.

[0052] The oscillation circuit 30 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 30 is electrically connected to the connecting disks PX1 and PX2, and generates an oscillation signal OSC by causing the oscillator 10 to oscillate. Connecting disk PX1 is a connecting disk for connecting the first oscillator, and connecting disk PX2 is a connecting disk for connecting the second oscillator. For example, the oscillation circuit 30 can be implemented using an oscillation drive circuit and active components such as capacitors or resistors provided between connecting disks PX1 and PX2. The drive circuit can be implemented, for example, using a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 30, and the drive circuit drives the oscillator 10 with voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 30, various types of oscillation circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used, for example. In addition, a variable capacitor circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitor circuit. The variable capacitor circuit can be implemented, for example, using a variable capacitor element such as a varactor diode. For example, a variable capacitor circuit can be implemented using a variable capacitor element that controls the capacitor based on a temperature-compensated voltage. Alternatively, a variable capacitor circuit can be implemented using a capacitor array and a switch array connected to the capacitor array. Furthermore, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals and transmitting information via electrical signals. An electrical connection can also be a connection via passive components, etc.

[0053] Output circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC. Output circuit 50 includes an output buffer circuit 52. The output buffer circuit 52 outputs the buffered signal of the oscillation signal OSC as the clock signal CKQ to the clock connection disk PCK. Furthermore, this clock signal CKQ is output to the outside via the external terminal TCK of the oscillator 4. For example, output circuit 50 outputs the clock signal CKQ in the form of a single-ended CMOS signal. Alternatively, output circuit 50 can also output the clock signal CKQ in a signal form other than CMOS. For example, output circuit 50 can also output a differential clock signal to the outside in the form of LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS) signals.

[0054] The power supply circuit 60 is supplied with a power supply voltage VDD from the power connector PVDD and a ground voltage from the ground connector PGND, supplying various power supply voltages for the internal circuits of the integrated circuit device 20. For example, the power supply circuit 60 supplies an regulated power supply voltage based on the power supply voltage VDD to the oscillation circuit 30, etc. Furthermore, the power supply circuit 60 includes a reference voltage generation circuit 62 and a regulator 64. The reference voltage generation circuit 62 generates and outputs a reference voltage. The reference voltage generation circuit 62 can be implemented, for example, using a bandgap reference circuit, a circuit using the difference in the work function of the gate, or a circuit utilizing the difference in threshold voltage caused by changes in the channel impurity concentration, etc. The regulator 64 is supplied with the power supply voltage VDD, thereby generating various regulated power supply voltages. For example, the regulator 64 generates a constant voltage regulated power supply voltage obtained by stepping down the power supply voltage VDD based on the reference voltage generated by the reference voltage generation circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20.

[0055] Logic circuit 70 is a control circuit that performs various control processes. For example, logic circuit 70 performs overall control of integrated circuit device 20, or controls the sequence of actions of integrated circuit device 20. For example, logic circuit 70 controls individual circuit blocks of integrated circuit device 20, such as oscillation circuit 30, output circuit 50, power supply circuit 60, or temperature compensation circuit 80. Logic circuit 70 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing, such as a gate array.

[0056] The temperature compensation circuit 80 performs temperature compensation for the oscillation signal OSC of the oscillation circuit 30. Temperature compensation of the OSC is temperature compensation for the oscillation frequency of the oscillation circuit 30. Specifically, the temperature compensation circuit 80 performs temperature compensation based on temperature detection information from the temperature sensor circuit 90. For example, the temperature compensation circuit 80 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor circuit 90 and outputs the generated temperature compensation voltage VCP to the oscillation circuit 30, thereby performing temperature compensation for the oscillation signal OSC of the oscillation circuit 30. For example, the temperature compensation circuit 80 outputs a temperature compensation voltage VCP as the capacitor control voltage of the variable capacitor circuit in the oscillation circuit 30 to perform temperature compensation. In this case, the variable capacitor circuit of the oscillation circuit 30 is implemented using a variable capacitor element such as a varactor diode. Temperature compensation is a process that suppresses and compensates for changes in the oscillation frequency caused by temperature variations. For example, the temperature compensation circuit 80 performs temperature compensation using an analog method based on polynomial approximation. For example, when the temperature compensation voltage for compensating the frequency-temperature characteristics of the oscillator 10 is approximated by a polynomial, the temperature compensation circuit 80 performs analog temperature compensation based on the coefficient information of the polynomial. Alternatively, the temperature compensation circuit 80 can also perform digital temperature compensation.

[0057] The temperature sensor circuit 90 is a sensor circuit for detecting temperature. Specifically, the temperature sensor circuit 90 outputs a temperature-dependent voltage, which varies according to the ambient temperature, as a temperature detection voltage VT. For example, the temperature sensor circuit 90 uses a temperature-dependent circuit element to generate the temperature detection voltage VT. Specifically, the temperature sensor circuit 90 outputs a temperature detection voltage VT whose voltage value varies with temperature by utilizing the temperature dependence of the forward voltage of a PN junction. The forward voltage of the PN junction can be, for example, the base-emitter voltage of a bipolar transistor. Furthermore, in the case of digital temperature compensation processing, the temperature sensor circuit 90 measures the ambient temperature and other temperatures, and outputs the result as temperature detection data.

[0058] In addition, the integrated circuit device 20 includes a power connection pad PVDD, a ground connection pad PGND, a clock connection pad PCK, an output enable connection pad POE, and connection pads PX1 and PX2 for oscillator connection. These connection pads are, for example, terminals of the integrated circuit device 20, which is a semiconductor chip.

[0059] The power supply terminal PVDD is the terminal supplied with the power supply voltage VDD. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply terminal PVDD. The ground terminal PGND is the terminal supplied with the ground voltage GND. GND can also be called VSS, and the ground voltage is, for example, the ground potential. In this embodiment, ground is appropriately referred to as GND. The clock terminal PCK is the terminal that outputs the clock signal CKQ. For example, the clock signal CKQ based on the oscillation signal OSC in the oscillation circuit 30 is output from the clock terminal PCK to the outside. The output enable terminal POE is the terminal used to control the output enable of the clock signal CKQ. Specifically, the output enable of the clock signal CKQ is controlled according to the output enable signal OE input via the output enable terminal POE. For example, the logic circuit 70 receives the output enable signal OE from the output enable terminal POE and controls the output enable of the clock signal CKQ in the output circuit 50.

[0060] The power connector PVDD, ground connector PGND, clock connector PCK, and output enable connector POE are electrically connected to the external terminals TVDD, TGND, TCK, and TOE of the oscillator 4, respectively. This electrical connection can be achieved using, for example, internal wiring of the package, bonding wires, or metal bumps. Furthermore, the external terminals TVDD, TGND, TCK, and TOE of the oscillator 4 are electrically connected to external devices. Additionally, connectors PX1 and PX2 are used for connecting the oscillator 10. For example, connector PX1 is electrically connected to one end of the oscillator 10, and connector PX2 is electrically connected to the other end of the oscillator 10. This electrical connection can be achieved using, for example, internal wiring of the package housing the oscillator 10 and the integrated circuit device 20, bonding wires, or metal bumps, connecting the oscillator 10 to the integrated circuit device 20 via connectors PX1 and PX2.

[0061] Figure 11 An example of the structure of the reference voltage generation circuit 62 is shown. Figure 11The reference voltage generation circuit 62 includes an N-type transistor TD1, resistors RD1, RD2, and RD3, and bipolar transistors BP1 and BP2 disposed between the VDD node and the GND node. Furthermore, the reference voltage generation circuit 62 includes P-type transistors TD2 and TD3 whose gates are biased by an input voltage VB; and a bipolar transistor BP3 disposed between the drain node of transistor TD2 and the GND node. The reference voltage generation circuit 62 is a bandgap reference circuit that generates and outputs a reference voltage VREF based on the bandgap voltage. For example, the base-emitter voltages of the PNP bipolar transistors BP1 and BP2 are set to VBE1 and VBE2, respectively, and ΔVBE = VBE1 ~ VBE2. The reference voltage generation circuit 62 outputs, for example, a reference voltage VREF = K × ΔVBE + VBE2. K is set by the resistance values ​​of resistors RD1 and RD2. For example, VBE2 has a negative temperature characteristic, while ΔVBE has a positive temperature characteristic. Therefore, by adjusting the resistance values ​​of resistors RD1 and RD2, a constant reference voltage VREF that is not temperature-dependent can be generated. Then, the generated reference voltage VREF becomes a constant voltage based on ground voltage.

[0062] Figure 12 This shows another structural example of the reference voltage generation circuit 62. Figure 12 The reference voltage generation circuit 62 is also a bandgap reference circuit, and includes N-type transistors TE1 and TE2, P-type transistors TE3, TE4, and TE5, resistors RE1 and RE2, and diodes DI1, DI2, and DI3 with PN junctions. N-type transistors TE1 and TE2 form a current mirror circuit, and P-type transistors TE3, TE4, and TE5 also form a current mirror circuit, so the current flowing through these transistors is approximately equal. Furthermore, the source voltages of N-type transistors TE1 and TE2 are also approximately equal. In addition, the number of parallel connections of the PN junctions in diode DI2 is set to M times the number of parallel connections of the PN junctions in diode DI1. Therefore, if the saturation current of diode DI1 is set to Is, the saturation current of diode DI2 becomes M × Is. Here, when the current flowing through transistors TE3, TE4, and TE5 is set to I, the voltages across diodes DI1, DI2, and DI3 are set to Vd1, Vd2, and Vd3 respectively, and the resistance values ​​of resistors RE1 and RE2 are set to R1 and R2, the reference voltage VREF generated by the reference voltage generation circuit 62 is as shown in equation (1).

[0063] VREF=I·R2+Vd3=(R2 / R1)·(kT / q)·In(M)+Vd3(1)

[0064] Here, k is Boltzmann's constant, T is the absolute temperature, and q is the charge of the electron. If we differentiate equation (1) with respect to the absolute temperature T, we get equation (2).

[0065] dVREF / dT=(R2 / R1)·(k / q)·In(M)+Vd3 / dT(2)

[0066] In equation (2) above, the term Vd3 / dT has a negative temperature characteristic. By correspondingly adjusting the value of (R2 / R1)·(k / q)·In(M) to a positive value, the value of equation (2) above can be made zero, thus generating a reference voltage VREF that eliminates temperature dependence. Furthermore, the reference voltage generation circuit 62 is not limited to... Figure 11 , Figure 12 The structure includes various circuits, such as those that can generate a reference voltage VREF using the work function difference voltage of transistors.

[0067] The above description illustrates a structural example of an integrated circuit device 20 assembled within an oscillator 4, but this embodiment is not limited to this. For example, the device in this embodiment could also be a sensor device such as a gyroscope sensor or an accelerometer, a display device that displays images on a display panel, a communication device that communicates using a specified communication standard, a drive device that drives a specified mechanism for a printer, or a power supply device that supplies or controls power. Furthermore, the integrated circuit device 20 in this embodiment is not limited to being assembled within the oscillator 4; it could also be an IC (Integrated Circuit) assembled within the aforementioned sensor device, display device, communication device, or power supply device. For example, if the device is a gyroscope sensor, the integrated circuit device 20 could include a drive circuit that drives the oscillator of the gyroscope sensor, a detection circuit that detects sensor signals from the oscillator, etc. If the device is an accelerometer sensor, the integrated circuit device 20 could include a drive circuit or a detection circuit for an acceleration sensor element implemented using MEMS (Micro Electro Mechanical Systems). When the sensor is a display device, the integrated circuit device 20 can include a driving circuit for the display panel or logic circuits for processing display data. When the sensor is a communication device, the integrated circuit device 20 can include physical layer circuits, link layer circuits, and logic circuits for communication. Thus, various circuit structures can be adopted as the integrated circuit device 20.

[0068] 3. Layout Configuration

[0069] Figure 13 express Figure 10An example layout configuration of an integrated circuit device 20. The outer shape of the integrated circuit device 20 includes edge SD1 and edge SD2 opposite to edge SD1. Edge SD1 is the first edge, edge SD2 is the second edge, and edge SD2 is the opposite edge of edge SD1. In addition, the outer shape of the integrated circuit device 20 includes edge SD1 and edges SD3 and SD4 intersecting edge SD2. Edge SD3 is the third edge, edge SD4 is the fourth edge, and edge SD4 is the opposite edge of edge SD3. The outer shape of the integrated circuit device 20 is, for example, the shape of a rectangular semiconductor chip. For example, edges SD1, SD2, SD3, and SD4 are edges of the substrate of the semiconductor chip. The semiconductor chip is also called a silicon chip. Here, let the direction from edge SD1 to edge SD2 be DR1, and let the direction from edge SD3 to edge SD4 be DR2. In addition, let the opposite direction of direction DR1 be direction DR3, and let the opposite direction of direction DR2 be direction DR4. Directions DR1, DR2, DR3, and DR4 are the first, second, third, and fourth directions, respectively.

[0070] like Figure 13 As shown, the integrated circuit device 20 includes a ground connection pad PGND, a power connection pad PVDD, a clock connection pad PCK, and an output enable connection pad POE. The power connection pad PVDD and the clock connection pad PCK are arranged along edge SD1. The clock connection pad PCK is, for example, located at the first corner where edge SD1 intersects with edge SD4. The output enable connection pad POE and the ground connection pad PGND are arranged along edge SD2. The ground connection pad PGND is, for example, located at the second corner where edge SD2 intersects with edge SD4. Additionally, the temperature sensor circuit 90 is, for example, located at the third corner where edge SD2 intersects with edge SD3. Alternatively, the temperature sensor circuit 90 may be configured to overlap with the output enable connection pad POE when viewed from above.

[0071] Here, output enabling connection disk POE is equivalent to Figure 3 The input connection disk PI and the clock connection disk PCK are equivalent to Figure 4 The output connection disk PQ. Additionally, the ground connection disk PGND is... Figure 5 The ground connection pad PGND. Furthermore, the output enable connection pad POE, clock connection pad PCK, ground connection pad PGND, and power connection pad PVDD configured in the integrated circuit device 20 are as follows: Figure 1 As explained in the previous section, the connecting pads are shaped with a long side and a short side, specifically, rectangular connecting pads. For example, these connecting pads have direction DR1 as the long side and direction DR2 as the short side. That is, the integrated circuit device 20 includes a plurality of connecting pads with direction DR1 as the long side and direction DR2 as the short side. Furthermore, direction DR1 becomes, for example, in... Figure 8The vibration direction of the ultrasonic wave is described in the diagram. In other words, the integrated circuit device 20 includes a connecting plate and a second connecting plate as a plurality of connecting plates, the connecting plate and the second connecting plate having shapes with long side direction and short side direction, respectively. Moreover, the long side direction of the connecting plate and the long side direction of the second connecting plate are the same direction DR1, and direction DR1 is the vibration direction of the ultrasonic wave.

[0072] Furthermore, the integrated circuit device 20 includes connection pads PX1 and PX2 for connecting the oscillator. These connection pads PX1 and PX2 are arranged along edge SD3. For example, an oscillation circuit 30 is arranged along edge SD3, and the connection pads PX1 and PX2 are arranged in the region of the oscillation circuit 30. Additionally, an output circuit 50 is arranged along edge SD1, and a power supply circuit 60 is arranged along edge SD4. Moreover, a logic circuit 70 is arranged between the oscillation circuit 30 and the power supply circuit 60. Furthermore, a temperature compensation circuit 80 is arranged between the oscillation circuit 30 and the output circuit 50, and the logic circuit 70 is arranged between the temperature compensation circuit 80 and edge SD2.

[0073] Moreover, in Figure 13 In the center, a reference voltage generation circuit 62 is configured to overlap with the ground connection disk PGND when viewed from above. That is, as Figure 5 As explained, a reference voltage generation circuit 62 is positioned below the ground connection pad PGND. This shielding effect of the ground connection pad PGND suppresses high-frequency noise transmission to the reference voltage generation circuit 62, preventing potential fluctuations in the reference voltage generated by the reference voltage generation circuit 62 that could lead to a decrease in clock frequency accuracy. Furthermore, since the reference voltage generation circuit 62 can be configured within the designated area of ​​the ground connection pad PGND, a smaller area of ​​the integrated circuit device 20 can be achieved. Additionally, circuits in the power supply circuit 60 other than the reference voltage generation circuit 62 do not overlap with the ground connection pad PGND when viewed from above; for example, they are configured along edge SD4.

[0074] In addition, Figure 13 In the center, an output buffer circuit 52 is configured to overlap with the clock connection disk PCK when viewed from above. That is, as in Figure 4 As described above, an output buffer circuit 52 is arranged below the clock connection disk PCK. Furthermore, the circuitry in the output circuitry 50 other than the output buffer circuit 52 does not overlap with the clock connection disk PCK when viewed from above, for example, it is arranged along edge SD1.

[0075] By configuring the clock connection disk PCK and the output buffer circuit 52 to overlap when viewed from above, the clock signal CKQ from the output buffer circuit 52 can be output to the clock connection disk PCK via a shortest clock routing path from the output buffer circuit 52 towards the clock connection disk PCK positioned directly above it. This minimizes the impedance of the clock routing and suppresses potential fluctuations caused by this impedance. The output buffer circuit 52 has a high driving capability because it needs to drive a large external load. Therefore, if the impedance of the clock routing is high, its potential fluctuations also increase, degrading the signal quality of the clock signal CKQ. In this regard, by configuring the clock connection disk PCK and the output buffer circuit 52 to overlap when viewed from above, the clock routing path connecting the output buffer circuit 52 and the clock connection disk PCK can be made a shortest path, thereby minimizing the impedance of the clock routing and suppressing the degradation of the signal quality of the clock signal CKQ. Furthermore, the output buffer circuit 52, due to its high driving capability to drive external loads, generates significant high-frequency noise. The output buffer circuit 52 and the clock connection disk PCK of the output clock signal CKQ become sources of high-frequency noise. To address this, if the clock connection disk PCK overlaps with the output buffer circuit 52 when viewed from above, these high-frequency noise sources can be concentrated in one location. This allows for easy implementation of layout configurations and other measures to mitigate the adverse effects of noise from these high-frequency noise sources.

[0076] In addition, such as Figure 13As shown, the integrated circuit device 20 includes side SD1 and side SD2 opposite to side SD1. An output buffer circuit 52 and a clock connection disk PCK are disposed on side SD1, and a reference voltage generation circuit 62 and a ground connection disk PGND are disposed on side SD2. Side SD1 is the first side, and side SD2 is the second side. For example, the output buffer circuit 52 and the clock connection disk PCK are disposed closer to side SD1 than side SD2. Similarly, the reference voltage generation circuit 62 and the ground connection disk PGND are disposed closer to side SD2 than side SD1. For example, the output buffer circuit 52 and the clock connection disk PCK are disposed in a first region between side SD1 and the center line of sides SD1 and SD2, and the reference voltage generation circuit 62 and the ground connection disk PGND are disposed in a second region between side SD2 and the center line of sides SD1 and SD2. Thus, the output buffer circuit 52 and clock connection disk PCK, which are sources of high-frequency noise, are configured on the SD1 side, while the reference voltage generation circuit 62 and ground connection disk PGND, which need to avoid high-frequency noise, are configured on the SD2 side. This allows for separation between the output buffer circuit 52 and clock connection disk PCK, which are sources of high-frequency noise, and the reference voltage generation circuit 62 and ground connection disk PGND. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 52 and clock connection disk PCK to the reference voltage generation circuit 62 and ground connection disk PGND, preventing clock frequency accuracy degradation caused by high-frequency noise.

[0077] Furthermore, the integrated circuit device 20 includes a third side SD3, which intersects with sides SD1 and SD2, and an oscillation circuit 30 is disposed on the side of side SD3. For example, the oscillation circuit 30 is disposed along side SD3. Specifically, the oscillation circuit 30 is disposed such that, for example, its long side is along side SD3. By distributing the oscillation circuit 30 on the side of side SD3, the distance between the output buffer circuit 52 and the oscillation circuit 30 disposed on the side of side SD1 can be separated, preventing high-frequency noise from the output buffer circuit 52 from being superimposed on the oscillation signal OSC and thus degrading the oscillation characteristics. In addition, by distributing the oscillation circuit 30 on the side of side SD3, the distance between the reference voltage generation circuit 62 and the oscillation circuit 30 disposed on the side of side SD2 can be separated, preventing oscillation noise from the oscillation circuit 30 from being superimposed on the reference voltage of the reference voltage generation circuit 62 and thus preventing a decrease in clock frequency accuracy.

[0078] Furthermore, the integrated circuit device 20 includes a temperature compensation circuit 80 that performs temperature compensation for the oscillation frequency of the oscillation signal OSC. And, as... Figure 13As shown, the temperature compensation circuit 80 is disposed between the oscillation circuit 30 and the clock connection disk PCK. For example, the temperature compensation circuit 80 is disposed on the DR2 side of the oscillation circuit 30, and the clock connection disk PCK is disposed on the DR2 side of the temperature compensation circuit 80. In this way, by disposing of the temperature compensation circuit 80 between the oscillation circuit 30 and the clock connection disk PCK, the area between the oscillation circuit 30 and the clock connection disk PCK can be effectively utilized to configure the temperature compensation circuit 80, achieving an efficient layout configuration. Furthermore, by separating the clock connection disk PCK, which is a noise source, from the oscillation circuit 30, the transmission of noise from the clock connection disk PCK to the oscillation circuit 30 can be suppressed. In addition, by disposing of the temperature compensation circuit 80 near the oscillation circuit 30, the temperature compensation voltage VCP from the temperature compensation circuit 80 can be input to the oscillation circuit 30 through a short-path signal path to achieve temperature compensation of the oscillation frequency.

[0079] 4. Oscillator

[0080] Figure 14 The following describes a construction example of an oscillator 4, which is an example of the device in this embodiment. The oscillator 4 includes an oscillator 10, an integrated circuit device 20, and a package 15 housing the oscillator 10 and the integrated circuit device 20. The package 15 is formed, for example, of ceramic, and has an inner storage space in which the oscillator 10 and the integrated circuit device 20 are housed. The storage space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the integrated circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0081] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the integrated circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the oscillator 10 and the base 16. The oscillator 10 is supported on a stepped portion provided inside the base 16 via terminal electrodes. The integrated circuit device 20 is disposed on the inner bottom surface, surface SF, of the base 16. Specifically, the integrated circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the integrated circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the connection pad 2, which serves as a terminal of the integrated circuit device 20. The integrated circuit device 20 is supported on surface SF of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps such as gold bumps. Furthermore, one end of the bump BMP is connected to the connection pad 2 of the integrated circuit device 20, and the other end of the bump BMP is disposed on the mounting surface SF of the integrated circuit device 20 and connected to the terminal TM. Thus, the connection pad 2 of the integrated circuit device 20 is electrically connected to the external terminals 18 and 19, which serve as external connection terminals for the oscillator 4, and the vibrator 10 via the bump BMP, the terminal TM, and internal wiring. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. Therefore, the integrated circuit device 20 can output clock signals, etc., to external devices.

[0082] exist Figure 14 In the process of flip-chip mounting the integrated circuit device 20 onto the surface SF of the package 15, it is used in Figure 8 The ultrasonic bonding described herein. Specifically, ultrasonic bonding is used when connecting the other end of the bump BMP, which is connected to the connector pad 2 of the integrated circuit device 20, to the terminal TM of the surface SF of the package 15. In this case, in this embodiment, the connector pad 2, in which the direction of ultrasonic vibration during ultrasonic bonding is the long side direction DL, is disposed on the integrated circuit device 20. As a result, defects such as short circuits in the wiring caused by ultrasonic vibration can be suppressed. In addition, along the short side direction DS of the connector pad 2, a lead wire 5 is led out from the outer edge EDL of the long side of the connector pad 2, and the lead wire 5 is electrically connected to the wiring 7 of the circuit 8 below the connector pad 2 via the via group 6. As a result, defects caused by stress applied to the lead wire 5 and the via group 6 due to ultrasonic vibration can be suppressed.

[0083] As described above, the oscillator 4 and other devices of this embodiment include: an integrated circuit device 20; a package 15 that houses the integrated circuit device 20; a terminal TM disposed on the surface SF of the package 15; and a bump BMP that electrically connects the terminal TM to the connection pad 2 of the integrated circuit device 20. Thus, by electrically connecting the connection pad 2 of the integrated circuit device 20 and the terminal TM on the surface SF of the package 15 via the bump BMP, signals from the integrated circuit device 20 can be output to the terminal TM, or signals from the terminal TM can be input to the integrated circuit device 20. Furthermore, by mounting the integrated circuit device 20 on the surface SF of the package 15 in this way, and by making the connection pad 2 have a shape with its long side in the direction of its length, and by leading the lead-out wiring 5 of the connection pad 2 out from the outer edge EDL on the long side, the occurrence of the aforementioned various adverse conditions can be suppressed.

[0084] For example, as in Figure 8 As explained, the bump BMP is connected to the terminal TM via ultrasonic bonding, and the long side direction of the connecting plate 2 is the direction of ultrasonic vibration during ultrasonic bonding. In this way, even when stress from ultrasonic vibration during ultrasonic bonding is applied, by setting the connecting plate 2 to a shape with the long side direction and leading the lead wire 5 of the connecting plate 2 out from the outer edge EDL on the long side, it is possible to suppress the occurrence of adverse conditions caused by ultrasonic vibration.

[0085] In addition, such as Figure 14 As shown, the device of this embodiment includes an oscillator 10 housed in a package 15, such as Figure 10 As shown, the integrated circuit device 20 includes an oscillation circuit 30 that generates an oscillation signal OSC by oscillating the oscillator 10. Therefore, as a device of this embodiment, it is possible to achieve… Figure 10 , Figure 14 The oscillator 4 is described in the text. Furthermore, by setting the connection pad 2 of the integrated circuit device 20 assembled in the oscillator 4 to have a shape with the long side direction, and by leading out the lead wire 5 of the connection pad 2 from the outer edge EDL on the long side, the oscillator 4 can be realized to suppress the occurrence of the above-mentioned various adverse conditions, and the reliability of the oscillator 4 can be improved.

[0086] Furthermore, the device in this embodiment is not limited to... Figure 14 The oscillator 4 shown, as described above, can also be a sensor device, display device, communication device, or power supply device, etc.

[0087] Figure 15This is a manufacturing process diagram illustrating an example of the manufacturing method of the device according to this embodiment. The manufacturing method of this embodiment is a method for manufacturing a device including an integrated circuit device 20 and a package 15 housing the integrated circuit device 20, including a manufacturing process S1 for the integrated circuit device 20 and processes S2, S3, and S4 as a mounting process of the integrated circuit device 20 to the package 15.

[0088] In manufacturing process S1, a connection pad 2, a circuit 8 electrically connected to the connection pad 2, lead-out wiring 5 of the connection pad 2, and a via group electrically connecting the lead-out wiring 5 to the wiring 7 of the circuit 8 are formed on the active surface of the integrated circuit device 20. The active surface is the area where circuit elements are formed. For example, in... Figure 1 , Figure 2 As explained in the diagram, the connecting pad 2 is a connecting pad with a shape having a long side direction and a short side direction. The circuit 8 overlaps with the connecting pad 2 when viewed from above and is electrically connected to the connecting pad 2. The lead-out wiring 5 extends from the outer edge EDL of the long side of the connecting pad 2 along the short side direction DS. The via group 6 electrically connects the lead-out wiring 5 to the wiring 7 of the circuit 8 and is positioned in a position that does not overlap with the connecting pad 2 when viewed from above. The manufacturing process S1 of the integrated circuit device 20 is implemented by a semiconductor process. The semiconductor process includes a film formation process for conductive films, insulating films, etc., a photolithography process for patterning using a resist, an etching process for removing unwanted oxide films, an ion implantation process for implanting impurities and activating them through heat treatment, etc., but these processes are well known, so detailed descriptions are omitted.

[0089] In the mounting process following the manufacturing process S1 of the integrated circuit device, a bump BMP is formed on the connector 2 of the integrated circuit device 20 (process S2). For example, a bump BMP called a cylindrical bump is formed. However, the bump BMP is not limited to cylindrical bumps. Next, as in Figure 14 As explained, the integrated circuit device 20 is arranged with the active surface facing the surface SF of the package 15 (step S3). Then, the terminal TM on the surface SF of the package 15 is connected to the bump BMP formed on the connecting pad 2 by ultrasonic bonding with the long side direction of the connecting pad 2 as the vibration direction (step S4). For example, the gold bump BMP and the terminal TM, which is a gold-plated electrode, are joined by friction caused by ultrasonic vibration. The distance between the bonding interfaces is brought closer by the amplitude of the ultrasonic waves, thereby allowing metal atoms to diffuse and join through this metal diffusion. Thus, bonding of the bump BMP and the terminal TM can be achieved at low temperature.

[0090] Thus, according to the manufacturing method of this embodiment, the connection pad 2 of the integrated circuit device 20 can be joined to the terminal TM provided on the surface of the package 15 using ultrasonic vibration. Moreover, in this case, in this embodiment, the connection pad 2 of the integrated circuit device 20 is also provided with a shape having a long side direction, and the lead-out wiring 5 of the connection pad 2 is led out from the outer edge EDL on the long side, so the occurrence of adverse conditions caused by stress caused by ultrasonic vibration can be effectively suppressed.

[0091] As described above, the integrated circuit device of this embodiment includes a connection disk having a shape in the long side direction and a short side direction; a circuit that overlaps with the connection disk when viewed from above and is electrically connected to the connection disk; lead-out wiring that is led out from the outer edge of the long side of the connection disk along the short side direction; and a via group that electrically connects the lead-out wiring to the wiring of the circuit and does not overlap with the connection disk when viewed from above.

[0092] In this embodiment, the circuit is arranged to overlap with the connector pad when viewed from above. Therefore, the area of ​​the connector pad can be effectively utilized to arrange the circuit, enabling miniaturization of the integrated circuit device. Furthermore, the connector pad has a shape with both a long side and a short side, and through-hole groups are used to electrically connect the lead-out wiring extending from the outer edge of the long side of the connector pad along the short side direction to the circuit wiring. This also helps to suppress defects caused by forces acting along the long side direction of the connector pad. Therefore, an integrated circuit device can be provided that achieves miniaturization by arranging the circuit to overlap with the connector pad, and can achieve appropriate lead-out wiring for electrically connecting the connector pad to the circuit.

[0093] Alternatively, in this embodiment, the wiring may be wiring on a metal layer lower than the metal layer of the connecting plate, and when viewed from above, a portion of the wiring overlaps with the connecting plate.

[0094] In this way, the lead wires from the connector are connected to one end of the wires via a group of through holes, and the other end of the wires is connected to the circuit elements of the circuit, thereby enabling the connector to be electrically connected to the circuit elements of the circuit that are arranged in an overlapping manner with the connector.

[0095] Alternatively, in this embodiment, the wiring may be wiring of a metal layer that is arranged with one or more gaps between the metal layers of the connecting plate.

[0096] In this way, even when a load is applied to the connecting plate, it is possible to prevent damage to the wiring and the occurrence of adverse conditions.

[0097] In addition, in this embodiment, the lead-out wiring may also have a shape in which the long side direction of the connecting plate is the long side direction.

[0098] In this way, a shorter horizontal lead wire can be drawn from the outer edge of the long side of the connecting plate, and the lead wire can be electrically connected to the circuit wiring through the through hole group.

[0099] In addition, in this embodiment, the multiple through holes of the through hole group can also be arranged along the long side of the lead wire.

[0100] This allows for an increase in the number of via groups used to electrically connect the lead wires to the circuitry.

[0101] In addition, in this embodiment, the lead-out wiring may also have a shape in which the corners are beveled when viewed from above.

[0102] In this way, when static electricity is applied to the connecting plate, it can prevent the charge from accumulating at the corners and causing adverse conditions.

[0103] Alternatively, in this embodiment, the connection disk may be an input connection disk for inputting input signals, and the circuit may be an I / O circuit that receives input signals from the input connection disk.

[0104] In this way, input signals input to the input connector can be routed to the I / O circuit via lead-out wiring, via groups, and wiring, and the integrated circuit device can be miniaturized by making effective use of the area of ​​the input connector.

[0105] Alternatively, in this embodiment, the connecting disk may be an output connecting disk that outputs the output signal, and the circuit may be an output buffer circuit that outputs the output signal to the output connecting disk.

[0106] This allows the output signal from the output buffer circuit to be output from the output connector via wiring, via groups, and lead-out wiring. Furthermore, it suppresses the performance degradation of integrated circuit devices caused by noise from the output buffer circuit.

[0107] Alternatively, in this embodiment, the connection plate may be a ground connection plate that provides grounding, and the circuit may be a reference voltage generating circuit that generates a reference voltage.

[0108] In this way, the ground voltage supplied to the ground connection pad can be provided to the reference voltage generation circuit via lead-out wiring, via groups, and wiring. In addition, the ground connection pad acts as a shielding layer, which can suppress noise from other circuits in the integrated circuit device from being superimposed on the reference voltage generated by the reference voltage generation circuit.

[0109] Alternatively, in this embodiment, it may include a second lead wire that is led out from the outer edge of the short side of the connecting disk along the long side direction, and the second lead wire is composed of a metal layer of the same layer as the connecting disk.

[0110] Thus, depending on the connection plate, there may also be a connection plate from which the second lead-out wiring is led out from the outer edge of the short side of the connection plate.

[0111] Alternatively, in this embodiment, a second connecting disk may be included, which has a shape having a long side direction and a short side direction, and the long side direction of the connecting disk is the same as the long side direction of the second connecting disk.

[0112] In this way, when bonding integrated circuit devices to the package, ultrasonic bonding vibration can be applied along the long side of the connection pad and the second connection pad, and the stress caused by ultrasonic vibration can be suppressed on the lead-out wiring and via group.

[0113] Additionally, this embodiment relates to an apparatus comprising: a package housing an integrated circuit device; terminals disposed on a surface of the package; and bumps electrically connecting the terminals to a connection pad of the integrated circuit device.

[0114] In this way, the connection pad of the integrated circuit device can be electrically connected to the terminal provided on the surface of the package via the bump, and the occurrence of adverse conditions caused by forces acting along the long side of the connection pad can also be suppressed.

[0115] Alternatively, in this embodiment, the protrusion and the terminal may be ultrasonically joined, with the long side of the connecting disc oriented in the same direction as the long side of the protrusion.

[0116] This can suppress the adverse effects caused by the stress of ultrasonic vibration during ultrasonic bonding.

[0117] Alternatively, in this embodiment, an oscillator housed in a package may also be included, and the integrated circuit device includes an oscillation circuit that causes the oscillator to vibrate to generate an oscillation signal.

[0118] This enables the development of highly reliable oscillators that can suppress various adverse conditions.

[0119] Furthermore, this embodiment is a method for manufacturing an apparatus comprising an integrated circuit device and a package housing the integrated circuit device. The manufacturing method includes: a manufacturing step for the integrated circuit device; and a mounting step for mounting the integrated circuit device onto the package. In the manufacturing step, on the active surface of the integrated circuit device, a connection pad having shapes in a long-side direction and a short-side direction is formed; a circuit that overlaps with the connection pad in plan view and is electrically connected to the connection pad; lead-out wiring that extends from the outer edge of the long-side of the connection pad along the short-side direction; and a via group that electrically connects the lead-out wiring to the wiring of the circuit, and does not overlap with the connection pad in plan view. In the mounting step, bumps are formed on the connection pad of the integrated circuit device, and the integrated circuit device is arranged with the active surface facing the package surface. Terminals on the package surface are connected to the bumps formed on the connection pad by ultrasonic bonding with the long-side direction of the connection pad as the vibration direction.

[0120] According to this manufacturing method, ultrasonic vibration can be used to join the connector pad of the integrated circuit device to the terminals provided on the package surface. Furthermore, the connector pad of the integrated circuit device is shaped with its long side facing outwards, and the lead-out wiring of the connector pad is led out from the outer edge of the long side of the connector pad, thereby suppressing the occurrence of defects caused by stress due to ultrasonic vibration. Therefore, a manufacturing method can be provided that enables miniaturization of the integrated circuit device by arranging the circuit in a manner overlapping with the connector pad, and enables appropriate lead-out wiring for electrically connecting the connector pad to the circuit.

[0121] Furthermore, while this embodiment has been described in detail above, those skilled in the art should readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Moreover, the structure / operation and manufacturing methods of integrated circuit devices and equipment are not limited to those described in this embodiment, and various modifications are possible.

Claims

1. An integrated circuit device, characterized by The integrated circuit device includes: a land having a shape with a long side direction and a short side direction, a circuit that overlaps the land when viewed in plan and is electrically connected to the land; a lead wire that is led out from an outer edge of the land on a long side side of the land in the short side direction of the land, does not overlap the land when viewed in plan; and a via group that electrically connects the lead wire and a wire of the circuit, does not overlap the land when viewed in plan, and is disposed below the lead wire in a manner that overlaps the lead wire when viewed in plan.

2. The integrated circuit device according to claim 1, wherein the wire is a wire of a metal layer that is lower than a metal layer of the land, a portion of the wire overlaps the land when viewed in plan.

3. The integrated circuit device according to claim 2, wherein the wire is a wire of a metal layer that is disposed with a separation of one or more layers from the metal layer of the land.

4. The integrated circuit device according to any one of claims 1 to 3, wherein the lead wire has a shape with the long side direction of the land as a long side direction.

5. The integrated circuit device according to claim 4, wherein a plurality of vias of the via group are arranged in the long side direction of the lead wire.

6. The integrated circuit device according to any one of claims 1 to 3, wherein the lead wire has a shape in which a corner portion when viewed in plan is chamfered.

7. The integrated circuit device according to any one of claims 1 to 3, wherein the land is an input land that inputs an input signal, the circuit is an I / O circuit that inputs the input signal from the input land.

8. The integrated circuit device according to any one of claims 1 to 3, wherein the land is an output land that outputs an output signal, the circuit is an output buffer circuit that outputs the output signal to the output land.

9. The integrated circuit device according to any one of claims 1 to 3, wherein the land is a ground land that provides a ground, the circuit is a reference voltage generation circuit that generates a reference voltage.

10. The integrated circuit device according to any one of claims 1 to 3, wherein the integrated circuit device includes a second lead wire that is led out from an outer edge of the land on a short side side of the land in the long side direction of the land, the second lead wire is composed of a metal layer that is the same layer as the land.

11. The integrated circuit device according to any one of claims 1 to 3, wherein the integrated circuit device includes a second land having a shape with a long side direction and a short side direction, the long side direction of the land and the long side direction of the second land are in the same direction.

12. An apparatus, comprising: The apparatus includes: the integrated circuit device according to any one of claims 1 to 9; a package in which the integrated circuit device is housed; a terminal provided to a face of the package; and a terminal provided to a face of the package; and a bump electrically connecting the terminal and the land of the integrated circuit device.

13. The apparatus according to claim 12, wherein the bump is ultrasonically joined with the terminal, the long-side direction of the land is a long-side direction of the bump.

14. The apparatus according to claim 12, wherein the apparatus includes a vibrator housed in the package, the integrated circuit device includes an oscillation circuit that generates an oscillation signal by vibrating the vibrator.

15. A manufacturing method of an apparatus including an integrated circuit device and a package housing the integrated circuit device, the manufacturing method comprising: a manufacturing process of the integrated circuit device; and a mounting process of mounting the integrated circuit device in the package, in the manufacturing process, on an active surface of the integrated circuit device, a land having a shape with a long-side direction and a short-side direction, a circuit that overlaps the land when viewed in plan and is electrically connected to the land, a lead wire that is led out from an outer edge of the land on a long-side side of the land in the short-side direction of the land and does not overlap the land when viewed in plan, and a via group that electrically connects the lead wire and a wire of the circuit, does not overlap the land when viewed in plan, and is disposed below the lead wire in a manner of overlapping the lead wire when viewed in plan are formed, in the mounting process, a bump is formed on the land of the integrated circuit device, the integrated circuit device is disposed in a manner that the active surface faces a surface of the package, a terminal provided to the surface of the package is connected to the bump formed on the land by ultrasonic joining in a manner that the long-side direction of the land is a vibration direction.

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