Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, comprising a substrate and a pixel circuit, a power line, a first data line and a second data line located on one side of the substrate; the pixel circuit comprises a first transistor and a second transistor, the orthographic projection of the semiconductor pattern of the first transistor on the substrate is closer to the orthographic projection of the first data line on the substrate than the orthographic projection of the semiconductor pattern of the second transistor on the substrate, and the orthographic projection of the semiconductor pattern of the second transistor on the substrate is closer to the orthographic projection of the second data line on the substrate than the orthographic projection of the semiconductor pattern of the first transistor on the substrate; the orthographic projection of the power line on the substrate passes through the area between the semiconductor pattern of the first electrode of the second transistor and the orthographic projection of the second data line on the substrate. Therefore, the array substrate and the display panel provided by the present application can reduce the voltage drop of the power line, and ensure the power supply effect of the array substrate and the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Organic Light-Emitting Diode (OLED) has the characteristics of active luminescence, high contrast, ultra-lightness, low temperature resistance, fast response speed, low power consumption, wide viewing angle, and strong shock resistance, so it is used more and more.

[0003] In the related art, the display panel includes an array substrate and a light-emitting layer. The array substrate has a high-level (ELVDD) signal line. One end of the ELVDD signal line is electrically connected to a power chip, and the other end of the ELVDD signal line is electrically connected to an anode in the light-emitting layer, thereby providing a high-level signal to the anode.

[0004] However, the voltage drop of the ELVDD signal line is relatively large, thereby affecting the display effect of the display panel. Summary of the invention

[0005] In view of at least one of the above technical problems, the embodiments of the present application provide an array substrate and a display panel, which can reduce the voltage drop of the ELVDD signal line, thereby ensuring the power supply effect of the array substrate and the display effect of the display panel.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides an array substrate, comprising: a substrate and a pixel circuit, a power line, a first data line, and a second data line located on one side of the substrate, wherein the first data line and the second data line are arranged at intervals along a first direction, and the power line, the first data line, and the second data line all extend in a second direction;

[0008] The pixel circuit includes a first transistor and a second transistor, the orthographic projection of a semiconductor pattern of the first transistor on a substrate is closer to the orthographic projection of a first data line on the substrate than the orthographic projection of a semiconductor pattern of the second transistor on the substrate, the orthographic projection of the semiconductor pattern of the second transistor on the substrate is closer to the orthographic projection of the second data line on the substrate than the orthographic projection of the semiconductor pattern of the first transistor on the substrate, the orthographic projection of the semiconductor pattern of the first electrode of the second transistor on the substrate is located between the orthographic projections of the first data line and the second data line on the substrate; the orthographic projection of the power line on the substrate passes through the area between the semiconductor pattern of the first electrode of the second transistor and the orthographic projection of the second data line on the substrate; wherein the first direction is different from the second direction.

[0009] In the array substrate provided by the embodiment of the present application, the orthographic projection of the power line on the substrate passes through the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the second data line on the substrate. The orthographic projection of the power line on the substrate does not pass through the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the semiconductor pattern of the first pole of the first transistor on the substrate, so as to avoid the influence of the width of the power line due to the small distance between the semiconductor pattern of the first pole of the second transistor and the semiconductor pattern of the first pole of the first transistor. The width of the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the second data line on the substrate is large, and the part of the power line passing through the area can be set wider, so that the resistance of the part of the power line passing through the area is low, and the voltage drop of the power line can be reduced, thereby ensuring the display effect of the display panel.

[0010] In a possible implementation, the power line includes a first extension segment, an orthographic projection of the first extension segment on the substrate is located between the second data line and an orthographic projection of the semiconductor pattern of the first electrode of the second transistor on the substrate, and a distance between the orthographic projection of the semiconductor pattern of the first electrode of the second transistor on the substrate and the orthographic projection of the second data line on the substrate is greater than a maximum width of the first extension segment;

[0011] A distance between the semiconductor pattern of the first electrode of the first transistor and the semiconductor pattern of the first electrode of the second transistor is smaller than a minimum width of the first extending section.

[0012] In this way, short circuit between the power line and other structures can be avoided; in addition, the first extension section can be set wider, so that the voltage drop of the first extension section is smaller, so as to ensure the display effect of the display panel.

[0013] In a possible implementation, the first transistor is used for data writing, the first electrode of the first transistor is electrically connected to the first data line or the second data line, and the orthographic projection of the power line on the substrate does not overlap with the orthographic projection of the semiconductor pattern of the first transistor on the substrate.

[0014] In this way, the power line can be avoided from being located directly above the semiconductor pattern of the first transistor, thereby avoiding excessive coupling capacitance between the power line and the data line when the first transistor writes a signal on the data line, and reducing interference between the power line and the data line, which is beneficial to the display of the display panel.

[0015] In a possible implementation, the pixel circuit further includes a driving transistor and a third transistor, and the third transistor is used to control the light-emitting unit to emit light in the light-emitting stage;

[0016] A first electrode of the third transistor is electrically connected to the power line, a second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, a distance between an orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and an orthographic projection of the first data line on the substrate is greater than a distance between an orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and an orthographic projection of the second data line on the substrate, and a distance between an orthographic projection of the semiconductor pattern of the second electrode of the third transistor on the substrate and an orthographic projection of the second data line on the substrate is greater than a distance between an orthographic projection of the semiconductor pattern of the second electrode of the third transistor on the substrate and an orthographic projection of the first data line on the substrate;

[0017] It can be realized that the distance between the orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and the orthographic projection of the second data line on the substrate is in the range of 1.2 μm-3 μm.

[0018] In this way, the semiconductor pattern of the first electrode of the third transistor is conveniently connected to the power line through the via hole.

[0019] In a possible implementation, the pixel circuit includes a fourth transistor and a fifth transistor, the fourth transistor is used to control the light-emitting unit to emit light in the light-emitting stage, and the first electrode of the fourth transistor is electrically connected to the light-emitting unit, and the fifth transistor is used to reset the light-emitting unit;

[0020] Orthographic projections of the semiconductor pattern of the fourth transistor and the semiconductor pattern of the fifth transistor on the substrate are respectively located on both sides of the orthographic projection of the semiconductor pattern of the third transistor on the substrate.

[0021] In a possible implementation manner, the semiconductor pattern of the first electrode of the fourth transistor is disconnected from the semiconductor pattern of the first electrode of the fifth transistor;

[0022] The array substrate further includes a connection line, which is used to electrically connect the semiconductor pattern of the first electrode of the fourth transistor with the semiconductor pattern of the first electrode of the fifth transistor, and the connection line and the semiconductor pattern of the pixel circuit are located in different layers.

[0023] In this way, short circuits among the semiconductor pattern of the fifth transistor, the semiconductor pattern of the fourth transistor, and the semiconductor pattern of the first electrode of the third transistor can be avoided.

[0024] In a possible embodiment, there are multiple pixel circuits, and the multiple pixel circuits are arranged in the first direction and the second direction. In two adjacent pixel circuits in the second direction, the first electrode of the first transistor of one pixel circuit is electrically connected to the first data line, and the first electrode of the first transistor of the other pixel circuit is electrically connected to the second data line.

[0025] In this way, the data writing time can be increased, which is beneficial to high refresh rate and power consumption.

[0026] In a possible implementation, the first data line and the second data line are both provided with data connection ends, and are respectively electrically connected to the first electrode of the corresponding first transistor through the corresponding data connection ends, the data connection end is located between the first data line and the second data line, and the distance between the data connection end and the first data line is equal to the distance between the data connection end and the second data line.

[0027] In this way, the transmission distances of the first data line and the second data line and the first transistors of the odd and even rows are made consistent, thereby ensuring the consistency of the data signals of the pixel circuits of the odd and even rows.

[0028] In a possible implementation, the pixel circuit includes a driving transistor and a sixth transistor, the sixth transistor is used to reset the gate of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the gate of the driving transistor; the orthographic projection of the power line on the substrate at least partially overlaps with the orthographic projection of the semiconductor pattern of the second electrode of the sixth transistor on the substrate;

[0029] Along the thickness direction of the array substrate, the semiconductor pattern of the sixth transistor and the second data line are located at two opposite sides of the power line.

[0030] In this way, signal interference between the semiconductor pattern at the second electrode of the sixth transistor and the second data line can be reduced.

[0031] A second aspect of the embodiments of the present application provides a display panel, comprising the array substrate in the first aspect.

[0032] The display panel provided by the embodiment of the present application includes an array substrate, and the orthographic projection of the power line on the substrate passes through the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the second data line on the substrate. The orthographic projection of the power line on the substrate does not pass through the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the semiconductor pattern of the first pole of the first transistor on the substrate, so as to avoid the influence of the width of the power line due to the small distance between the semiconductor pattern of the first pole of the second transistor and the semiconductor pattern of the first pole of the first transistor. The width of the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the second data line on the substrate is large, and the part of the power line passing through the area can be set wider, so that the resistance of the part of the power line passing through the area is low, and the voltage drop of the power line can be reduced, thereby ensuring the display effect of the display panel.

[0033] The construction of the present application and its other inventive objectives and beneficial effects will be more clearly understood through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A partial top view of an array substrate;

[0036] Figure 2 A partial top view of an array substrate provided in an embodiment of the present application;

[0037] Figure 3 A circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0038] Figure 4 for Figure 2 Another enlarged view of part E in the middle;

[0039] Figure 5 A schematic diagram of the structure of a semiconductor pattern layer provided in an embodiment of the present application.

[0040] Description of reference numerals:

[0041] 101-first metal layer; 103-third metal layer;

[0042] 104-a fourth metal layer; 105-a semiconductor pattern layer;

[0043] 110-signal line group; 111-first data line;

[0044] 112 - a second data line; 113 - a data connection terminal;

[0045] 131-first connecting line; 132-second connecting line;

[0046] 133 - the third connecting line; 134 - the fourth connecting line. DETAILED DESCRIPTION

[0047] In related technologies, such as Figure 1As shown, the array substrate may include a first connection line 131, a second connection line 132, a data line Data, a power line ELVDD and a pixel circuit, wherein the pixel circuit includes a first transistor T1, a second transistor T2 and a driving transistor DT. The first transistor T1 is used for data writing, and the second transistor T2 is used for threshold compensation. The data line Data is electrically connected to the first transistor T1 through the first connection line 131, the first transistor T1 and the second transistor T2 are electrically connected through the driving transistor DT, and the second transistor T2 is electrically connected to the capacitor through the second connection line 132, so that the data signal on the data line Data is written into the capacitor of the pixel circuit through the first connection line 131, the first transistor T1, the driving transistor DT, the second transistor T2 and the second connection line 132.

[0048] The first end A1 of the first connection line 131 is electrically connected to the first electrode of the first transistor T1, and the second end A2 of the first connection line 131 is electrically connected to the data line Data; the first end B1 of the second connection line 132 is electrically connected to the first electrode of the second transistor T2, and the second end B2 of the second connection line 132 is electrically connected to the first plate of the capacitor. The power line ELVDD is used to provide a power signal to the pixel circuit. The power line ELVDD is arranged in the same layer as the first connection line 131 and the second connection line 132. Part of the power line ELVDD is located between the first connection line 131 and the second connection line 132, and is spaced from the first connection line 131 and the second connection line 132, respectively.

[0049] However, the distance between the first electrode of the first transistor T1 and the first electrode of the second transistor T2 is small, resulting in a distance W ( Figure 1 As a result, the power line ELVDD between the first end A1 of the first connection line 131 and the first end B1 of the second connection line 132 is narrower, and the resistance of the power line ELVDD is larger, resulting in a larger voltage drop of the power line ELVDD, thereby affecting the display effect of the display panel.

[0050] Based on at least one of the above technical problems, the embodiments of the present application provide an array substrate and a display panel, wherein the array substrate may include: a substrate and a pixel circuit, a power line, a first data line and a second data line located on one side of the substrate, wherein the first data line and the second data line are arranged at intervals along a first direction, and the power line, the first data line and the second data line all extend in a second direction; the pixel circuit includes a first transistor and a second transistor, wherein the orthogonal projection of the semiconductor pattern of the first transistor on the substrate is closer to the orthogonal projection of the first data line on the substrate than the orthogonal projection of the semiconductor pattern of the second transistor on the substrate, and the orthogonal projection of the semiconductor pattern of the second transistor on the substrate is closer to the orthogonal projection of the second data line on the substrate than the orthogonal projection of the semiconductor pattern of the first transistor on the substrate, and the orthogonal projection of the semiconductor pattern of the first electrode of the second transistor on the substrate is located between the orthogonal projections of the first data line and the second data line on the substrate; the orthogonal projection of the power line on the substrate passes through the area between the semiconductor pattern of the first electrode of the second transistor and the orthogonal projection of the second data line on the substrate; wherein the first direction is different from the second direction. The orthogonal projection of the power line on the substrate passes through the area between the semiconductor pattern of the first electrode of the second transistor and the orthogonal projection of the second data line on the substrate. The orthographic projection of the power line on the substrate does not pass through the area between the semiconductor pattern of the first pole of the second transistor and the orthographic projection of the semiconductor pattern of the first pole of the first transistor on the substrate, thereby avoiding the influence of the width of the power line due to the small distance between the semiconductor pattern of the first pole of the second transistor and the semiconductor pattern of the first pole of the first transistor. The width of the area between the orthographic projection of the semiconductor pattern of the first pole of the second transistor on the substrate and the orthographic projection of the second data line on the substrate is large, and the part of the power line passing through the area can be set wider, so that the resistance of the part of the power line passing through the area is low, so as to reduce the voltage drop of the power line, thereby ensuring the display effect of the display panel.

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The following will be combined Figure 2-Figure 5 The display panel provided in the embodiment of the present application is described.

[0053] This embodiment provides a display panel, which can be applied to mobile or fixed terminals such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, smart bracelets, smart watches, super personal computers, and navigators.

[0054] The display panel may be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0055] The display panel may include an array substrate and a light emitting layer on the array substrate. The array substrate is electrically connected to the light emitting layer. The light emitting layer may include an anode and a cathode, wherein the anode is located on a side of the cathode facing the array substrate. The anode may be a pixel electrode, and the cathode may be a common electrode. The light emitting layer may include a plurality of light emitting units arranged at intervals, and the light emitting units include a light emitting material.

[0056] The array substrate provided in the embodiments of the present application is described below.

[0057] In an embodiment of the present application, the array substrate may include a substrate, and the substrate may provide support for the remaining structural layers that are subsequently arranged. In some examples, the substrate may be a rigid substrate, for example, the material of the substrate may be glass. In some other examples, the substrate may be a flexible substrate, and the material of the substrate may include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0058] like Figure 2 As shown, the array substrate may include a first direction X, which may be the width direction of the array substrate; the array substrate may include a second direction Y, which may be the length direction of the array substrate; the array substrate may include a third direction, which may be the thickness direction of the array substrate. The length, width, and thickness in the embodiments of the present application are only for the convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to, or less than the length. Among them, the first direction X, the second direction Y, and the third direction are all different.

[0059] like Figure 2 and Figure 3 As shown, the array substrate may include a plurality of signal line groups 110 on a substrate, the plurality of signal line groups 110 may be arranged at intervals along a first direction X, and each signal line group 110 extends along a second direction Y. Each signal line group 110 may include a data line Data and a power line ELVDD. In addition, the array substrate may also be provided with a first scan line S1, a second scan line S2, a light emitting control line EM, a power line ELVSS, a first reference line Vref1, and a second reference line Vref2.

[0060] The array substrate may include a plurality of pixel circuit groups located on a substrate, and the plurality of pixel circuit groups may be arranged at intervals along a first direction X, and each pixel circuit group includes a plurality of pixel circuits arranged at intervals along a second direction Y. For example, the first direction X may be a row direction, and the second direction Y may be a column direction; or, the first direction X may be a column direction, and the second direction Y may be a row direction. The embodiment of the present application is described by taking the first direction X as the row direction and the second direction Y as the column direction as an example. The plurality of pixel circuits may be arranged in an array in the first direction and the second direction. The pixel circuit is electrically connected to the anode of the light-emitting unit to provide a driving signal for the light-emitting unit. The pixel circuit may include a plurality of transistors (Thin Film Transistor, referred to as TFT) and a capacitor structure C.

[0061] like Figure 4 and Figure 5 As shown, the array substrate may include a semiconductor pattern layer 105, a first metal layer 101, a second metal layer (not shown in the figure), a third metal layer 103 and a fourth metal layer 104 which are sequentially stacked on a substrate, and an insulating layer is provided between two adjacent layers of the semiconductor pattern layer 105, the first metal layer 101, the second metal layer, the third metal layer 103 and the fourth metal layer 104.

[0062] The semiconductor pattern layer 105 includes an active layer of multiple transistors, the first metal layer 101 may include a first scan line S1, a second scan line S2, a first electrode of a capacitor structure C, a light-emitting control line EM and at least one of gates of multiple transistors; the second metal layer may include a first reference line Vref1, a second reference line Vref2 and at least one of a second electrode of the capacitor structure C; the third metal layer 103 may include a power line ELVDD; and the fourth metal layer 104 may include a data line Data.

[0063] The material of the semiconductor pattern layer 105 may include polysilicon or metal oxide. The material of any one or more of the first metal layer 101, the second metal layer, the third metal layer 103 and the fourth metal layer 104 may include metal materials such as silver, aluminum, copper, etc.

[0064] Exemplarily, multiple pixel circuits can be arranged into M rows and N columns, and multiple pixel circuits in the same column form a pixel circuit group, that is, the array substrate can include N columns of pixel circuit groups, one pixel circuit group is corresponding to one signal line group 110, and a corresponding signal line group 110 is electrically connected to one pixel circuit group, that is, the signal line group 110 can also include N columns.

[0065] The array substrate also includes a data driver for providing data signals to the data lines Data, a scan driver for providing scan signals to the first scan lines S1 and the second scan lines S2, a light driver for providing light control signals to the light control lines EM, and a timing controller for providing drive signals to the data driver, the scan driver and the light driver.

[0066] like Figure 2 As shown, the i-th column pixel circuit group is electrically connected to the i-th column signal line group 110, and the data lines Data in each column signal line group 110 may include a first data line 111 and a second data line 112 arranged at intervals along the first direction X, and the orthographic projections of the first data line 111 and the second data line 112 on the substrate are located on both sides of the orthographic projection of the corresponding pixel circuit group on the substrate. Wherein, M and N are positive integers, and i is a positive integer less than or equal to N.

[0067] In two pixel circuits adjacent to each other in the second direction Y, the first pole T11 of the first transistor T1 of one pixel circuit is electrically connected to the first data line 111, and the first pole T11 of the first transistor T1 of the other pixel circuit is electrically connected to the second data line 112. For example, the first data line 111 can be connected to the pixel circuit of the odd row, and the second data line 112 can be connected to the pixel circuit of the even row. Alternatively, the first data line 111 can be connected to the pixel circuit of the even row, and the second data line 112 can be connected to the pixel circuit of the odd row. Two sub-data lines (the first data line 111 and the second data line 112) are correspondingly arranged in each column pixel circuit group, which can increase the data writing time, and is conducive to high refresh and power consumption. The embodiment of the present application is described by taking the first data line 111 connected to the pixel circuit of the odd row and the second data line 112 connected to the pixel circuit of the even row as an example.

[0068] The power line ELVDD in each column of the signal line group 110 provides power signals to each pixel circuit in the corresponding pixel circuit group. In the same signal line group 110, the positive projection of the power line ELVDD on the substrate is located between the positive projections of the first data line 111 and the second data line 112 on the substrate, and the positive projection of the power line ELVDD on the substrate does not overlap with the positive projections of the first data line 111 and the second data line 112 on the substrate, which can reduce the parasitic capacitance between the power line ELVDD and the first data line 111 and the second data line 112, thereby reducing the crosstalk between the power line ELVDD and the first data line 111 and the second data line 112, and reducing the impact on the display effect of the display panel.

[0069] The following describes a plurality of transistors provided in embodiments of the present application.

[0070] like Figure 2As shown, the pixel circuit may include any one or more of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor DT. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be switch transistors.

[0071] The type of transistors in the pixel circuit may be P-type transistors or N-type transistors. Alternatively, a portion of the transistors may be P-type transistors, and the remaining number of transistors may be N-type transistors. Different enable levels are provided according to different transistor types. The enable level refers to the level at which the transistor can be turned on. Exemplarily, when the transistor is a P-type transistor, the enable level is a low level. When the transistor is an N-type transistor, the enable level is a high level. The embodiment of the present application is described by taking a plurality of transistors as P-type transistors as an example.

[0072] like Figure 2 As shown, the orthographic projection of the semiconductor pattern of the first transistor T1 (the pattern on the semiconductor pattern layer 105) on the substrate is closer to the orthographic projection of the first data line 111 on the substrate than the orthographic projection of the semiconductor pattern of the second transistor T2 on the substrate. That is, the distance between the orthographic projection of the semiconductor pattern of the first transistor T1 on the substrate and the orthographic projection of the first data line 111 on the substrate is smaller than the distance between the orthographic projection of the semiconductor pattern of the second transistor T2 on the substrate and the orthographic projection of the first data line 111 on the substrate.

[0073] The orthographic projection of the semiconductor pattern of the second transistor T2 on the substrate is closer to the orthographic projection of the second data line 112 on the substrate than the orthographic projection of the semiconductor pattern of the first transistor T1 on the substrate. That is, the distance between the orthographic projection of the semiconductor pattern of the second transistor T2 on the substrate and the orthographic projection of the second data line 112 on the substrate is smaller than the distance between the orthographic projection of the semiconductor pattern of the first transistor T1 on the substrate and the orthographic projection of the second data line 112 on the substrate.

[0074] The orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate is located between the orthographic projection of the first data line 111 on the substrate and the orthographic projection of the second data line 112 on the substrate.

[0075] It should be noted that one of the first electrode and the second electrode of the transistor may be the source electrode of the transistor, and the other of the first electrode and the second electrode of the transistor may be the drain electrode of the transistor. The semiconductor pattern of the transistor may include a source electrode, a drain electrode, and a channel structure located between the source electrode and the drain electrode. The distance between the orthogonal projection of the semiconductor pattern of the transistor on the substrate and the orthogonal projection of another structure on the substrate may be the distance between the orthogonal projection of the channel structure of the transistor on the substrate and the orthogonal projection of another structure on the substrate. For example, the distance between the orthogonal projection of the semiconductor pattern of the first transistor T1 on the substrate and the orthogonal projection of the first data line 111 on the substrate is smaller than the distance between the orthogonal projection of the semiconductor pattern of the second transistor T2 on the substrate and the orthogonal projection of the first data line 111 on the substrate. It can be seen that the distance between the orthogonal projection of the channel structure of the first transistor T1 on the substrate and the orthogonal projection of the first data line 111 on the substrate is smaller than the distance between the orthogonal projection of the channel structure of the second transistor T2 on the substrate and the orthogonal projection of the first data line 111 on the substrate.

[0076] The orthographic projection of the semiconductor pattern of the driving transistor DT on the substrate is located between the orthographic projections of the first data line 111 and the second data line 112 on the substrate; the semiconductor pattern of the third transistor T3 is located on the side of the semiconductor pattern of the driving transistor DT away from the semiconductor pattern of the first transistor T1; the semiconductor pattern of the fourth transistor T4 is located on the side of the semiconductor pattern of the driving transistor DT away from the semiconductor pattern of the second transistor T2; the orthographic projections of the semiconductor pattern of the fourth transistor T4 and the semiconductor pattern of the fifth transistor T5 on the substrate are respectively located on opposite sides of the orthographic projection of the semiconductor pattern of the third transistor T3 on the substrate; the semiconductor pattern of the sixth transistor T6 is located on the side of the semiconductor pattern of the second transistor T2 away from the driving transistor DT.

[0077] like Figure 3 and Figure 5 As shown, the first transistor T1 is used for data writing, the second transistor T2 is used for threshold compensation, the third transistor T3 and the fourth transistor T4 are used to control the light emitting unit to emit light in the light emitting stage, the fifth transistor T5 is used to reset the light emitting unit; the sixth transistor T6 is used to reset the gate of the driving transistor DT.

[0078] The first electrode T11 of the first transistor T1 is electrically connected to the first data line 111 or the second data line 112, and the second electrode T12 of the first transistor T1 is electrically connected to the first electrode DT1 of the driving transistor DT; the second electrode DT2 of the driving transistor DT is electrically connected to the second electrode T22 of the second transistor T2, and the first electrode T21 of the second transistor T2 is electrically connected to the first electrode plate of the capacitor structure C; the first electrode T31 of the third transistor T3 is electrically connected to the power line ELVDD, and the second electrode T32 of the third transistor T3 is electrically connected to the first electrode DT1 of the driving transistor DT; the fourth transistor T3 is electrically connected to the power line ELVDD, and the second electrode T32 of the third transistor T3 is electrically connected to the first electrode DT1 of the driving transistor DT; The first electrode T41 of T4 is electrically connected to the anode, and the second electrode T42 of the fourth transistor T4 is electrically connected to the second electrode DT2 of the driving transistor DT; the first electrode T51 of the fifth transistor T5 is electrically connected to the anode, and the second electrode T52 of the fifth transistor T5 is electrically connected to the second reference line Vref2; the first electrode T61 of the sixth transistor T6 is electrically connected to the first reference line Vref1, and the second electrode T62 of the sixth transistor T6 is electrically connected to the first electrode plate of the capacitor structure C; the second electrode plate of the capacitor structure C is connected to the power line ELVDD; the cathode of the light-emitting layer is connected to the power line ELVSS.

[0079] In addition, the gate of the first transistor T1 is connected to the second scan line S2, the gate of the second transistor T2 is connected to the second scan line S2, the gate of the third transistor T3 is connected to the light emitting control line EM, the gate of the fourth transistor T4 is connected to the light emitting control line EM, the gate of the fifth transistor T5 is connected to the first scan line S1' of the pixel circuit in the previous row, and the gate of the sixth transistor T6 is connected to the first scan line S1 of the pixel circuit in this row; the gate of the driving transistor DT is connected to the first plate of the capacitor structure C.

[0080] The working process of the pixel circuit provided in the embodiment of the present application is described below.

[0081] In the first stage, the light-emitting control line EM provides a high level, controls the third transistor T3 and the fourth transistor T4 to be turned off, and the light-emitting layer does not emit light. The first scan line S1 corresponding to the pixel circuit of the current row provides a low level, controls the sixth transistor T6 to be turned on, and the reference voltage of the first reference line Vref1 is transmitted to the gate of the driving transistor DT, and the gate of the driving transistor DT is reset; the second scan line S2 provides a high level, controls the first transistor T1 and the second transistor T2 to be turned off, and the first scan line S1' corresponding to the pixel circuit of the previous row provides a low level, controls the fifth transistor T5 to be turned on, and the reference voltage of the second reference line Vref2 is transmitted to the anode, and the anode of the light-emitting layer is reset.

[0082] In the second stage, the light-emitting control line EM provides a high level to control the third transistor T3 and the fourth transistor T4 to be turned off, and the light-emitting layer does not emit light. The first scan line S1 corresponding to the pixel circuit of this row provides a high level to control the sixth transistor T6 to be turned off, and the second scan line S2 provides a low level to control the first transistor T1 and the second transistor T2 to be turned on. The data voltage of the data line Data is transmitted to the first electrode plate of the capacitor structure C through the first transistor T1, the driving transistor DT and the second transistor T2, and the capacitor structure C is charged. The first scan line S1' corresponding to the pixel circuit of the previous row provides a high level to control the fifth transistor T5 to be turned off.

[0083] In the third stage (i.e., the light emitting stage), the light emitting control line EM provides a low level to control the third transistor T3 and the fourth transistor T4 to be turned on. The first scanning line S1 corresponding to the pixel circuit of the current row provides a high level to control the sixth transistor T6 to be turned off; the second scanning line S2 provides a high level to control the first transistor T1 and the second transistor T2 to be turned off, and the first scanning line S1' corresponding to the pixel circuit of the previous row provides a high level to control the fifth transistor T5 to be turned off. Under the potential control of the first electrode plate of the capacitor structure C, the driving transistor DT is turned on: the power line ELVDD provides a driving current to the light emitting layer to drive the light emitting layer to emit light.

[0084] The connection between the data line Data and the first transistor T1 provided in the embodiment of the present application is described below.

[0085] The first data line 111 is electrically connected to the first electrodes T11 of the first transistors T1 in odd-numbered rows, and the second data line 112 is electrically connected to the first electrodes T11 of the first transistors T1 in even-numbered rows.

[0086] like Figure 2 As shown, the first data line 111 and the second data line 112 are both provided with a data connection terminal 113, and the data connection terminal 113 can be connected to the data line Data and provided in the same layer and the same material, so that the preparation process of the array substrate can be simplified. The orthographic projection of the data connection terminal 113 on the substrate is located between the orthographic projections of the first data line 111 and the second data line 112 on the substrate. The data connection terminal 113 of the first data line 111 is located on the side of the first data line 111 facing the second data line 112, and the data connection terminal 113 of the second data line 112 is located on the side of the second data line 112 facing the first data line 111.

[0087] like Figure 2As shown, the array substrate is provided with a first connection line 131, and one first connection line 131 is provided corresponding to one pixel circuit. In the odd rows, the data connection end 113 of the first data line 111 is connected to the first end of the first connection line 131 of the odd rows, and the second end of the first connection line 131 of the odd rows is connected to the first electrode T11 of the first transistor T1 of the odd rows, so that the data signal of the first data line 111 is transmitted to the first transistor T1 of the odd rows. In addition, in the even rows, the data connection end 113 of the second data line 112 is connected to the first end of the first connection line 131 of the even rows, and the second end of the first connection line 131 of the even rows is connected to the first electrode T11 of the first transistor T1 of the even rows, so that the data signal of the second data line 112 is transmitted to the first transistor T1 of the even rows. For example, the first connection line 131 can be provided in the same layer and the same material as the power line ELVDD, so that the preparation process of the array substrate can be simplified.

[0088] Exemplarily, along the first direction X, the distance between the data connection terminal 113 and the first data line 111 is equal to the distance between the data connection terminal 113 and the second data line 112. The data connection terminal 113 is located at the center of the first data line 111 and the second data line 112, so that the transmission distance between the first data line 111 and the first transistor T1 of the odd row is equal to the transmission distance between the second data line 112 and the first transistor T1 of the even row, thereby ensuring the consistency of the data signals of the pixel circuits of the odd row and the even row.

[0089] like Figure 2 As shown, the array substrate may include a second connection line 132, one end of the second connection line 132 is electrically connected to the first electrode T21 of the second transistor T2, and the other end of the second connection line 132 is electrically connected to the first electrode plate of the capacitor structure C, so that the data line Data is charged to the first electrode plate of the capacitor structure C through the first connection line 131, the first transistor T1, the driving transistor DT, the second transistor T2, and the second connection line 132. For example, the second connection line 132 can be set in the same layer and material as the power line ELVDD, so that the preparation process of the array substrate can be simplified.

[0090] Continue to refer Figure 2 and Figure 5, the semiconductor pattern of the first electrode T21 of the second transistor T2 is closer to the semiconductor pattern of the first transistor T1 than the semiconductor pattern of the second electrode T22 of the second transistor T2, and the distance between the orthographic projection of each part of the power line ELVDD on the substrate and the orthographic projection of the second data line 112 on the substrate is smaller than the distance between the orthographic projection of the part of the power line ELVDD on the substrate and the orthographic projection of the first data line 111 on the substrate. A part of the orthographic projection of the power line ELVDD on the substrate is located between the second data line 112 and the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate. That is, the orthographic projection of the power line ELVDD on the substrate passes through the area between the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate and the orthographic projection of the second data line 112 on the substrate (i.e. Figure 2 The orthographic projection of the power line ELVDD on the substrate no longer passes through the area between the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate and the orthographic projection of the first data line 111 on the substrate. The distance W1 ( Figure 2 ) is small and affects the width W2 of the power line ELVDD ( Figure 2 In addition, the width of the area between the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate and the orthographic projection of the second data line 112 on the substrate is relatively large, and the portion of the power line ELVDD passing through the area can be set to be relatively wide, so that the resistance of the portion of the power line ELVDD passing through the area is relatively low, and the voltage drop of the power line ELVDD can be reduced, thereby ensuring the display effect of the display panel.

[0091] Exemplarily, the power line ELVDD includes a first extension section (i.e., located at Figure 2 The power line ELVDD in the middle G area), the orthographic projection of the first extension segment on the substrate is located between the orthographic projection of the second data line 112 on the substrate and the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate, and the distance between the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate and the orthographic projection of the second data line 112 on the substrate is greater than the width W2 ( Figure 2 ) to avoid a short circuit between the power line ELVDD and the second connection line 132. The semiconductor pattern of the first electrode T21 of the second transistor T2 is far from the second data line 112 along the first direction X, and the first extension segment can be set wider, so that the voltage drop of the first extension segment is small, so as to ensure the display effect of the display panel.

[0092] It should be noted that the distance between the orthographic projection of the semiconductor pattern of the first electrode T21 of the second transistor T2 on the substrate and the orthographic projection of the second data line 112 on the substrate is, Figure 2 The extension length of the middle G region along the first direction X can also be regarded as Figure 5 The distance W3 between the orthographic projection of the second connection line 132 on the substrate and the orthographic projection of the second data line 112 on the substrate.

[0093] Exemplarily, the distance W1 ( Figure 2 ), which is smaller than the width W2 of the first extension section ( Figure 2 ) minimum value; thereby making the width of the power line ELVDD larger, the power line ELVDD resistance can be reduced to ensure the display effect of the display panel. Wherein, the width direction of the power line ELVDD can be the first direction X.

[0094] like Figure 5 As shown, the orthographic projection of the power line ELVDD on the substrate does not overlap with the orthographic projection of the semiconductor pattern of the first transistor T1 on the substrate. In this way, the power line ELVDD can be prevented from being located directly above the semiconductor pattern of the first transistor T1, thereby preventing the coupling capacitance between the power line ELVDD and the first transistor T1 from being too large when writing the signal of the data line Data, so that the coupling between the power line ELVDD and the data signal transmitted by the first transistor T1 is small, which is beneficial to the display of the display panel.

[0095] like Figure 5 As shown, the distance W5 between the orthographic projection of the semiconductor pattern of the first electrode T31 of the third transistor T3 on the substrate and the orthographic projection of the first data line 111 on the substrate is greater than the distance W4 between the orthographic projection of the semiconductor pattern of the first electrode T31 of the third transistor T3 on the substrate and the orthographic projection of the second data line 112 on the substrate, that is, W5>W4.

[0096] The semiconductor pattern of the first electrode T31 of the third transistor T3 is extended to a position close to the second data line 112 along the first direction X. The orthographic projection of the semiconductor pattern of the first electrode T31 of the third transistor T3 on the substrate partially overlaps with the orthographic projection of the power line ELVDD on the substrate, so that the semiconductor pattern of the first electrode T31 of the third transistor T3 and the power line ELVDD can be electrically connected through a via hole on the insulating layer therebetween.

[0097] Continue to refer Figure 5, a distance W7 between an orthographic projection of the semiconductor pattern of the second electrode T32 of the third transistor T3 on the substrate and an orthographic projection of the second data line 112 on the substrate is greater than a distance W6 between an orthographic projection of the semiconductor pattern of the second electrode T32 of the third transistor T3 on the substrate and an orthographic projection of the first data line 111 on the substrate; that is, W7>W6.

[0098] For example, the length range of the distance W4 between the orthographic projection of the semiconductor pattern of the first electrode T31 of the third transistor T3 on the substrate and the orthographic projection of the second data line 112 on the substrate may be 1.2 μm-3 μm. Thus, by designing W4 within a reasonable range, it is possible to avoid the semiconductor pattern of the first electrode T31 of the third transistor T3 being too close to the second data line 112, thereby reducing the parasitic capacitance therebetween; it is also possible to avoid the semiconductor pattern of the first electrode T31 of the third transistor T3 being too far from the second data line 112, thereby preventing it from being easily connected to the power line ELVDD through a via.

[0099] like Figure 2 and Figure 5 As shown, the orthographic projection of the semiconductor pattern of the fourth transistor T4 on the substrate and the orthographic projection of the semiconductor pattern of the fifth transistor T5 on the substrate are respectively located on both sides of the orthographic projection of the semiconductor pattern of the third transistor T3 on the substrate.

[0100] Specifically, the semiconductor pattern of the first electrode T51 of the fifth transistor T5 and the semiconductor pattern of the first electrode T41 of the fourth transistor T4 are respectively located on both sides of the semiconductor pattern of the first electrode T31 of the third transistor T3, and are respectively arranged between the semiconductor pattern of the first electrode T31 of the third transistor T3. This is equivalent to the semiconductor pattern of the first electrode T41 of the fourth transistor T4 and the semiconductor pattern of the first electrode T51 of the fifth transistor T5 being in a disconnected state, thereby avoiding a short circuit between the semiconductor pattern of the fifth transistor T5, the semiconductor pattern of the fourth transistor T4, and the semiconductor pattern of the first electrode T31 of the third transistor T3.

[0101] like Figure 2 and Figure 5As shown, another connection line may be provided in the array substrate, which is a third connection line 133, one end of the third connection line 133 is electrically connected to the semiconductor pattern of the first pole T41 of the fourth transistor T4, and the other end of the third connection line 133 is electrically connected to the semiconductor pattern of the first pole T51 of the fifth transistor T5; so that the semiconductor pattern of the first pole T41 of the fourth transistor T4 is electrically connected to the semiconductor pattern of the first pole T51 of the fifth transistor T5 through the third connection line 133. The third connection line 133 and the semiconductor pattern layer 105 of the pixel circuit are located in different layers. Specifically, the third connection line 133 can be electrically connected to the semiconductor pattern of the first pole T41 of the fourth transistor T4 and the semiconductor pattern of the first pole T51 of the fifth transistor T5 through a via hole. In this way, the second reference line Vref2 can be transmitted to the anode after passing through the second pole T52 of the fifth transistor T5, the first pole T51 of the fifth transistor T5, the third connection line 133 and the first pole T41 of the fourth transistor T4 in sequence. The orthographic projection of the third connection line 133 on the substrate partially overlaps with the orthographic projection of the semiconductor pattern of the third transistor T3 on the substrate. The third connection line 133 crosses the semiconductor pattern of the first electrode T31 of the third transistor T3, so that the extension length of the third connection line 133 is shorter and the manufacturing process is simpler. For example, the third connection line 133 can be provided in the same layer and material as the power line ELVDD, thereby simplifying the manufacturing process of the array substrate.

[0102] like Figure 2 and Figure 5 As shown, the orthographic projection of the semiconductor pattern of the second electrode T62 of the sixth transistor T6 on the substrate is at least partially overlapped with the orthographic projection of the power line ELVDD on the substrate. Since the semiconductor pattern of the second electrode T62 of the sixth transistor T6 is located in the semiconductor pattern layer 105, the power line ELVDD is located in the third metal layer 103, and the second data line 112 is located in the fourth metal layer 104. Along the thickness direction of the array substrate, the semiconductor pattern of the sixth transistor T6 and the second data line 112 are located on opposite sides of the power line ELVDD. On the one hand, the distance between the semiconductor pattern of the sixth transistor T6 and the second data line 112 is large, which can reduce the parasitic capacitance between the semiconductor pattern of the sixth transistor T6 and the second data line 112, so as to reduce the crosstalk between the semiconductor pattern of the second electrode T62 of the sixth transistor T6 and the second data line 112 in the light emitting stage, thereby ensuring the display effect of the display panel. On the other hand, in the light emitting stage, the power line ELVDD can serve as a shielding layer to shield the signal between the semiconductor pattern of the second electrode T62 of the sixth transistor T6 and the second data line 112, thereby better reducing the signal interference between the semiconductor pattern of the second electrode T62 of the sixth transistor T6 and the second data line 112.

[0103] like Figure 2 and Figure 5As shown, the array substrate may include a fourth connection line 134, and the fourth connection line 134 is used to electrically connect the anode of the light-emitting unit and the semiconductor pattern of the first electrode T41 of the fourth transistor T4. In addition, the fourth connection line 134 is also used to electrically connect the third connection line 133 and the anode of the light-emitting unit, so that the semiconductor pattern of the first electrode T51 of the fifth transistor T5 is electrically connected to the anode of the light-emitting unit. For example, the fourth connection line 134 can be set in the same layer and the same material as the data line Data, so that the preparation process of the array substrate can be simplified.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: A substrate and a pixel circuit, a power line, a first data line and a second data line located on one side of the substrate, wherein the first data line and the second data line are arranged at intervals along a first direction, and the power line, the first data line and the second data line all extend in a second direction; The pixel circuit comprises a first transistor and a second transistor, an orthographic projection of a semiconductor pattern of the first transistor on the substrate is closer to an orthographic projection of the first data line on the substrate than an orthographic projection of the semiconductor pattern of the second transistor on the substrate, an orthographic projection of the semiconductor pattern of the second transistor on the substrate is closer to an orthographic projection of the second data line on the substrate than an orthographic projection of the semiconductor pattern of the first transistor on the substrate, and an orthographic projection of a semiconductor pattern of a first electrode of the second transistor on the substrate is located between orthographic projections of the first data line and the second data line on the substrate; The orthographic projection of the power line on the substrate passes through a region between the semiconductor pattern of the first electrode of the second transistor and the orthographic projection of the second data line on the substrate; wherein the first direction is different from the second direction; The pixel circuit further includes a driving transistor and a third transistor, wherein the third transistor is used to control the light emitting unit to emit light in the light emitting stage; The first electrode of the third transistor is electrically connected to the power line, the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, the distance between the orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and the orthographic projection of the first data line on the substrate is greater than the distance between the orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and the orthographic projection of the second data line on the substrate, and the distance between the orthographic projection of the semiconductor pattern of the second electrode of the third transistor on the substrate and the orthographic projection of the second data line on the substrate is greater than the distance between the orthographic projection of the semiconductor pattern of the second electrode of the third transistor on the substrate and the orthographic projection of the first data line on the substrate.

2. The array substrate according to claim 1, characterized in that: The power line comprises a first extension segment, the orthographic projection of the first extension segment on the substrate is located between the second data line and the orthographic projection of the semiconductor pattern of the first electrode of the second transistor on the substrate, and the distance between the orthographic projection of the semiconductor pattern of the first electrode of the second transistor on the substrate and the orthographic projection of the second data line on the substrate is greater than the maximum width of the first extension segment; A distance between the semiconductor pattern of the first electrode of the first transistor and the semiconductor pattern of the first electrode of the second transistor is smaller than a minimum width of the first extension segment.

3. The array substrate according to claim 1, characterized in that: The first transistor is used for data writing, a first electrode of the first transistor is electrically connected to the first data line or the second data line, and an orthographic projection of the power line on the substrate does not overlap with an orthographic projection of the semiconductor pattern of the first transistor on the substrate.

4. The array substrate according to claim 1, characterized in that: A distance between an orthographic projection of the semiconductor pattern of the first electrode of the third transistor on the substrate and an orthographic projection of the second data line on the substrate is in a range of 1.2 μm to 3 μm.

5. The array substrate according to claim 4, characterized in that: The pixel circuit includes a fourth transistor and a fifth transistor, the fourth transistor is used to control the light-emitting unit to emit light in the light-emitting stage, and the first electrode of the fourth transistor is electrically connected to the light-emitting unit, and the fifth transistor is used to reset the light-emitting unit; Orthographic projections of the semiconductor pattern of the fourth transistor and the semiconductor pattern of the fifth transistor on the substrate are respectively located on both sides of the orthographic projection of the semiconductor pattern of the third transistor on the substrate.

6. The array substrate according to claim 5, characterized in that: The semiconductor pattern of the first electrode of the fourth transistor is disconnected from the semiconductor pattern of the first electrode of the fifth transistor; The array substrate further includes a connection line, which is used to electrically connect the semiconductor pattern of the first electrode of the fourth transistor with the semiconductor pattern of the first electrode of the fifth transistor, and the connection line and the semiconductor pattern of the pixel circuit are located in different layers.

7. The array substrate according to any one of claims 1 to 6, characterized in that: There are multiple pixel circuits, and the multiple pixel circuits are arranged in the first direction and the second direction. In two adjacent pixel circuits in the second direction, the first electrode of the first transistor of one of the pixel circuits is electrically connected to the first data line, and the first electrode of the first transistor of the other pixel circuit is electrically connected to the second data line.

8. The array substrate according to claim 7, characterized in that: The first data line and the second data line are both provided with data connection ends, and are respectively electrically connected to the first electrode of the corresponding first transistor through the corresponding data connection ends. The data connection end is located between the first data line and the second data line, and the distance between the data connection end and the first data line is equal to the distance between the data connection end and the second data line.

9. The array substrate according to any one of claims 1 to 6, characterized in that: The pixel circuit includes a driving transistor and a sixth transistor, the sixth transistor is used to reset the gate of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the gate of the driving transistor; the orthographic projection of the power line on the substrate at least partially overlaps with the orthographic projection of the semiconductor pattern of the second electrode of the sixth transistor on the substrate; Along a thickness direction of the array substrate, the semiconductor pattern of the sixth transistor and the second data line are located on opposite sides of the power line.

10. A display panel, characterized in that: It comprises the array substrate described in any one of claims 1 to 9.

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