Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a substrate and discrete fins located on the substrate; forming an isolation structure on the substrate where the fins are exposed, the isolation structure covering the sidewalls of the fins; after forming the isolation structure, performing well implantation on the fins; after well implantation, etching back a portion of the isolation structure to expose a portion of the sidewalls of the fins; after etching back the isolation structure, performing a well implantation-followed annealing process on the fins. This reduces the probability of lattice damage forming dislocation defects during the annealing process, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and fins disposed on the substrate; forming an isolation structure on the substrate where the fins are exposed, the isolation structure covering the sidewalls of the fins; after forming the isolation structure, performing well region implantation on the fins; after performing the well region implantation, etching back a portion of the thickness of the isolation structure to expose a portion of the sidewalls of the fins; after etching back the portion of the thickness of the isolation structure, performing a well region implantation annealing process on the fins.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] This invention provides a method for forming a semiconductor structure, comprising forming an isolation structure on a substrate with exposed fins, the isolation structure covering the sidewalls of the fins; after forming the isolation structure, performing well implantation on the fins; after performing well implantation, etching back a portion of the isolation structure to expose a portion of the sidewalls of the fins; after etching back the isolation structure, performing a well implantation-induced annealing process on the fins. Fins are susceptible to lattice damage during well implantation. The formation of the isolation structure typically generates significant stress on the fins. Under these internal stresses, lattice damage in the fins can easily lead to dislocation defects during subsequent annealing after well implantation. Since the stress generated by the isolation structure is positively correlated with its volume, this embodiment of the invention reverses the process sequence. After well implantation of the fins, a portion of the isolation structure is etched back to reduce its volume. This reduces or eliminates the impact of internal stress on the exposed fins. Furthermore, during the subsequent annealing process after well implantation, the probability of dislocation defects forming in the fins is significantly reduced, thereby improving the electrical performance of the semiconductor structure.

[0008] In an optional embodiment, the well implantation has preset conditions, including one or both of heating the substrate during implantation and using a low ion beam current, wherein the low ion beam current is less than or equal to 200 μA. Under these preset conditions, the kinetic energy of the implanted ions and atoms in the fin material (e.g., silicon atoms) can be increased, causing attraction or repulsion between them. This allows the atoms in the crystal lattice to rearrange themselves neatly, thereby reducing the probability of lattice damage caused during well implantation. Subsequently, after etching back a portion of the isolation structure, the annealing process following well implantation significantly reduces the probability of lattice damage to the fins, leading to a substantial decrease in the probability of dislocation defects formed during annealing. This, in turn, improves the electrical performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] The electrical performance of semiconductor devices still needs improvement. This paper analyzes the reasons why the electrical performance of a semiconductor structure still needs to be improved, using an example of such a method.

[0011] The method for forming the semiconductor structure includes: providing a substrate, the substrate including a substrate and fins disposed on the substrate; forming an isolation structure on the substrate where the fins are exposed, the isolation structure covering the sidewalls of the fins; after forming the isolation structure, performing well implantation on the fins; after performing the well implantation, performing a well implantation annealing process on the fins; after performing the annealing process, etching back a portion of the thickness of the isolation structure to expose a portion of the sidewalls of the fins.

[0012] Specifically, fins are susceptible to lattice damage during well implantation. During the formation of the isolation structure, the isolation structure covers the entire sidewall of the fin. The isolation structure usually generates significant stress on the fin. In the presence of internal stress, lattice damage in the fin is prone to forming dislocation defects during the subsequent annealing process after well implantation, thereby reducing the electrical performance of the semiconductor device.

[0013] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and fins disposed on the substrate; forming an isolation structure on the substrate where the fins are exposed, the isolation structure covering the sidewalls of the fins; after forming the isolation structure, performing well region implantation on the fins; after performing the well region implantation, etching back a portion of the thickness of the isolation structure to expose a portion of the sidewalls of the fins; after etching back the portion of the thickness of the isolation structure, performing a well region implantation-followed annealing process on the fins.

[0014] In the formation method provided by the embodiments of the present invention, an isolation structure is formed on the substrate exposed by the fin, the isolation structure covering the sidewall of the fin; after forming the isolation structure, well implantation is performed on the fin; after the well implantation, a portion of the isolation structure is etched back to expose a portion of the sidewall of the fin; after the portion of the isolation structure is etched back, an annealing process following well implantation is performed on the fin. Fins are susceptible to lattice damage during well implantation. The formation of the isolation structure typically generates significant stress on the fins. Under these internal stresses, lattice damage in the fins can easily lead to dislocation defects during subsequent annealing after well implantation. Since the stress generated by the isolation structure is positively correlated with its volume, this embodiment of the invention reverses the process sequence. After well implantation of the fins, a portion of the isolation structure is etched back to reduce its volume. This reduces or eliminates the impact of internal stress on the exposed fins. Furthermore, during the subsequent annealing process after well implantation, the probability of dislocation defects forming in the fins is significantly reduced, thereby improving the electrical performance of the semiconductor structure.

[0015] In an optional embodiment, the well implantation has preset conditions, including one or both of heating the substrate during implantation and using a low ion beam current, wherein the low ion beam current is less than or equal to 200 μA. Under these preset conditions, the kinetic energy of the implanted ions and atoms in the fin material (e.g., silicon atoms) can be increased, causing attraction or repulsion between them. This allows the atoms in the crystal lattice to rearrange themselves neatly, thereby reducing the probability of lattice damage caused during well implantation. Subsequently, after etching back a portion of the isolation structure, the annealing process following well implantation significantly reduces the probability of lattice damage to the fins, leading to a substantial decrease in the probability of dislocation defects formed during annealing. This, in turn, improves the electrical performance of the semiconductor structure.

[0016] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0017] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0018] refer to Figure 1 A substrate is provided, the substrate including a substrate 100 and fins 101 disposed on the substrate 100.

[0019] The substrate is used to provide a process platform for subsequent process manufacturing.

[0020] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0021] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fins 101 on the substrate 100 are used to provide the channel of the fin field-effect transistor.

[0022] In this embodiment, the fin 101 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate.

[0023] Therefore, in this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin can also be a semiconductor material suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from the material of the substrate.

[0024] In this embodiment, the steps of forming the substrate 100 and the fin 101 include: providing an initial substrate (not shown); forming a fin mask layer 102 on the initial substrate; using the fin mask layer 102 as a mask, etching the initial substrate, and the remaining initial substrate after etching serves as the substrate 100, and the protrusions on the substrate 100 serve as the fin 101.

[0025] It should be noted that after forming the fin 101, a fin mask layer 102 is retained on top of the fin 101. The fin mask layer 102 is made of silicon nitride. During the subsequent formation of the isolation structure, the top surface of the fin mask layer 102 can be used to define the stop position of the planarization process, and the fin mask layer 102 also serves to protect the top of the fin 101. In other embodiments, the fin mask layer can also be made of silicon oxynitride.

[0026] In this embodiment, the fin mask layer 102 is formed through deposition, photolithography, and etching processes. In other embodiments, to reduce the feature size of the fins and decrease the pitch between adjacent fins, the fin mask layer can also be formed through a multiple patterning process. The multiple patterning mask process includes: Self-Aligned Double Patterned (SADP) process, Self-Aligned Triple Patterned (SATP) process, or Self-Aligned Double Double Patterned (SADDP) process, and Litho-Eth-Litho-Etch (LELE) process, etc.

[0027] refer to Figure 2 An isolation structure 104 is formed on the substrate 100 exposed by the fin 101, and the isolation structure 104 covers the sidewall of the fin 101.

[0028] The isolation structure 104 is used to isolate adjacent devices. The material of the isolation structure 104 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation structure 104 is silicon oxide.

[0029] In this embodiment, the step of forming the isolation structure 104 includes: forming an isolation material layer (not shown) on the substrate 100 exposed on the fin 101, the isolation material layer also covering the top surface of the fin mask layer 102; planarizing the isolation material layer with the top surface of the fin mask layer 102 as the stopping position; and the remaining isolation material layer serving as the isolation structure 104. Therefore, at this time, the isolation structure 104 covers the entire sidewall of the fin 101.

[0030] In this embodiment, the process for forming the isolation structure 104 includes fluid chemical vapor deposition.

[0031] The fluid chemical vapor deposition process features good deposition uniformity, high density, and high coverage, making it more suitable for filling gaps with high aspect ratios. In this embodiment, a flowable medium fills the grooves between adjacent fins, forming an isolation structure 104 between adjacent fins 101.

[0032] refer to Figure 3 Remove the fin mask layer 102 from the top of the fin 101.

[0033] By removing the fin mask layer 102 from the top of the fin 101, the top of the fin 101 is exposed, thereby providing a process basis for subsequent well injection of the fin 101.

[0034] Specifically, the step of removing the fin mask layer 102 on the top of the fin 101 includes: using the isolation structure 104 as a mask, etching away the fin mask layer 102.

[0035] In this embodiment, a wet etching process is used to etch and remove the fin mask layer 102.

[0036] Wet etching has isotropic etching characteristics, which is beneficial for increasing the etching rate of the fin mask layer 102 and for completely removing the fin mask layer 102 embedded in the isolation structure 104. In addition, wet etching makes it easy to achieve etching selectivity and provides good process controllability.

[0037] In this embodiment, the material of the fin mask layer 102 is silicon nitride, therefore, the etching solution of the wet etching process is a hot phosphoric acid solution.

[0038] refer to Figure 4 After the isolation structure 104 is formed, the fin 101 is injected into the trap region.

[0039] It should be noted that the fin 101 is susceptible to lattice damage during the well region implantation process. During the formation of the isolation structure 104, the fin 101 is usually subjected to large stress. Furthermore, the annealing process after well region implantation is required. Under the presence of internal stress, the lattice damage in the fin 101 is prone to forming dislocation defects during the subsequent annealing process after well region implantation.

[0040] It should also be noted that, in other embodiments, the well implantation has preset conditions, which include one or both of heating the substrate during the implantation process and a low ion beam current, wherein the low ion beam current is less than or equal to 200 μA.

[0041] During the well implantation process under the preset conditions, the kinetic energy of the implanted ions and silicon atoms can be increased, causing the implanted ions and silicon atoms to generate attraction or repulsion between each other. This allows the atoms in the crystal lattice to rearrange themselves neatly, thereby reducing the probability of lattice damage caused during the well implantation process. Subsequently, after etching back a portion of the isolation structure, when performing the annealing process after well implantation on the fin, the probability of the fin being damaged by the lattice is reduced, and the probability of the lattice damage forming dislocation defects in the subsequent annealing process is also greatly reduced, which is beneficial to improving the electrical performance of the semiconductor structure.

[0042] When the semiconductor structure is an N-type transistor, the implanted ion type during well region implantation of the fin is P-type. In other embodiments, when the semiconductor structure is a P-type transistor, the implanted ion type during well region implantation of the fin is N-type.

[0043] It should be noted that the sidewalls of the adjacent fins are covered with an isolation structure. During the process of well region implantation of the fins, the isolation structure can protect the top of the substrate and reduce the probability of lattice damage to the substrate.

[0044] It should also be noted that during the process of well injection into the fin, the well injection is subject to preset conditions, which include one or both of heating the substrate and using a low ion beam current during the injection process.

[0045] Taking heating the substrate as a preset condition for well implantation as an example, that is, the well implantation process is hot implantation.

[0046] By heating the substrate during the implantation process, the kinetic energy of the implanted ions and silicon atoms can be increased, causing the implanted ions and silicon atoms to generate attraction or repulsion between each other. This allows the atoms in the lattice to rearrange themselves neatly, thereby reducing the probability of lattice damage caused during the well region implantation process. The probability of forming dislocation defects in the subsequent annealing process is also greatly reduced.

[0047] The temperature at which the substrate is heated is between 50°C and 500°C.

[0048] It should be noted that the heating temperature of the substrate should not be too high or too low. If the heating temperature is too high, the diffusion area of ​​the implanted ions in the substrate may be too large, failing to meet process requirements. If the heating temperature is too low, the repair effect of lattice damage generated in the fins during well implantation may be poor, thus increasing the probability of dislocation defects in the subsequent annealing process. Therefore, the heating temperature of the substrate is between 50°C and 500°C. For example, the heating temperature of the substrate is 100°C, 200°C, or 300°C.

[0049] In other embodiments, the process of well implantation into the fin may also include well implantation using a low ion beam current less than or equal to 200 μA.

[0050] Using a low ion beam current for well implantation can increase the kinetic energy of the implanted ions and silicon atoms, causing them to attract or repel each other. This allows the atoms in the lattice to rearrange themselves neatly, thereby reducing the probability of lattice damage during well implantation and significantly reducing the probability of dislocation defects forming during subsequent annealing processes.

[0051] It should be noted that the low ion beam current should not be too high or too low. If the low ion beam current is too high, the probability of lattice damage to the fins will increase; if the low ion beam current is too low, the efficiency of the well implantation process will be too low, failing to effectively repair lattice damage, and also increasing process time and cost. Therefore, in this embodiment, the ion beam current is between 20 μA and 200 μA.

[0052] refer to Figure 5 After the well region is injected, the isolation structure 104 of a certain thickness is etched back to expose part of the sidewall of the fin 101.

[0053] Specifically, the fin 101 is susceptible to lattice damage during well implantation. During the formation of the isolation structure 104, the fin 101 is usually subjected to significant stress. In the presence of internal stress, the lattice damage in the fin 101 is prone to forming dislocation defects in the subsequent annealing process after well implantation. Since the stress generated by the isolation structure 104 is positively correlated with its volume, this embodiment reduces the volume of the isolation structure 104 by reversing the process steps and etching back a portion of the thickness of the isolation structure 104 first. This reduces or eliminates the influence of the internal stress of the isolation structure 104 on the exposed fin 101. In the subsequent annealing process after well implantation, the probability of dislocation defects forming in the fin 101 is also greatly reduced, thereby improving the electrical performance of the semiconductor structure.

[0054] In this embodiment, the process for etching back the thickness of the isolation structure 104 includes a dry etching process.

[0055] The dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic dry etching, so its longitudinal etching rate is much greater than its transverse etching rate. This is beneficial for accurately controlling the reduction in thickness of the isolation structure 104, and also beneficial for improving the top morphology of the remaining isolation structure 104. It also causes less damage to the sidewalls of the fin 101.

[0056] refer to Figures 6 to 7 Annealing process 200 is performed on the fin 101 after well injection.

[0057] Since the implanted ions can easily damage the fin 101 after trap implantation, and most of the implanted ions are not located at lattice sites in a substitute form, an annealing process 200 at an appropriate temperature can repair the lattice damage in the fin 101 and also move the implanted ions to lattice sites, thereby enhancing the activity of the implanted ions and activating them.

[0058] In this embodiment, after etching back the thickness of the isolation structure 104, the annealing process 200 after well implantation is performed.

[0059] Since the stress generated by the isolation structure 104 is positively correlated with its volume, by first etching back a portion of the thickness of the isolation structure 104, the volume of the isolation structure 104 can be reduced, thereby reducing or eliminating the influence of the stress inside the isolation structure 104 on the exposed fin 101. During the annealing process 200 after well region implantation on the fin 101, the probability of dislocation defects forming in the fin 101 is also greatly reduced.

[0060] The annealing process 200 after well injection includes one or more of the following: uniform temperature annealing, peak annealing, millisecond-level annealing, and rapid thermal annealing.

[0061] The rapid thermal annealing (RTA) process refers to rapidly heating to the target temperature and then achieving annealing in a very short time. RTA minimizes diffusion effects and allows for excellent control over the size of the ion implantation diffusion region. As an example, the annealing process 200 after well implantation is a rapid thermal annealing process.

[0062] In this embodiment, the parameters of the annealing process 200 after the well injection include: the reaction gas includes one or more of N2, H2, NH3, O2 and Ar; the process temperature is 500℃ to 1400℃; the process time is 0.1us to 60s; and the chamber pressure is 0.001torr to 780torr.

[0063] It should be noted that the process temperature should not be too high or too low. If the process temperature is too high, the depth of longitudinal diffusion of implanted ions will increase, which may lead to the implanted well region not meeting process requirements, thus affecting the electrical performance of the semiconductor. If the process temperature is too low, the diffusion area of ​​implanted ions in the fin may be too small, which may also lead to the implanted well region not meeting process requirements. Furthermore, it may result in poor repair of lattice damage in the fin, further affecting the electrical performance of the semiconductor. Therefore, in this embodiment, the process temperature is between 500°C and 1400°C.

[0064] It should be noted that the process time should not be too long or too short. If the process time is too long, the diffusion area of ​​the dopant ions implanted in the well region will be too large, failing to meet the process requirements and affecting device performance. If the process time is too short, the activation efficiency of the dopant ions will be too low, affecting both the process time and process efficiency, thereby increasing the production cost of the process. Therefore, in this embodiment, the process time is 0.1 μs to 60 s.

[0065] It should be noted that the chamber pressure should not be too high or too low. If the chamber pressure is too high, it may cause safety issues for the equipment during the annealing process; if the chamber pressure is too low, it may lead to low activation efficiency of the doped ions, affecting process time and efficiency, thereby increasing the production cost of the process. Therefore, in this embodiment, the chamber pressure is between 0.001 torr and 780 torr.

[0066] refer to Figure 6After etching back a portion of the thickness of the isolation structure 104 and before performing the annealing process 200 after well implantation, the formation method further includes forming a protective layer 105 on the sidewalls and top of the fin 101 exposed by the remaining isolation structure 104.

[0067] In the annealing process 200 after well implantation, the material on the surface of the fin 101 is highly likely to be oxidized. For example, since the fin 101 contains silicon atoms, the material on the surface of the fin 101 is easily oxidized to silicon oxide, which reduces the volume of the fin 101 and affects its structural strength and reliability. Therefore, before performing the annealing process 200 after well implantation, a protective layer 105 is formed on the sidewalls and top of the fin 101 exposed by the remaining isolation structure 104 using a deposition process. The protective layer 105 protects the fin 101 exposed by the substrate 100 during the annealing process 200, reducing the probability of damage to the fin. Moreover, the protective layer 105 is formed by a deposition process, which consumes less material in the fin 101, thus reducing the impact on the linewidth and volume of the fin 101.

[0068] In this embodiment, the deposition process for forming the protective layer 105 includes atomic layer deposition.

[0069] The atomic layer deposition process includes multiple atomic layer deposition cycles, which helps improve the thickness uniformity of the protective layer 105 and allows the protective layer 105 to cover the sidewalls of the fin 101. In other embodiments, the protective layer can also be formed using chemical vapor deposition (CVD).

[0070] In other embodiments, instead of forming a protective layer, a passivating gas may be used to passivate the surface of the fins exposed by the remaining isolation structure, thereby forming a protective layer on the sidewalls and top of the fins exposed by the remaining isolation structure.

[0071] By performing surface passivation treatment on the fins exposed by the remaining isolation structure, a protective layer is formed on the surface of the fins, thereby protecting the fins exposed to the substrate during the annealing process after the well region implantation, and reducing the probability of the fins being damaged.

[0072] Specifically, in this embodiment, the passivation gas is an oxygen-containing gas, the surface passivation treatment is an oxidation treatment, and the protective layer formed after the surface passivation treatment is an oxide layer. That is, the exposed fin portion of the remaining isolation structure undergoes surface passivation treatment, causing the passivation gas to react with the material of the fin portion, forming a conformal oxide layer (e.g., a silicon oxide layer) covering the fin portion on its surface. This provides protection for the fin portion in subsequent related manufacturing processes.

[0073] The passivating gas includes one or more of O2, N2O and H2O.

[0074] Specifically, O2, N2O and H2O are all oxygen-containing gases. During the annealing process, oxygen atoms react with silicon atoms in the fins at high temperatures to form silicon oxide on the surface of the fins, which protects the fins.

[0075] In the step of performing the surface passivation treatment on the exposed fins of the remaining isolation structure, the surface passivation treatment temperature is 500°C to 1200°C.

[0076] The surface passivation temperature should not be too high or too low. If the surface passivation temperature is too high, the oxide layer formed on the fin surface will be too thick, affecting the subsequent fabrication process of the metal gate structure. If the surface passivation temperature is too low, the oxide layer formed on the fin surface will be too thin, reducing the protective effect on the fin and thus affecting the performance of the semiconductor structure. Therefore, in the step of performing the surface passivation treatment on the remaining exposed fins of the isolation structure, the surface passivation temperature is between 500°C and 1200°C.

[0077] In the step of performing the surface passivation treatment on the exposed fins of the remaining isolation structure, the content of the passivation gas used is greater than 10 ppm.

[0078] The content of the passivation gas used should not be too low. If the content of the oxygen-containing gas used is too low, the oxide layer formed on the surface of the fin will be too thin. This will increase the probability of silicon atoms migrating in the fin during subsequent manufacturing processes, thereby creating defects in the fin and affecting the performance of the semiconductor structure.

[0079] It should be noted that in this embodiment, a scheme was adopted to change the process sequence between the etched isolation structure and the annealing process after well implantation.

[0080] The solution adopted in this embodiment can significantly reduce the probability of dislocation defects forming in the semiconductor device and improve the electrical performance of the semiconductor device.

[0081] In other embodiments, the process can also involve: after forming the isolation structure, performing well implantation on the fin, the well implantation having preset conditions; after performing well implantation, etching back a portion of the isolation structure to expose part of the sidewall of the fin; after etching back a portion of the isolation structure, performing an annealing process following well implantation. The fin is susceptible to lattice damage during well implantation. During the formation of the isolation structure, significant stress is typically generated on the fin. In the presence of internal stress, lattice damage in the fin is prone to forming dislocation defects during the subsequent annealing process following well implantation. Since the stress generated by the isolation structure is positively correlated with its volume, by changing the process sequence, after well implantation of the fin, etching back a portion of the isolation structure first reduces the volume of the isolation structure, thereby reducing or eliminating the influence of the internal stress on the exposed fin from the isolation structure. Then, when performing the annealing process following well implantation, the probability of dislocation defects forming in the fin can also be reduced.

[0082] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and fins disposed on the substrate, wherein a fin mask layer is formed on the top of the fins; An isolation structure is formed on the substrate exposed by the fin, the isolation structure covering the sidewalls of the fin and the fin mask layer; Remove the fin mask layer at the top of the fin; After removing the fin mask layer, the fin is then injected into the trap region. After the well region is injected, the isolation structure is etched back to a certain thickness to expose part of the sidewall of the fin. A protective layer is formed on the sidewalls and top of the fins exposed in the remaining isolation structure; After the protective layer is formed, the fin is subjected to an annealing process following trap injection.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The well implantation has preset conditions, which include one or both of heating the substrate during the implantation process and a low ion beam current, wherein the low ion beam current is less than or equal to 200 μA.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the protective layer after etching back a portion of the isolation structure and before performing the annealing process following the well implantation includes: using a deposition process to form a protective layer on the sidewalls and top of the remaining exposed fins of the isolation structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, After etching back a portion of the isolation structure and before performing the annealing process following the well implantation, the step of forming the protective layer includes: using a passivating gas to perform surface passivation treatment on the fins exposed by the remaining isolation structure, and forming a protective layer on the sidewalls and top of the fins exposed by the remaining isolation structure.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The annealing process after well injection includes one or more of the following: uniform temperature annealing, peak annealing, millisecond-level annealing, and rapid thermal annealing.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The parameters of the annealing process after the well injection include: the reaction gas includes one or more of N2, H2, NH3, O2 and Ar; the process temperature is 500℃ to 1400℃; the process time is 0.1us to 60s; and the chamber pressure is 0.001torr to 780torr.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, The deposition process for forming the protective layer includes atomic layer deposition (ALD).

8. The method for forming a semiconductor structure as described in claim 4, characterized in that, The passivating gas is an oxygen-containing gas.

9. The method for forming a semiconductor structure as described in claim 4 or 8, characterized in that, The passivating gas includes one or more of O2, N2O and H2O.

10. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the step of performing the surface passivation treatment on the exposed fins of the remaining isolation structure, the surface passivation treatment temperature is 600°C to 1200°C.

11. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the step of performing the surface passivation treatment on the exposed fins of the remaining isolation structure, the content of the passivation gas used is greater than 10 ppm.

12. The method for forming a semiconductor structure as described in claim 2, characterized in that, The temperature at which the substrate is heated is between 50°C and 500°C.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, The low ion beam current has a current value of 20 μA to 200 μA.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the isolation structure includes fluid chemical vapor deposition.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for etching back the thickness of the isolation structure includes a dry etching process.

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