Insulated gate bipolar transistor device and method of manufacturing the same

Abstract

The present disclosure relates to an insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof. The IGBT device according to the present disclosure includes a substrate of a first conductivity type, and a plurality of trenches formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction and in which a plurality of gates are respectively disposed. An active region is formed between the trenches, and the active region has a source region of the first conductivity type extending in the first direction and a contact region of a second conductivity type having a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width being alternately arranged in the first direction, and the trench has a uniform third width in the second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductors, and in particular, the present disclosure relates to a trench type insulated gate bipolar transistor device and a method of manufacturing the same. BACKGROUND

[0002] An insulated gate bipolar transistor (IGBT) is a voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and a metal oxide semiconductor field effect transistor (MOSFET), which has both high input impedance of the MOSFET and low on-voltage of the BJT, and is widely used in rail transportation, smart grid, aerospace, electric vehicles, new energy equipment, and the like.

[0003] Currently, the purpose of the research on the IGBT is mainly to improve the power density and switching speed of the IGBT and to reduce the power consumption of the IGBT. For this purpose, a trench type IGBT device is proposed in the prior art, which converts the current channel direction in the IGBT from the lateral direction on the device surface to the vertical direction in the device body by adjusting the gate from the horizontal direction to the vertical direction, so that the junction field effect transistor (JFET) effect in the IGBT can be eliminated, and the channel density and the near-surface carrier concentration can be increased, thereby greatly reducing the collector-emitter (source) on-voltage (Vceon) without increasing the off-loss.

[0004] However, for the trench type IGBT, the high channel density and the low on-voltage Vceon resulting therefrom increase the saturation current, which can adversely affect the short circuit performance of the IGBT. Therefore, it is usually necessary to use a dummy area of a pseudo gate and / or a pseudo well when performing layout design to balance the trade-off between the short circuit current and the on-loss. However, this increases the complexity of the layout design and increases the manufacturing cost. SUMMARY

[0005] A brief summary of the present disclosure is presented in the following to provide a basic understanding of some aspects of the present disclosure. However, it should be understood that this summary is not an exhaustive overview of the present disclosure, nor is it intended to identify key or critical elements of the present disclosure or to delineate the scope of the present disclosure. The purpose of this summary is merely to present some of the inventive concepts of the present disclosure in a simplified form as a prelude to the more detailed description to be given later.

[0006] An object of the present disclosure is to provide a trench type insulated gate bipolar transistor (IGBT) device and a method of manufacturing the same, which can overcome the above-mentioned problems existing in the prior art.

[0007] According to an aspect of the disclosure, there is provided an insulated gate bipolar transistor device including a substrate of a first conductivity type; and a plurality of trenches formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction and in which a plurality of gates are respectively disposed, wherein an active region is formed between the trenches, and the active region has a source region of the first conductivity type and a contact region of a second conductivity type extending in the first direction, wherein the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width are alternately arranged in the first direction, and the gate has a uniform third width in the second direction.

[0008] According to another aspect of the disclosure, there is provided an insulated gate bipolar transistor device including a substrate of a first conductivity type; and a plurality of trenches formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction and in which a plurality of gates are respectively disposed, wherein an active region is formed between the trenches, and the active region has a source region of the first conductivity type and a contact region of a second conductivity type extending in the first direction, wherein the gate has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width are alternately arranged in the first direction, and the contact region has a uniform third width in the second direction.

[0009] According to still another aspect of the disclosure, there is provided a method of manufacturing an insulated gate bipolar transistor device including forming a plurality of trenches downward from an upper surface of a substrate of a first conductivity type such that the plurality of trenches have a strip shape parallel to each other extending in a first direction; respectively disposing a plurality of gates in the plurality of trenches; and forming a source region of the first conductivity type and a contact region of a second conductivity type in each of an active region formed between the trenches using a same mask such that the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width are alternately arranged in the first direction.

[0010] The trench type IGBT device according to the disclosure does not require a complex layout design and can be manufactured in a simplified conventional semiconductor process step, thereby enabling reduction of manufacturing costs. Meanwhile, the trench type IGBT device according to the disclosure can reduce a saturation current, thereby improving short circuit performance. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

[0012] Figure 1A A plan view of a trench-type IGBT device according to the first embodiment of the present disclosure is shown;

[0013] Figure 1B A perspective view of a trench-type IGBT device according to the first embodiment of the present disclosure is shown;

[0014] Figure 2 A cross-sectional perspective view of a trench-type IGBT device according to the first embodiment of the present disclosure taken along the line AA' of Figure 1A

[0015] Figure 3 A cross-sectional perspective view of a trench-type IGBT device according to the first embodiment of the present disclosure taken along the line BB' of Figure 1A

[0016] Figure 4 An I-V characteristic curve of a trench-type IGBT device according to the first embodiment of the present disclosure is shown;

[0017] Figure 5 A curve of saturation current of a trench-type IGBT device according to the first embodiment of the present disclosure is shown;

[0018] Figure 6 A plan view of a trench-type IGBT device according to the second embodiment of the present disclosure is shown;

[0019] Figure 7 A cross-sectional perspective view of a trench-type IGBT device according to the second embodiment of the present disclosure taken along the line CC' of Figure 6

[0020] A cross-sectional perspective view of a trench-type IGBT device according to the second embodiment of the present disclosure taken along the line DD' of Figure 8 Figure 6 DETAILED DESCRIPTION

[0021] In this specification, it will also be understood that when a part (or region, layer, portion, etc.) is referred to as being on (or positioned on, directly on, disposed on, connected to, coupled to, etc.) another part (or region, layer, portion, etc.), it can be directly on the other part (or region, layer, portion, etc.), or intervening third parts (or regions, layers, portions, etc.) can also be present. In contrast, when an element (or region, layer, portion, etc.) is referred to as being "directly" on, "directly connected to", or "directly coupled to" another element (or region, layer, portion, etc.), there are no intervening elements present.

[0022] ​​​​The present disclosure will now be described more fully with reference to the accompanying drawings, in which various embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout. Furthermore, in the drawings, the thickness of components, ratios, and dimensions are exaggerated for clarity.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms "a," "an," and "the" are not intended to refer to only a singular entity but include the general class of which a specific one can be an example. For example, a reference to "an element" is a reference to one or more elements and can include a combination of one or more elements. As used herein, the term "or" means "and / or" unless clearly indicated otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] It will be understood that, although the terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0025] Furthermore, "below," "lower," "above," "upper," and the like are used for explanation only and are not otherwise limiting. These terms are relative concepts and are described based on the orientation presented in the drawings.

[0026] "About" or "approximately," as used herein, includes the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean an average within one or more standard deviations, or an average within ± 30%, 20%, 10%, 5% of the stated value.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] The meaning of "including" or "comprising" indicates the presence of the stated feature, number, step, operation, element, component, or a combination thereof, but does not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0029] Embodiments are described herein with reference to cross-sectional, perspective views that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected to occur. Thus, embodiments described herein are not to be construed as limited to the precise shapes illustrated but are to include deviations in shapes that result from, for example, manufacturing. For example, a region illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, illustrated sharp angles can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0030] Hereinafter, exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

[0031] Figure 6 A plan view of a trench IGBT device 10 according to a first embodiment of the present disclosure is shown. Figure 1A A perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure is shown. Figure 1B A cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure taken along a line AA' of Figure 2 A cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure taken along a line BB' of Figure 1A A cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure taken along a line BB' of Figure 3 A cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure taken along a line BB' of

[0032] Referring to Figure 1A The trench IGBT device 10 according to the first embodiment of the present disclosure can include a substrate 3 of a first conductivity type and a plurality of trenches 4. The plurality of trenches 4 are formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending along a first direction DR1 and in which a plurality of gates G are respectively provided. A source region 7 of the first conductivity type and a contact region 8 of a second conductivity type extending along the first direction DR1 are formed between the plurality of trenches 4 and have a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WC2 different from the first width WC1, the first width WC1 and the second width WC2 being alternately arranged along the first direction DR1. Each of the plurality of gates G has a uniform third width WG3 in the second direction DR2.

[0033] It will be understood by those skilled in the art that, although the first embodiment of the present disclosure is described herein with the first conductivity type being N-type and the second conductivity type being P-type as an example, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0034] Further, it will be understood by those skilled in the art that the term "heavily doped region" herein generally refers to a region with a doping concentration greater than or equal to 10 18 cm -3 and is denoted by the symbol "+". Further, the term "lightly doped region" herein refers to a region with a doping concentration less than 10 18 cm -3 and is denoted by the symbol "-". For example, "n+" denotes an n-type region with a doping concentration greater than or equal to 10 18 cm -3 , "n-" denotes an n-type region with a doping concentration less than 10 18 cm -3

[0035] Specifically, as shown in Figures 1A to 3 , the trench IGBT device 10 according to the first embodiment of the present disclosure includes first cells 10A and second cells 10B alternately arranged along a first direction DR1. As shown in Figure 1A , the gate G in the first cell 10A and the gate G in the second cell 10B have a uniform third width WG3 in a second direction DR2. Further, as shown in Figure 1A , according to the first embodiment of the present disclosure, a first width WC1 of the p+ contact region in the first cell 10A in the second direction DR2 can be less than a second width WC2 of the p+ contact region in the second cell 10B in the second direction DR2.

[0036] Referring to Figure 1A and Figure 2 , Figure 3 shows a cross-sectional perspective view of the first cell 10A of the trench IGBT device 10, while Figure 2 shows a cross-sectional perspective view of the second cell 10B of the trench IGBT device 10.

[0037] As shown in Figure 3 and Figure 2 ​As shown in the figure, the trench IGBT device 10 according to the first embodiment of the present disclosure has vertical trenches 4 arranged along the first direction DR1, and a gate G arranged in the trenches 4. According to the embodiments of the present disclosure, the trenches 4 can be formed by an etching process. In addition, an oxide layer (e.g., a silicon oxide layer) can be formed on the inner surface of the trenches 4 as a dielectric layer by, but not limited to, a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process.

[0038] According to the embodiments of the present disclosure, the gate G can be formed in the trenches 4 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the gate G can include, but is not limited to, doped polysilicon.

[0039] In the trench IGBT device 10 according to the first embodiment of the present disclosure, since the channel is changed from a lateral direction to a vertical direction by using the vertical gate G, the cell size can be reduced to increase the cell density, so that the total width of the channel of the IGBT device can be increased and the channel resistance can be reduced. On the other hand, the area of the polysilicon gate in the trench gate is increased, so that the distributed resistance can be reduced, which is beneficial to improve the switching speed.

[0040] Referring to Figure 3 and Figure 2 , the trench IGBT device 10 according to the first embodiment of the present disclosure has an active region formed between the trenches 4, and the active region can include, from the bottom to the top, a p+ type collector layer 1, an n+ type buffer layer 2, an n- type semiconductor substrate 3, a p- type channel layer 5, an n- type carrier blocking layer 6, an n+ type source (emitter) region 7, and a p+ type contact region 8.

[0041] Although not shown in the figure, in the first embodiment of the present disclosure, the trench IGBT device 10 can further include a collector metal layer arranged on and in electrical contact with the p+ type collector layer 1. In addition, the trench IGBT device 10 can further include a source metal layer arranged on and in electrical contact with the n+ type source region 7 and the p+ type contact region 8. In addition, the trench IGBT device 10 can further include a gate electrode which can be in electrical contact with the vertical gate in the trench 4 in a via manner.

[0042] According to the embodiments of the present disclosure, the p+ type collector layer 1 can be used as a hole injection layer which forms a forward biased PN junction with the n+ type buffer layer 2 to increase the hole injection effect. In addition, according to the embodiments of the present disclosure, the n+ type buffer layer 2 can be used as an electric field stop layer for generating electrons which recombine with the holes injected from the p+ type collector layer 1 when the IGBT is turned off, thereby improving the turn-off speed.

[0043] According to embodiments of the present disclosure, the n-type semiconductor substrate 3 can be a substrate with high resistivity. For example, the n-type semiconductor substrate 3 can be a FZ wafer or a MCZ wafer. Further, according to embodiments of the present disclosure, the n-type semiconductor substrate 3 can also include, but is not limited to, a silicon substrate, a silicon carbide, a gallium nitride substrate, or a germanium silicon substrate.

[0044] According to embodiments of the present disclosure, the p-type channel layer 5, the n-type carrier barrier layer 6, and the n+ type source region 7 can be formed between the trenches 4 so as to be in contact with the sidewalls of the trenches 4. According to embodiments of the present disclosure, the p-type channel layer 5 is formed on the n-type carrier barrier layer 6, and the n+ type source region 7 is formed on the p-type channel layer 5.

[0045] According to embodiments of the present disclosure, the n-type carrier barrier layer 6 has a depth in the vertical direction that is less than the depth of the vertical trench 4. In other words, in the vertical direction, the lower surface of the n-type carrier barrier layer 6 can be higher than the lower surface of the trench 4.

[0046] According to embodiments of the present disclosure, the p+ type contact region 8 is formed by ion implantation after etching the trench. In this way, the formation of the p+ type contact region 8 does not require the use of an additional mask, while the p+ contact region 8 of the deep trench can effectively improve the anti-latch-up capability of the trench IGBT device.

[0047] According to embodiments of the present disclosure, the p+ type contact region 8 can also be formed in the n+ type source region 7 by, for example, an ion implantation process. The implantation depth of the p+ type contact region 8 can be controlled by the ion implantation energy, in other words, the greater the implantation depth of the p+ type contact region 8, the greater the required ion implantation energy. Those skilled in the art will recognize that the implantation depth of the p+ type contact region 8 should not exceed the depth of the p-type channel layer 5.

[0048] According to embodiments of the present disclosure, the p+ type contact region 8 can have a depth in the vertical direction that is greater than the depth of the n+ type source region 7. In other words, in the vertical direction, the lower surface of the p+ type contact region 8 can be lower than the lower surface of the n+ type source region 7, but not lower than the lower surface of the p-type channel layer 5.

[0049] The IGBT structure formed according to the above embodiments of the present disclosure can be referred to as a carrier storage trench type IGBT, in which the n-type carrier blocking layer 6 formed below the p-type channel layer 5 can be used to store carriers. In a conventional trench type IGBT device, the hole density decreases with the distance from the source (emitter). However, in the trench type IGBT device formed according to the above embodiments of the present disclosure, a high hole density can still be maintained at the source side, which can reduce the on-voltage (i.e., Vceon) without increasing the off-loss.

[0050] Further, in the IGBT structure formed according to the above embodiments of the present disclosure, due to the layout of the n+ type source region 7 and the p+ type contact region 8, the latch-up effect of the parasitic NPNP thyristor formed by the n+ type source region 7, the p-type channel layer 5, the n-type semiconductor substrate 3, and the p+ type collector layer 1 can also be greatly eliminated.

[0051] Further, as shown in FIG. 1, the first and second cells 10A and 10B having different widths of the p+ type contact region 8 are alternately arranged along the first direction DR1. The trench type IGBT devices are formed in the first and second cells 10A and 10B, respectively. Figure 3

[0052] As described above, the second width WC2 of the P+ contact region 8 in the second cell 10B can be greater than the first width WC1 of the P+ contact region 8 in the first cell 10A. That is, in the second cell 10B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 μm to about 0.5 μm, so that the channel doping concentration of the IGBT device in the second cell 10B is greater than 1015cm-2. 18 cm -3 Therefore, the IGBT device in the second cell 10B is always off. In contrast, in the first cell 10A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 μm, so that the trench type IGBT device in the first cell 10A can operate normally.

[0053] ​That is, the trench IGBT device according to the first embodiment of the present disclosure has a cell arrangement of normal IGBT devices and always-off IGBT devices that are arranged in parallel with each other in alternation. Therefore, the trench IGBT device according to the first embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics. Further, since the IGBT devices in the second cell 10B are always-off, the gates in the IGBT devices in the second cell 10B can be regarded as dummy gates, so that gate charge (Qg) can also be reduced. Therefore, in the trench IGBT device according to the first embodiment of the present disclosure, there is no need to additionally add dummy regions for balancing the trade-off between short-circuit current and on-state loss, so that it is possible to simplify the manufacturing process and reduce the chip area.

[0054] According to the first embodiment of the present disclosure, by adjusting the proportional relationship between the first width WC1 of the p+ type contact region 8 in the first cell 10A and the fourth width WE4 of the n+ type source region 7 along the second direction DR2, it is possible to adjust the I-V characteristics of the trench IGBT device.

[0055] Figure 1A An I-V characteristic curve of the trench IGBT device according to the first embodiment of the present disclosure is shown. Figure 4 A curve of the saturation current of the trench IGBT device according to the first embodiment of the present disclosure is shown.

[0056] As Figure 5 and Figure 4 As shown in the first embodiment of the present disclosure, by changing the proportional relationship between the first width WC1 and the fourth width WE4, it is possible to adjust the I-V characteristics of the trench IGBT device.

[0057] According to the first embodiment of the present disclosure, the lengths of the first cell 10A and the second cell 10B along the first direction DR1 can be the same. According to the first embodiment of the present disclosure, the lengths of the first cell 10A and the second cell 10B along the first direction DR1 can be different. In the case where the lengths of the first cell 10A and the second cell 10B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 10A and the second cell 10B along the first direction DR1, it is also possible to adjust the I-V characteristics of the trench IGBT device.

[0058] A method for manufacturing a trench-type IGBT device 10 according to a first embodiment of the present disclosure may include the following steps: forming a plurality of trenches 4 downward from an upper surface of a first conductive type substrate 3 so that the plurality of trenches 4 have a strip shape parallel to each other extending along a first direction DR1; respectively arranging a plurality of gates G in the plurality of trenches 4; and forming a first conductive type source region 7 and a second conductive type contact region 8 in each of the active regions formed between the trenches 4 using the same mask, so that the contact region 8 has a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WC2 different from the first width WC1, and the first width WC1 and the second width WC2 are alternately arranged along the first direction DR1.

[0059] For example, a trench IGBT device can be manufactured on an n-type semiconductor substrate 3, such as an FZ wafer or an MCZ wafer. First, a plurality of trenches 4 extending along a first direction DR1 are formed on the upper surface of the n-type semiconductor substrate 3, for example, by etching. Subsequently, a plurality of gates G are formed in the plurality of trenches 4, for example, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The plurality of gates G have a uniform third width WG3 along a second direction DR2. Subsequently, an n-type carrier blocking layer 6, a p-type channel layer 5, an n+-type source region 7, and a p+-type contact region 8 are sequentially formed on the upper surface of the n-type semiconductor substrate 3 between the plurality of trenches 4, by high-energy ion implantation. The n+-type source region 7 and the p+-type contact region 8 can be formed using the same mask, thereby simplifying the process steps. Finally, an n+ type buffer layer 2 and a p+ type collector layer 1 are formed on the lower surface of the n-type semiconductor substrate 3 by high-energy ion implantation and low-energy ion implantation, respectively, to complete the trench IGBT device, wherein the n+ type buffer layer can be implanted in the form of multiple ions, such as protons, phosphorus, etc.

[0060] The number of cells in the trench IGBT device according to the first embodiment of the present disclosure can be adjusted according to the application scenario and applicable scope.

[0061] Figure 5 A plan view of a trench-type IGBT device 20 according to a second embodiment of the present disclosure is shown. Figure 6 Shown along Figure 7 A cross-sectional perspective view of a trench IGBT device 20 according to a second embodiment of the present disclosure, taken along line CC′. Figure 6 Shown along Figure 8 A cross-sectional perspective view of a trench IGBT device 20 according to a second embodiment of the present disclosure, taken along line DD′.

[0062] Reference Figure 6According to the second embodiment of the present disclosure, the trench-type IGBT device 20 can include a substrate 3 of a first conductivity type and a plurality of trenches 4. The plurality of trenches 4 are formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction DR1 and in which a plurality of gates G are respectively provided. A source region 7 of the first conductivity type and a contact region 8 of a second conductivity type extending in the first direction DR1 are formed between the plurality of trenches 4. Each of the plurality of gates G has a first width WG1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WG2 different from the first width, the first width WG1 and the second width WG2 being alternately arranged in the first direction DR1. The contact region 8 has a uniform third width WC3 in the second direction DR2.

[0063] The person skilled in the art will understand that, although the second embodiment of the present disclosure is described herein by way of example with the first conductivity type being N-type and the second conductivity type being P-type, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0064] In particular, as shown in Figures 6 to 8 According to the second embodiment of the present disclosure, the trench-type IGBT device 20 includes a first cell 20A and a second cell 20B alternately arranged in the first direction DR1. As shown in Figure 6 The p+ contact region in the first cell 20A and the p+ contact region in the second cell 10B have a uniform third width WC3 in the second direction DR2. In addition, as shown in Figure 6 According to the second embodiment of the present disclosure, the first width WG1 of the gate G in the first cell 20A in the second direction DR2 can be smaller than the second width WG2 of the gate G in the second cell 10B in the second direction DR2.

[0065] The second embodiment of the present disclosure is substantially the same as the first embodiment of the present disclosure except that, in the second embodiment of the present disclosure, the gate G has the first width WG1 and the second width WG2 alternately arranged in the first direction DR1, and the p+ contact region has the uniform third width WC3 in the first direction DR1, and therefore details of the structure of the trench-type IGBT device 20 according to the second embodiment of the present disclosure are not further described herein.

[0066] As shown in Figure 6 Figure 6 The first cell 20A and the second cell 20B having different widths of the gate G are alternately arranged in the first direction DR1. The trench-type IGBT devices are respectively formed in the first cell 20A and the second cell 20B.

[0067] As described above, the second width WG2 of the gate G in the second cell 20B can be greater than the first width WC1 of the gate G in the first cell 20A. That is, in the second cell 20B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 μm to about 0.5 μm, so that the channel doping concentration of the IGBT device in the second cell 20B is greater than 1018cm-3 18 cm -3 Thus, the IGBT device in the second cell 20B is always off. In contrast, in the first cell 20A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 μm, so that the trench type IGBT device in the first cell 20A can be normally operated.

[0068] That is, the trench type IGBT device according to the second embodiment of the present disclosure has a cell arrangement in which normal IGBT devices and always-off IGBT devices are alternately arranged in parallel with each other. Thus, the trench type IGBT device according to the second embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics. Further, since the IGBT device in the second cell 20B is always off, the gate in the IGBT device in the second cell 20B can be regarded as a dummy gate, so that gate charge (Qg) can also be reduced. Thus, in the trench type IGBT device according to the second embodiment of the present disclosure, there is no need to additionally add a dummy region for balancing the trade-off relationship between short-circuit current and on-state loss, so that the manufacturing process can be simplified and the chip area can be reduced.

[0069] According to the second embodiment of the present disclosure, by adjusting the proportional relationship between the third width WC3 of the p+ type contact region 8 in the first cell 20A and the fourth width WE4 of the n+ type source region 7 along the second direction DR2, the I-V characteristics of the trench type IGBT device can be adjusted.

[0070] According to the second embodiment of the present disclosure, the lengths of the first cell 20A and the second cell 20B along the first direction DR1 can be the same. According to the second embodiment of the present disclosure, the lengths of the first cell 20A and the second cell 20B along the first direction DR1 can be different. In the case where the lengths of the first cell 20A and the second cell 20B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 20A and the second cell 20B along the first direction DR1, the I-V characteristics of the trench type IGBT device can also be adjusted.

[0071] The method for manufacturing the trench-type IGBT device 20 according to the second embodiment of the present disclosure is substantially the same as the method for manufacturing the trench-type IGBT device 10 according to the first embodiment of the present disclosure, except that the etching mask for forming the trench 4 needs to be adjusted according to the change in the shape of the gate G, but this does not add additional process steps.

[0072] The trench-type IGBT device according to the present disclosure does not require a complex layout design and can be manufactured with simplified conventional semiconductor process steps, thereby enabling reduction in manufacturing cost. At the same time, the trench-type IGBT device according to the present disclosure enables reduction in saturation current, thereby improving short-circuit performance. In addition, by adjusting the relevant parameters in the trench-type IGBT device, the I-V characteristics of the trench-type IGBT device can be easily adjusted.

[0073] Although the present disclosure has been described with reference to the exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction and in which a plurality of gates are respectively provided, wherein an active region is formed between the trenches, and the active region has a source region of a first conductivity type and a contact region of a second conductivity type extending in the first direction, characterized in that the insulated-gate bipolar transistor device includes at least one first cell and a second cell alternately arranged in the first direction, the first cell and the second cell respectively including a portion of the plurality of gates and the contact region in the active region, wherein the contact region of the first cell has a first width in a second direction perpendicular to the first direction, the contact region of the second cell has a second width in the second direction perpendicular to the first direction, the first width is different from the second width, and the gates in the first cell and the second cell respectively have a uniform third width in the second direction, wherein the second width is greater than the first width, and The channel doping concentration of the second insulated gate bipolar transistor cell having the contact region of the second width is greater than 10 18 cm -3 such that the second insulated gate bipolar transistor cell is normally off.

2. The insulated-gate bipolar transistor device according to claim 1, characterized in that the active region includes a carrier blocking layer of a first conductivity type and a channel layer of a second conductivity type provided on the carrier blocking layer, and the source region and the contact region are provided on the channel layer.

3. The insulated-gate bipolar transistor device according to claim 1, characterized in that a depth of the contact region is greater than a depth of the source region.

4. The insulated gate bipolar transistor device of claim 1, wherein including: a source metal layer in contact with the source region and the contact region.

5. The insulated-gate bipolar transistor device according to claim 1, characterized in that a collector layer of a second conductivity type and an electric field cutoff layer of a first conductivity type are provided on a lower surface of the substrate.

6. The insulated gate bipolar transistor device of claim 5, wherein including: a collector metal layer in contact with the collector layer.

7. The insulated-gate bipolar transistor device according to claim 1, characterized in that the first conductivity type is N type and the second conductivity type is P type.

8. An insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downward from an upper surface of the substrate to have a strip shape parallel to each other extending in a first direction and in which a plurality of gates are respectively provided, wherein an active region is formed between the trenches, and the active region has a source region of a first conductivity type and a contact region of a second conductivity type extending in the first direction, characterized in that the insulated-gate bipolar transistor device includes at least one first cell and a second cell alternately arranged in the first direction, the first cell and the second cell respectively including a portion of the plurality of gates and the contact region in the active region, wherein the gates of the first cell have a first width in a second direction perpendicular to the first direction, and the gates of the second cell have a second width in the second direction perpendicular to the first direction, the first width is different from the second width, and a contact region of the first cell and the second cell has a uniform third width in the second direction, the second width is greater than the first width, and a channel doping concentration of a second insulated-gate bipolar transistor cell having the second gate is greater than 10 18 cm -3 such that the second insulated-gate bipolar transistor cell is normally-off.

9. A method of making an insulated gate bipolar transistor device according to any one of claims 1 to 8, characterized by comprises: forming a plurality of trenches downward from an upper surface of a substrate of a first conductivity type such that the plurality of trenches have a strip shape parallel to each other extending in a first direction; providing a plurality of gates in the plurality of trenches, respectively; and forming a source region of a first conductivity type and a contact region of a second conductivity type in each of active regions formed between the trenches using the same mask such that the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width being arranged alternately in the first direction.

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