Normally-off transistor and method of manufacturing the same

Abstract

A normally-off transistor is a III-V transistor comprising a buffer layer, a channel layer on top of the buffer layer, a barrier layer on top of the channel layer, a source, a drain and a gate on top of the barrier layer, and a threshold voltage adjustment layer composed of a reduced transition metal oxide and located under the gate and on top of the barrier layer. The normally-off transistor of the present embodiment is simple to manufacture, does not require additional etching which can cause surface damage, and does not require additional doping (current P-GaN gates require doping).

Description

TECHNICAL FIELD

[0001] The present application relates to a III-V transistor, and in particular, to a III-V normally-off (or E-mode) transistor and a method of manufacturing the same. BACKGROUND

[0002] Nowadays, in the field of power electronics, it is a future trend to introduce wide bandgap semiconductor devices to improve the efficiency of devices and modules and reduce energy consumption. In particular, gallium nitride high-frequency power devices, due to their excellent performance, have become the most promising semiconductor to surpass the limits of silicon materials in the next generation of high-power and high-frequency devices. However, to achieve high frequency and high power output, III-V transistors, such as gallium nitride (GaN) transistors, usually form a two-dimensional electron cloud (2DEG), making the operation of the device inherently normally-on (or D-mode), which causes the circuit to be more complex to use.

[0003] Figure 1 A III-V normally-on transistor is shown. The normally-on transistor 1 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a source 151, a drain 152, and a gate 153. The substrate 11 is, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), or a sapphire substrate. A buffer layer 12 of III-V metal material is formed on the substrate 11 through a nucleation layer (not shown) on the substrate 11. Figure 1 The channel layer 13 is a III-V material used to form a channel and is located above the buffer layer 12. The barrier layer 14 of III-V metal material is formed above the channel layer 13. The source 151, the drain 152, and the gate 153 are formed above the barrier layer 14, and in the horizontal direction, the gate 153 is located between the source 151 and the drain 152. In actual examples, the buffer layer 12 and the barrier layer 14 can be aluminum gallium nitride (AlGaN) layers, and the channel layer 13 can be a gallium nitride (GaN) layer. Under this architecture, the channel layer 13 near the barrier layer 14 forms a continuous two-dimensional electron cloud 131, causing the normally-on transistor 1 to be in a normally-on state, and the threshold voltage Vth to be less than zero.

[0004] To achieve the application goals of power saving, high speed and circuit miniaturization, the market requires the provision of normally-off components. In order to realize the normally-off transistor of III-V group, there are three known methods, which are described as follows. The first method is to etch the gate region of the transistor to form a recess, so that the gate can be closer to the transmission channel. However, this method requires the control of the cutoff etching process in the range of a few nanometers (<10 nm) to reduce the remaining thickness of the etching and integrate the dielectric layer to form a metal-insulator-semiconductor (MIS) structure, thereby increasing the threshold voltage (Vth) of the crystal, so the etching uniformity of the gate region and the production stability are greatly challenged. In addition, this method can damage the surface of the transmission channel, resulting in a significant decrease in the maximum current (Id) and a great impact on the electrical properties of the component.

[0005] The second method is to introduce negative fluorine ions under the gate to induce the channel below to shift the threshold voltage to the positive direction to achieve the normally-off purpose. The introduction of fixed fluorine ions can be achieved by plasma surface treatment or ion implantation, but it must also integrate the dielectric layer to form a metal-insulator-semiconductor (MIS) structure. Furthermore, the number of negative fluorine ions introduced will affect the threshold voltage, and it is difficult to control consistently in production, so it will affect the electrical uniformity of the transistors on the chip.

[0006] The third method is to form a P-type III-V group layer (such as a P-GaN layer) between the gate and the barrier layer to realize a normally-off transistor of III-V group high electron mobility (HEMT), where the threshold voltage Vth of the GaN transistor can reach 1.0 volt. The third method can effectively make the transistor normally-off, however, when the epitaxial (Epitaxy, also known as epitaxy) temperature exceeds 500 degrees Celsius, the magnesium hydride (Mg-H) complex will be formed in the hydrogen environment, resulting in a decrease in hole concentration and affecting the breakdown voltage. Accordingly, the compatibility of the above-mentioned P-GaN gate structure and subsequent annealing process is very challenging, and the production cost is relatively high. SUMMARY

[0007] According to the purpose of the present application, a normally-off transistor is provided for III-V group transistors, which includes a buffer layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a source, a drain and a gate located above the barrier layer, and a threshold voltage adjustment layer composed of a reduced transition metal oxide and located below the gate and above the barrier layer.

[0008] According to the above technical features, the work function of the threshold voltage adjustment layer is greater than or equal to 6.0 electron volts.

[0009] According to the above technical features, the reduced transition metal oxide is reduced molybdenum oxide (MoOx a reduced transition metal oxide (M x a reduced transition metal oxide (M x a reduced transition metal oxide (M x a reduced transition metal oxide (M x a reduced transition metal oxide (M x a reduced transition metal oxide (M

[0010] According to the above technical features, the normally-off transistor further comprises a substrate, wherein the buffer layer is located on the substrate.

[0011] According to the above technical features, the normally-off transistor is a high electron mobility transistor (HEMT transistor) or a metal-oxide-semiconductor field-effect transistor (MOSFET transistor) of group-III nitride (III-N).

[0012] According to the above technical features, the normally-off transistor is a GaN transistor, the thickness of the channel layer is between 30 nm and 150 nm, the thickness of the barrier layer is between 1 nm and 30 nm, and the thickness of the threshold voltage adjustment layer is between 0.5 nm and 100 nm.

[0013] According to the above technical features, the material of the buffer layer is AlGaN, and the chemical composition of the AlGaN is Al y Ga 1-y N, 5% <= y; and the material of the barrier layer of the AlGaN or AlN is AlGaN or AlN, and the chemical composition of the AlGaN is Al x Ga 1-x N, 0 <= x <= 40%.

[0014] According to the above technical features, the barrier layer is further formed with a trench, wherein the threshold voltage adjustment layer is embedded in the trench, and a portion of the gate is embedded in the trench.

[0015] According to the above technical features, the shape of the vertical cross section of the gate is a polygon similar to a trapezoid.

[0016] According to the above technical features, the normally-off transistor is a GaN transistor, the thickness of the channel layer is between 30 nm and 150 nm, the thickness of the barrier layer is between 1 nm and 30 nm, and the thickness of the threshold voltage adjustment layer is between 0.5 nm and 100 nm.

[0017] According to the above technical features, the threshold voltage adjusting layer is formed on the barrier layer by thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition or sputtering.

[0018] According to the above technical features, the sputtering is a reactive sputtering in which a metal target of molybdenum, vanadium, tungsten, niobium, palladium or rhenium is mixed with argon gas by combining oxygen or nitrogen dioxide gas, and the ratio of the oxygen or nitrogen dioxide to the argon gas is 0.05 to 0.5.

[0019] In summary, the normally closed transistor of the embodiment of the present application is simple to manufacture, does not need additional etching and does not cause surface damage, and does not need additional doping (the P-GaN gate needs doping). BRIEF DESCRIPTION OF DRAWINGS

[0020] The drawings of the present application are only used to make those skilled in the art of the present application easy to understand, the size and configuration are only schematic, and are not used to limit the present application, wherein the drawings are briefly described as follows:

[0021] Figure 1 is a sectional view of a normally open transistor of III-V group;

[0022] Figure 2 is a sectional view of a normally closed transistor of the embodiment of the present application;

[0023] Figure 3A is a voltage-current curve diagram of the normally closed transistor of the embodiment of the present application;

[0024] Figure 3B is a voltage-current curve diagram of the normally closed transistor of the P-GaN structure;

[0025] Figures 4A to 4G is a schematic diagram of each step of the manufacturing method of the normally closed transistor of the embodiment of the present application;

[0026] Figure 5A is a sectional view of a normally closed transistor of another embodiment of the present application; and

[0027] Figure 5B is a sectional view of a normally closed transistor of another embodiment of the present application.

[0028] Wherein, the reference signs are described as follows:

[0029] 1: normally open transistor

[0030] 2, 2', 2": normally closed transistor

[0031] 11, 21: substrate

[0032] 12, 22: buffer layer

[0033] 13, 23: channel layer

[0034] 131, 231: two-dimensional electron cloud

[0035] 14, 24, 24': barrier layer

[0036] 151, 251: source

[0037] 152, 252: drain

[0038] 153, 253, 253': gate

[0039] 254: threshold voltage adjustment layer DETAILED DESCRIPTION

[0040] In order to understand the technical features, contents and advantages of the present application and the effects that can be achieved, the present application is described in detail below in the form of embodiments in conjunction with the accompanying drawings, whose purpose is only to illustrate and assist the description, and not necessarily the true proportions and accurate configurations after implementation of the present application. Therefore, the appended drawings should not be interpreted as limiting the scope of the present application in actual implementation, and the foregoing is stated in advance.

[0041] In order to avoid the technical disadvantages caused by the prior art normally closed transistor, the present application proposes another novel and feasible method, which does not cause damage to the gate region, has a simple process, and does not require additional surface treatment, so as not to cause damage to the transistor channel surface and affect the electrical properties. Further, the present application is to grow a threshold voltage adjustment layer of reduced transition metal oxide on the barrier layer, which is located between the barrier layer and the gate, and has a work function greater than or equal to 6 electron volts (eV),

[0042] Please refer to Figure 2 , Figure 2 is a cross-sectional schematic diagram of a normally closed transistor according to an embodiment of the present application. The normally closed transistor 2 includes a substrate 21, a buffer layer 22, a channel layer 23, a barrier layer 24, a source 251, a drain 252, a gate 253, and a threshold voltage adjustment layer 254. The substrate 21 can be silicon, silicon carbide (SiC), silicon on insulator (SOI), or a sapphire substrate, which can have a size of, for example, from 2 inches to 8 inches, or larger. A nucleation layer, a buffer layer 22, and a channel layer 23 are formed on the substrate 21 by a method such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The barrier layer 24 is formed on the channel layer 23 by a method such as MBE or MOCVD. The source 251 and the drain 252 are formed on the barrier layer 24 by a method such as MBE or MOCVD. The gate 253 is formed on the barrier layer 24 by a method such as MBE or MOCVD. The threshold voltage adjustment layer 254 is formed on the barrier layer 24 by a method such as MBE or MOCVD. Figure 2A buffer layer 22 of a III-V metal material is formed on the substrate 21 (not shown). A channel layer 23 of a III-V material is formed on the buffer layer 22 for forming a channel. A barrier layer 24 of a III-V metal material is formed on the channel layer 23.

[0043] In practical examples, the buffer layer 22 can be an aluminum gallium nitride (AlGaN) layer, the channel layer 23 can be a gallium nitride (GaN) layer, and the barrier layer 24 can be an aluminum gallium nitride (AlGaN) or an aluminum nitride (AIN) layer. In the buffer layer 22 of AlGaN, the chemical composition of AlGaN is Al y Ga 1-y N, 5% <= y. The thickness of the channel layer 23 of GaN is between 30 nm and 150 nm, inclusive. The thickness of the barrier layer 24 of AlGaN or AIN is between 2 nm and 40 nm, inclusive, and in the barrier layer 24 of AlGaN or AIN, the chemical composition of AlGaN is Al x Ga 1-x N, 0 <= x <= 40%.

[0044] A source 251, a drain 252, and a gate 253 are formed on the barrier layer 24, and in the horizontal direction, the gate 253 is between the source 251 and the drain 252, wherein the source 251, the drain 252, and the gate 253 are a metal stack layer formed by at least one of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au), such as a metal stack of Ni / Au. It is noted that a threshold voltage adjustment layer 254 is formed under the gate 253 and on the barrier layer 24, i.e., in the vertical direction, the threshold voltage adjustment layer 254 is between the gate 253 and the barrier layer 24. The threshold voltage adjustment layer 254 is composed of a reduced transition metal oxide and has a work function higher than 6.0 eV, such as a reduced molybdenum oxide (MoO x , x <= 2), a reduced vanadium oxide (VO x , x <= 2, a reduced tungsten oxide (WO x , x <= 2), a reduced niobium oxide (NbO x , x <= 2), a reduced rhenium oxide (ReO x , x <= 2), or a reduced palladium oxide (PdO x , x <= 2). In practical examples, the thickness of the threshold voltage adjustment layer 254 can be between 0.5 nm and 100 nm, inclusive, preferably between 0.5 nm and 50 nm.

[0045] Under this architecture, the channel layer 23 near the barrier layer 24 forms a discontinuous two-dimensional electron cloud 231, where the discontinuity of the two-dimensional electron cloud 231 is located under the gate 253, resulting in the normally-off transistor 2 being in a normally-off state, with a threshold voltage Vth greater than zero. In actual experiments, if the normally-off transistor 2 is a GaN transistor, and a threshold voltage adjustment layer 254 with a work function of 6.6 electron volts is selected, then the threshold voltage of the normally-off transistor 2 is positive 0.9 volts.

[0046] Please note that the normally-off transistor 2 can be a HEMT transistor or a MOSFET transistor (metal-oxide-semiconductor field-effect transistor), and the present application is not limited thereto. In short, as long as a threshold voltage adjustment layer composed of a reduced transition metal oxide is disposed between the gate and the barrier layer to generate a III-V transistor with a threshold voltage greater than 0 volts, it can be covered within the scope of the normally-off transistor 2 derived therefrom. In addition, the normally-off transistor 2 can be a III-N (V group compound selected as N, i.e. III group nitride) transistor, such as, but not limited to, a transistor of AlGaN / GaN, InAlN / GaN, AlN / GaN, AlN / AlGaN, AlInGaN / GaN, AlInGaN / AlGaN architecture.

[0047] Please refer to Figure 3A and Figure 3B , Figure 3A is a voltage-current curve diagram of the normally-off transistor of the embodiment of the present application, and Figure 3B is a voltage-current curve diagram of the normally-off transistor of the P-GaN architecture. In Figure 3A and 3B , the horizontal axis is the gate-source voltage of the transistor, and the vertical axis is the current per unit length of the transistor. By comparing Figure 3A and Figure 3B , it can be known that the threshold voltage of the normally-off transistor 2 of the embodiment of the present application using the threshold voltage adjustment layer 254 with a work function of 6.6 electron volts is higher than that of the normally-off transistor of the P-GaN gate structure, and has a better current performance.

[0048] Please continue to refer to Figures 4A to 4F , Figures 4A to 4F is a schematic diagram of each step of the manufacturing method of the normally-off transistor of the embodiment of the present application. In Figure 4A , a substrate 21 is provided, and a nucleation layer (not shown) is formed on the substrate 21, then epitaxy is performed to form a buffer layer 22 on the substrate 21, wherein the buffer layer 22 is formed at high temperature. In Figure 4B , epitaxy is performed on the buffer layer 22 to form a channel layer 23 on the buffer layer 22. In Figure 4CIn one embodiment, the barrier layer 24' is formed by epitaxy on top of the channel layer 23.

[0049] In Figure 4D one embodiment, the barrier layer 24' is defined by mesa etching of the barrier layer 24', for example, using a chlorine (Cl2) based plasma etching system. Figure 4E In one embodiment, the source and drain ohmic contacts are defined and formed on the barrier layer 24 by electron beam deposition and annealing at high temperature using a metal stack, for example, titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au). Figure 4F In one embodiment, the threshold voltage adjustment layer 254 is formed on the barrier layer 24 by physical or chemical vapor deposition, for example, thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition or sputtering, and the sputtering is a reactive sputtering using a metal target, for example, molybdenum, vanadium, tungsten, niobium, palladium, rhenium, mixed with oxygen or nitrogen dioxide gas and argon gas, wherein the ratio of oxygen or nitrogen dioxide to argon is 0.05 to 0.5 (including both end values 0.05 and 0.5). Figure 4G In one embodiment, the gate 253 is defined and formed on the threshold voltage adjustment layer 254 by electron beam deposition.

[0050] Please refer to Figure 2 and Figure 5A , Figure 5A is a cross-sectional view of a normally-off transistor according to another embodiment of the present application. Figure 2 The barrier layer 24 in the normally-off transistor 2' in the embodiment does not have any trench and the threshold voltage adjustment layer 254 is directly formed on the barrier layer 24, but the present application is not limited thereto. Figure 5A In one embodiment, the barrier layer 24 of the normally-off transistor 2' has a trench and the threshold voltage adjustment layer 254 is buried in the trench of the barrier layer 24, and a portion of the gate 253 is also buried in the trench of the barrier layer 24.

[0051] Please refer to Figure 5A and Figure 5B , Figure 5B is a cross-sectional view of a normally-off transistor according to another embodiment of the present application. Figure 5B The shape of the vertical cross-section of the gate 253' of the normally-off transistor 2" is different from the shape of the vertical cross-section of the gate 253 of the normally-off transistor 2' in Figure 5A the embodiment. Figure 5B The shape of the vertical cross-section of the gate 253' of the normally-off transistor 2" is substantially a polygon similar to a trapezoid, and Figure 5AThe vertical cross-section of the gate 253 of the normally-off transistor 2' is substantially rectangular.

[0052] In particular, the normally-off transistor of the present application has a positive threshold voltage and is simple to manufacture without additional etching which causes surface damage and without additional doping (P-GaN gate requires doping). In addition, the normally-off transistor of the present application has a high threshold voltage and a better current performance. Figure 3A In comparison with the prior art, the normally-off transistor of the present application has a positive threshold voltage and is simple to manufacture without additional etching which causes surface damage and without additional doping (P-GaN gate requires doping). In addition, the normally-off transistor of the present application has a high threshold voltage and a better current performance. Figure 3B It can be appreciated that the normally-off transistor of the present application has a high threshold voltage and a better current performance.

[0053] In view of the above, it will be seen that the several objects of the application are achieved and other advantageous results attained.

[0054] The embodiments described above are intended to be illustrative only and in no way limit the scope of the present application. Changes in form and substitution of equivalents are contemplated as circumstances can suggest or render expedient and as applications of the principles of the present application can suggest themselves to those skilled in the art.

Claims

1. A normally-off transistor, which is a III-V transistor, comprising: a buffer layer (22); a channel layer (23) on the buffer layer (22); a barrier layer (24) on the channel layer (23); a source (251), a drain (252) and a gate (253) on the barrier layer (24); and a threshold voltage adjustment layer (254) composed of a reduced transition metal oxide, under the gate (253) and on the barrier layer (24), wherein a work function of the threshold voltage adjustment layer (254) is equal to or greater than 6.0 eV.

2. The normally-off transistor of claim 1, wherein the reduced transition metal oxide is reduced molybdenum oxide (MoO x ,x<=2), reduced vanadium oxide (VO x ,x<=2), reduced tungsten oxide (WO x ,x<=2), reduced niobium oxide (NbO x ,x<=2), reduced rhenium oxide (ReO x ,x<=2), or reduced palladium oxide (PdO x ,x<=2).

3. The normally-off transistor of claim 1, further comprising: a substrate (21), wherein the buffer layer (22) is on the substrate (21).

4. The normally-off transistor of claim 1, wherein the normally-off transistor (2) is a III-N HEMT transistor or a MOSFET transistor.

5. The normally-off transistor of claim 1, wherein the normally-off transistor (2) is a GaN transistor, a thickness of the channel layer (23) is between 30 nm and 150 nm, a thickness of the barrier layer (24) is between 1 nm and 30 nm, and a thickness of the threshold voltage adjustment layer (254) is between 0.5 nm and 100 nm.

6. The normally-off transistor according to claim 5, wherein the material of the buffer layer (22) is AlGaN, and the chemical composition formula of AlGaN is Al Ga N, 0 < x < 40%, 5% < = y; and the material of the barrier layer (24) is AlGaN or AlN, and the chemical composition formula of AlGaN is Al Ga N, 0 < x < 40%, 5% < = y. y Ga 1-y N, 0 < x < 40%, 5% < = y. x Ga 1-x N, 0 < x < 40%, 5% < = y.

7. The normally-off transistor of claim 1, wherein the barrier layer (24) further forms a trench, wherein the threshold voltage adjustment layer (254) is embedded in the trench, and a portion of the gate (253) is embedded in the trench.

8. The normally-off transistor of claim 7, wherein a vertical cross-section of the gate (253) is a polygon similar to a trapezoid.

9. A method of manufacturing a normally-off transistor, wherein the normally-off transistor (2) is a III-V transistor, and the method comprises: providing a substrate (21), and sequentially forming a buffer layer (22), a channel layer (23) and a barrier layer (24) on the substrate (21); etching the barrier layer (24); forming a source (251) and a drain (252) on the barrier layer (24); forming a threshold voltage adjustment layer (254) on the barrier layer (24), wherein the threshold voltage adjustment layer (254) is composed of a reduced transition metal oxide, wherein a work function of the threshold voltage adjustment layer (254) is equal to or greater than 6.0 eV; and forming a gate (253) on the threshold voltage adjustment layer (254).

10. The method of claim 9, wherein the threshold voltage adjustment layer (254) is formed on the barrier layer (24) by thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition or sputtering.

11. The manufacturing method of claim 10, wherein the sputtering is a reactive sputtering with a metal target of molybdenum, vanadium, tungsten, niobium, palladium or rhenium mixed with argon gas in combination with oxygen or nitrogen dioxide gas, wherein the ratio of the oxygen or the nitrogen dioxide to the argon gas is 0.05 to 0.5.

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