Circuit board structure and manufacturing method thereof

Abstract

The present invention provides a circuit board structure and a manufacturing method thereof, wherein the circuit substrate structure includes a circuit layer, a first dielectric layer, a first graphene layer, a first conductive hole, and a first build-up circuit layer. The circuit layer includes a plurality of connection pads. The first dielectric layer is arranged on the circuit layer and has a first opening. The first opening exposes a plurality of connection pads. The first graphene layer is conformally arranged on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive hole is arranged in the first opening. The first build-up circuit layer is arranged corresponding to the first conductive seed layer region. The first build-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the plurality of connection pads through the first conductive hole and the first conductive seed layer region. The circuit board structure and the manufacturing method thereof of the present invention can effectively improve the reliability of signal transmission or the yield of the product.

Description

Technical Field

[0001] The present invention relates to a circuit board structure and a manufacturing method thereof, and in particular to a circuit board structure using graphene as an etching-free seed layer and a manufacturing method thereof. Background Art

[0002] With the demand for 5G and finer circuits, heat dissipation design and circuit line specifications are becoming increasingly important. In the current manufacturing process, after the circuits are formed, an etching process is required to remove the seed layer in the line spacing to form each independent circuit. However, during the etching process, the line line shape is often attacked by the etching solution, resulting in undercutting, peeling, or deformation of the line shape. This can hinder signal transmission, affect product reliability, and even lead to poor product quality. Summary of the Invention

[0003] The present invention is directed to a circuit board structure and a manufacturing method thereof, which can effectively improve the reliability of signal transmission or the yield of products.

[0004] The circuit board structure of the present invention includes a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first build-up circuit layer. The circuit layer includes a plurality of connection pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes a plurality of connection pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region that are staggered. The first conductive via is disposed in the first opening. The first build-up circuit layer is disposed corresponding to the first conductive seed layer region. The first build-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the plurality of connection pads through the first conductive via and the first conductive seed layer region.

[0005] In an embodiment of the present invention, the above-mentioned circuit board structure further includes a second dielectric layer, a second graphene layer, a second conductive hole and a second build-up circuit layer. The second dielectric layer is arranged on the first build-up circuit layer and covers the first non-conductive seed layer area. The second dielectric layer has a second opening, and the second opening exposes the first build-up circuit layer. The second graphene layer is conformally arranged on the second dielectric layer and in the second opening, and has a second conductive seed layer area and a second non-conductive seed layer area. The second conductive hole is arranged in the second opening. The second build-up circuit layer is arranged corresponding to the second conductive seed layer area. The second build-up circuit layer exposes the second non-conductive seed layer area and is electrically connected to the first build-up circuit layer through the second conductive hole and the second conductive seed layer area.

[0006] In an embodiment of the present invention, the circuit board structure further includes a graphene oxide layer. The graphene oxide layer is conformally disposed on the first build-up circuit layer. The second opening penetrates the graphene oxide layer to expose a portion of the surface of the first build-up circuit layer.

[0007] In an embodiment of the present invention, the circuit board structure further includes an insulating protective layer, which is disposed on the second build-up circuit layer and exposes the connection pads of the second build-up circuit layer.

[0008] In an embodiment of the present invention, the circuit board structure further includes an electronic component. The electronic component is embedded in the second dielectric layer and has an active surface and a back surface facing each other. The active surface of the electronic component is electrically connected to the first build-up circuit layer, and the back surface contacts the second graphene layer.

[0009] In an embodiment of the present invention, the electronic component protrudes from the upper surface of the second dielectric layer. The electronic component further comprises a peripheral surface connecting the active surface and the back surface. The second graphene layer contacts a portion of the peripheral surface.

[0010] In an embodiment of the present invention, the above-mentioned circuit board structure further includes a third dielectric layer, a third graphene layer, a third conductive hole and a third build-up circuit layer. The third dielectric layer is arranged on the second build-up circuit layer and covers the second non-conductive seed layer area. The third dielectric layer has a third opening, and the third opening exposes the second build-up circuit layer. The third graphene layer is conformally arranged on the third dielectric layer and in the third opening, and has a third conductive seed layer area and a third non-conductive seed layer area. The third conductive hole is arranged in the third opening. The third build-up circuit layer is arranged corresponding to the third conductive seed layer area. The third build-up circuit layer exposes the third non-conductive seed layer area and is electrically connected to the second build-up circuit layer through the third conductive hole and the third conductive seed layer area.

[0011] In an embodiment of the present invention, the second dielectric layer further comprises a fourth opening, and the circuit board structure further comprises an electronic component and a fourth conductive via. The electronic component is disposed on the first non-conductive seed layer region and has an active surface and a back surface facing each other. The fourth conductive via is disposed within the fourth opening. The second build-up circuit layer is electrically connected to the electronic component through the fourth conductive via and the second conductive seed layer region.

[0012] In an embodiment of the present invention, the circuit board structure further includes a graphene oxide layer. The graphene oxide layer is conformally disposed on the electronic component and is located between the electronic component and the second dielectric layer.

[0013] The manufacturing method of the circuit board structure of the present invention includes the following steps. A circuit structure is provided. The circuit structure includes a circuit layer and a first dielectric layer. The first dielectric layer is arranged on the circuit layer. The circuit layer includes a plurality of connection pads. A first opening is formed in the first dielectric layer to expose the plurality of connection pads. A first graphene layer is conformally formed on the first dielectric layer and in the first opening. The first graphene layer has a first portion and a second portion. A first conductive hole is formed in the first opening. A first build-up circuit layer is formed on the first portion to expose the second portion. The second portion of the first graphene layer is oxidized to form a first non-conductive seed layer region, and the first portion is defined as a first conductive seed layer region. The first build-up circuit layer is arranged corresponding to the first conductive seed layer region, and is electrically connected to the plurality of connection pads through the first conductive hole and the first conductive seed layer region.

[0014] In an embodiment of the present invention, the above-mentioned manufacturing method further includes the following steps. A second dielectric layer is formed on the first build-up circuit layer to cover the first non-conductive seed layer region. The second dielectric layer has a second opening to expose the first build-up circuit layer. A second graphene layer is conformally formed on the second dielectric layer and in the second opening. The second graphene layer has a third portion and a fourth portion. A second conductive hole is formed in the second opening. A second build-up circuit layer is formed on the third portion to expose the fourth portion. The fourth portion of the second graphene layer is oxidized to form a second non-conductive seed layer region, and the third portion is defined as a second conductive seed layer region. Wherein, the second build-up circuit layer is arranged corresponding to the second conductive seed layer region, and is electrically connected to the first build-up circuit layer through the second conductive hole and the second conductive seed layer region.

[0015] In an embodiment of the present invention, the manufacturing method further comprises the following steps: forming an insulating protection layer on the second build-up circuit layer to expose the connection pads of the second build-up circuit layer.

[0016] In an embodiment according to the present invention, the above-described steps, before forming the second dielectric layer on the first build-up wiring layer, further include the following steps: Disposing an electronic component on the first build-up wiring layer. The electronic component has an active surface and a back surface opposing each other, the active surface being electrically connected to the first build-up wiring layer, and the back surface being in contact with the second graphene layer.

[0017] In an embodiment of the present invention, the above-mentioned second dielectric layer also has a fourth opening, and before forming the second dielectric layer on the first build-up wiring layer, the following steps are also included. An electronic component is set on the first non-conductive seed layer area. The electronic component has an active surface and a back surface opposite to each other, and a surrounding surface connecting the active surface and the back surface. The back surface faces the first non-conductive seed layer area. A graphene oxide layer is conformally formed on the electronic component to cover the active surface and the surrounding surface. After forming the second dielectric layer on the first build-up wiring layer, the following steps are also included. A fourth conductive hole is formed in the fourth opening so that the second build-up wiring layer is electrically connected to the electronic component through the fourth conductive hole and the second conductive seed layer area.

[0018] In an embodiment of the present invention, before forming the second dielectric layer on the first build-up circuit layer, the process further includes the following steps: conformally forming a graphene oxide layer on the first build-up circuit layer to cover the first build-up circuit layer.

[0019] Based on the above, in the circuit board structure of the embodiment of the present invention, since the first non-conductive seed layer region can have good insulation properties, after the first build-up circuit layer is formed, it is not necessary to perform another etching process to remove the first non-conductive seed layer region. In this way, the existing situation in which the seed layer exposed by the first build-up circuit layer is removed, which causes circuit undercutting, circuit peeling or circuit shape deformation in the seed layer covered by the first build-up circuit layer, can be avoided. It can also effectively improve the reliability of signal transmission or the yield of the product.

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1G is a cross-sectional schematic diagram of a method for manufacturing a circuit board structure according to an embodiment of the present invention;

[0022] Figure 2 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention;

[0023] Figure 3 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention;

[0024] Figure 4 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention;

[0025] Figure 5 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention;

[0026] Figure 6 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention;

[0027] Figure 7 Schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention.

[0028] Description of Reference Numerals

[0029] 10a, 10b, 10c, 10d, 10e, 10f, 10g: circuit board structure;

[0030] 110: line structure;

[0031] 112: circuit layer;

[0032] 1121, 1901: connection pad;

[0033] 114: first dielectric layer;

[0034] 112a, 114a, 152, 164: upper surface;

[0035] 112b, 114b: lower surface;

[0036] 116: first opening;

[0037] 116S: side wall;

[0038] 120: first graphene layer;

[0039] 122: first portion / first conductive seed layer region;

[0040] 124: Part II;

[0041] 125: first non-conductive seed layer region;

[0042] 140: first conductive via;

[0043] 150: first build-up circuit layer;

[0044] 160: second dielectric layer;

[0045] 162: second opening;

[0046] 166: fourth opening;

[0047] 170: second graphene layer;

[0048] 172: third portion / second conductive seed layer region;

[0049] 175: second non-conductive seed layer region;

[0050] 180: second conductive hole;

[0051] 190: second build-up circuit layer;

[0052] 200: insulating protective layer;

[0053] 210, 280: graphene oxide layer;

[0054] 230: third dielectric layer;

[0055] 232: third opening;

[0056] 240: third graphene layer;

[0057] 242: third conductive seed layer region;

[0058] 245: third non-conductive seed layer region;

[0059] 250: third conductive via;

[0060] 260: third build-up circuit layer;

[0061] 270: fourth conductive via;

[0062] 300, 300a, 300b: electronic components;

[0063] 302, 302a, 304b: active surface;

[0064] 304, 304a, 304b: back surface;

[0065] 306a, 306b: surrounding surface;

[0066] Y: Normal direction. DETAILED DESCRIPTION

[0067] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0068] Please refer to Figure 1AIn this embodiment, a circuit structure 110 is first provided. The circuit structure 110 includes a circuit layer 112 and a first dielectric layer 114. The first dielectric layer 114 is disposed on the circuit layer 112, and the circuit layer 112 includes a plurality of connection pads 1121. Specifically, the first dielectric layer 114 has an upper surface 114a and a lower surface 114b opposite to each other, and the circuit layer 112 has an upper surface 112a and a lower surface 112b opposite to each other. The circuit layer 112 is buried in the first dielectric layer 114, and the first dielectric layer 114 exposes the lower surface 112b of the circuit layer 112. In other words, the lower surface 114b of the first dielectric layer 114 is flush and coplanar with the lower surface 112b of the circuit layer 112. In this embodiment, the material of the circuit layer 112 may be, for example, copper or other conductive materials, and the material of the first dielectric layer 114 may be, for example, resin or other dielectric materials, but is not limited thereto. Here, the method for forming the circuit layer 112 may be, for example, a lithography-electroplating semi-additive process (SAP), a modified semi-additive process (mSAP), or a dry film tenting process, but is not limited thereto.

[0069] Next, please refer to Figure 1B , forming a first opening 116 in the first dielectric layer 114 to expose the plurality of connection pads 1121. In this embodiment, the first opening 116 may expose a portion of the upper surface 112a of the circuit layer 112 (e.g., corresponding to the connection pads 1121), but is not limited thereto. Here, the method for forming the first opening 116 may be, for example, laser drilling, but is not limited thereto.

[0070] Next, please refer to Figure 1C , conformally forming the first graphene layer 120 on the first dielectric layer 114 and in the first opening 116. Specifically, the first graphene layer 120 directly contacts and completely covers the upper surface 114a of the first dielectric layer 114, the sidewall 116S in the first opening 116, and the upper surface 112a of the portion of the circuit layer 112 (for example, the connection pad 1121) exposed by the first opening 116. In this embodiment, the first graphene layer 120 can be composed of a single layer or multiple layers of graphene film and have a substantially uniform thickness. The thickness of the first graphene layer 120 can be, for example, between 0.5 nanometers and 500 nanometers, but is not limited thereto. When the thickness of the first graphene layer 120 is less than 0.5 nanometers, it will be difficult to use as a seed layer in subsequent processes. When the thickness of the first graphene layer 120 is greater than 500 nanometers, it is difficult to completely oxidize the first graphene layer 120 in the subsequent oxidation process.

[0071] In this embodiment, the method for forming the first graphene layer 120 may include the following steps: First, a graphene solution is prepared. Next, graphene is uniformly deposited on the first dielectric layer 114 and in the first opening 116. The deposition method may be, for example, an immersion method (the immersion time is, for example, 10 seconds to 5 minutes, but not limited thereto) or a coating method. Next, a drying step is performed, for example, by drying with hot air at 80°C, but not limited thereto. The prepared graphene solution may be a reduced graphene solution or an oxidized graphene solution. When a reduced graphene solution is used for graphene deposition, the first graphene layer 120 of this stage is formed after the drying step. If an oxidized graphene solution is used for graphene deposition, a reduction process (for example, by applying H2 plasma, but not limited thereto) must be performed after the drying step to reduce the graphene oxide to reduced graphene oxide, thereby forming the first graphene layer 120 of this stage. Furthermore, in this embodiment, since the liquid graphene solution can be evenly coated on various uneven substrates and the graphene material has good adhesion to the dielectric material, the graphene material can be used as the seed layer material.

[0072] Next, please refer to Figures 1D to 1E , forming a first conductive via 140 in the first opening 116, and forming a first build-up wiring layer 150 on the first portion 122 of the first graphene layer 120 to expose the second portion 124 of the first graphene layer 120. Specifically, in this embodiment, the method of forming the first conductive via 140 and the first build-up wiring layer 150 may include the following steps: First, as shown in FIG. Figure 1D As shown, a patterned photoresist layer 130 is formed on the first graphene layer 120 to expose a portion of the first graphene layer 120. Figure 1E As shown, the first graphene layer 120 is used as a seed layer to form a first conductive via 140 and a first build-up circuit layer 150 on a portion of the first graphene layer 120, and the patterned photoresist layer 130 is removed to expose another portion of the first graphene layer 120. Here, the material of the patterned photoresist layer 130 can be, for example, a positive photoresist or a negative photoresist, but is not limited thereto.

[0073] In this embodiment, the portion of the first graphene layer 120 covered by the first build-up circuit layer 150 can be defined as a first portion 122, and the other portion of the first graphene layer 120 exposed by the first build-up circuit layer 150 can be defined as a second portion 124. The first portion 122 and the second portion 124 are arranged in an alternating manner. Specifically, the first portion 122 can be disposed on the sidewall 116S of the first opening 116, the upper surface 112a of the portion of the circuit layer 112 exposed by the first opening 116 (for example, the connection pad 1121), and the upper surface 114a of a portion of the first dielectric layer 114. The second portion 124 can be disposed on the upper surface 114a of another portion of the first dielectric layer 114.

[0074] Please refer to Figure 1D and Figure 1E , since the reduced graphene material has an extremely high electron mobility (greater than 15,000 cm 2 V -1 s- 1 ) and low resistivity (10-8Ω·m), thus having good conductivity. Therefore, in this embodiment, the first graphene layer 120 can serve as a seed layer to form the first conductive via 140 and the first build-up wiring layer 150 on the first portion 122 not covered by the patterned photoresist layer 130. In this embodiment, the first conductive via 140 and the first build-up wiring layer 150 can directly contact the first portion 122 of the first graphene layer 120 and do not contact the second portion 124 of the first graphene layer 120. The first conductive via 140 and the first build-up wiring layer 150 can expose the second portion 124 of the first graphene layer 120. In other words, the orthographic projection of the first build-up wiring layer 150 on the first graphene layer 120 can completely overlap with the first portion 122 of the first graphene layer 120 and does not overlap with the second portion 124 of the first graphene layer 120. Here, the material of the first conductive via 140 and the first build-up circuit layer 150 can be copper or other conductive materials, but is not limited thereto.

[0075] Next, please refer to Figure 1F, oxidizing the second portion 124 of the first graphene layer 120 exposed by the first build-up wiring layer 150 to form a first non-conductive seed layer region 125, and defining the unoxidized section of the first graphene layer 120 (i.e., the first portion 122) as the first conductive seed layer region 122. In this embodiment, the first build-up wiring layer 150 may be disposed corresponding to the first conductive seed layer region 122, and the first build-up wiring layer 150 may be electrically connected to the first conductive seed layer region 122 via the first conductive vias 140 to the plurality of connection pads 1121. Specifically, because the first conductive vias 140 and the first build-up wiring layer 150 may completely cover the first portion 122 of the first graphene layer 120, in this step, only the second portion 124 of the first graphene layer 120 exposed by the first build-up wiring layer 150 is oxidized to form the first non-conductive seed layer region 125. The first conductive seed layer regions 122 and the first non-conductive seed layer regions 125 are arranged alternately. The first conductive seed layer region 122 may be reduced graphene, and the first non-conductive seed layer region 125 may be oxidized graphene. In the normal direction Y of the circuit board structure 10a, the orthographic projection area of the first build-up circuit layer 150 may be substantially equal to the orthographic projection area of the first conductive seed layer region 122. The method for oxidizing the second portion 124 of the first graphene layer 120 may be, for example, a dry process using O2 / O3 plasma oxidation or a wet process using a KMnO4 / H2O2 aqueous solution (i.e., the Hummer method), but the present invention is not limited thereto.

[0076] In other embodiments (not shown), when oxidizing second portion 124 of first graphene layer 120, first portion 122 adjacent to second portion 124 may also be oxidized, resulting in first non-conductive seed layer region 125 comprising second portion 124 and a small portion of first portion 122. In this case, first build-up wiring layer 150 may contact first non-conductive seed layer region 125. In other words, in the normal direction Y of circuit board structure 10a, the orthographic projection of first build-up wiring layer 150 may partially overlap with first non-conductive seed layer region 125, but the present invention is not limited to this.

[0077] In some embodiments, the first build-up wiring layer 150 contacts the first conductive seed layer region 122, and the first build-up wiring layer 150 may partially contact (not shown) or not contact the first non-conductive seed layer region 125 (e.g., Figure 1FAs shown in Figure 2 ). Because the oxidized graphene material has a high resistivity (1012 Ω·m), the first non-conductive seed layer region 125 can have excellent insulation properties. Consequently, after forming the first build-up wiring layer 150, a separate etching process is not required to remove the first non-conductive seed layer region 125. This avoids the conventional practice of removing the seed layer exposed by the first build-up wiring layer, which can cause undercutting, peeling, or deformation of the seed layer covered by the first build-up wiring layer. Furthermore, it effectively improves signal transmission reliability and product yield.

[0078] Next, please refer to Figure 1G , forming a second dielectric layer 160, a second opening 162, a second graphene layer 170, a second conductive via 180, a second build-up wiring layer 190, and an insulating protection layer 200. Specifically, the second dielectric layer 160 is first formed on the first build-up wiring layer 150, covering the first non-conductive seed layer region 125. The first dielectric layer 114 and the second dielectric layer 160 can be located on opposite sides of the first non-conductive seed layer region 125.

[0079] Then, similar to Figure 1B In the step of forming a second opening 162 in the second dielectric layer 160 to expose the first build-up circuit layer 150, the second opening 162 exposes a portion of the upper surface 152 of the first build-up circuit layer 150 away from the first graphene layer 120. However, the present invention is not limited thereto.

[0080] Then, similar to Figure 1C In the step of conformally forming the second graphene layer 170 on the second dielectric layer 160 and in the second opening 162 .

[0081] Then, similar to Figures 1D to 1E In the step of forming a second conductive hole 180 in the second opening 162, and forming a second build-up circuit layer 190 on the third portion 172 of the second graphene layer 170 to expose the fourth portion (i.e. Figure 1G The second non-conductive seed layer region 175 is located in the middle).

[0082] Then, similar to Figure 1F The fourth portion of the second graphene layer 170 is oxidized to form a second non-conductive seed layer region 175, and the unoxidized portion of the second graphene layer 170 (i.e., the third portion 172) is defined as a second conductive seed layer region 172. A second build-up circuit layer 190 is disposed corresponding to the second conductive seed layer region 172, and is electrically connected to the first build-up circuit layer 150 through second conductive vias 180.

[0083] Specifically, because the second conductive vias 180 and the second build-up wiring layer 190 can completely cover the third portion 172 of the second graphene layer 170, only the fourth portion of the second graphene layer 170 is oxidized in this step to form the second non-conductive seed layer region 175. The second conductive seed layer regions 172 and the second non-conductive seed layer regions 175 are arranged alternately. The second conductive seed layer regions 172 can be reduced graphene, and the second non-conductive seed layer regions 175 can be oxidized graphene. In the normal direction Y of the circuit board structure 10a, the orthographic projection area of the second build-up wiring layer 190 can be substantially equal to the orthographic projection area of the second conductive seed layer region 172.

[0084] In some embodiments, the second build-up wiring layer 190 contacts the second conductive seed layer region 172, and the second build-up wiring layer 190 may partially contact (not shown) or not contact the second non-conductive seed layer region 175 (e.g., Figure 1G Because second non-conductive seed layer region 175 has excellent insulation properties, a separate etching process is not required to remove second non-conductive seed layer region 175 after forming second build-up wiring layer 190. This avoids the conventional practice of removing the seed layer exposed by the second build-up wiring layer, which can cause undercutting, peeling, or deformation of the seed layer covered by the second build-up wiring layer. Furthermore, it effectively improves signal transmission reliability and product yield.

[0085] Then, an insulating protection layer 200 is formed on the second build-up circuit layer 190 to expose the connection pads 1901 of the second build-up circuit layer 190. Thus, the production of the circuit board structure 10a is completed.

[0086] In this embodiment, since both the oxidized graphene material and the reduced graphene material have excellent thermal conductivity (the thermal conductivity coefficient of a single-layer graphene film can reach 5300 W / mK), compared to the general method of conducting heat generated by the inner layer circuit through an embedded heat dissipation copper block, the circuit board structure 10a of this embodiment can also conduct heat generated by the inner layer circuit (i.e., the circuit layer 112, the first conductive via 140, the first build-up circuit layer 150, the second conductive via 180, and the second build-up circuit layer 190) through the first conductive seed layer region 122, the first non-conductive seed layer region 125, the second conductive seed layer region 172, and the second non-conductive seed layer region 175, thereby enabling the circuit board structure 10a of this embodiment to have better heat dissipation efficiency.

[0087] In short, the circuit board structure 10a of this embodiment includes a circuit layer 112, a first dielectric layer 114, a first graphene layer 120, a first conductive via 140, and a first build-up circuit layer 150. Circuit layer 112 includes a plurality of connection pads 1121. First dielectric layer 114 is disposed on circuit layer 112 and has a first opening 116. First opening 116 exposes a plurality of connection pads 1121. First graphene layer 120 is conformally disposed on first dielectric layer 114 and within first opening 116, and has alternating first conductive seed layer regions 122 and first non-conductive seed layer regions 125. First conductive via 140 is disposed within first opening 116. First build-up circuit layer 150 is disposed corresponding to first conductive seed layer regions 122. First build-up circuit layer 150 exposes first non-conductive seed layer regions 125 and is electrically connected to the plurality of connection pads 1121 through first conductive via 140 and first conductive seed layer regions 122.

[0088] It is particularly noted that although the circuit board structure 10a of this embodiment only shows three circuit layers (i.e., circuit layer 112, first build-up circuit layer 150, and second build-up circuit layer 190), two graphene layers (i.e., first graphene layer 120 and second graphene layer 170), and two dielectric layers (i.e., first dielectric layer 114 and second dielectric layer 160) stacked one on top of the other, the present invention does not limit the number of graphene layers, circuit layers, and dielectric layers. In other embodiments, the above steps can be repeated to form a circuit board structure with multiple stacked circuit layers.

[0089] The following examples are provided for illustration purposes only. It should be noted that the following examples share the same component numbers and some of the details as the previous examples, with the same numbers used to represent the same or similar components, and descriptions of the same technical details omitted. For the omitted details, please refer to the previous examples, and the following examples will not be repeated.

[0090] Figure 2 This is a cross-sectional diagram of a circuit board structure according to an embodiment of the present invention. Figure 1G and Figure 2 , Figure 2 The circuit board structure 10b and Figure 1G The main difference between the circuit board structure 10a and the circuit board structure 10b is that the circuit board structure 10b further includes an electronic component 300.

[0091] Specifically, please refer to Figure 2In this embodiment, the electronic component 300 is embedded in the second dielectric layer 160. The electronic component 300 has an active surface 302 and a back surface 304 facing each other. The active surface 302 of the electronic component 300 is electrically connected to the first build-up circuit layer 150, and the back surface 304 contacts the second graphene layer 170. In this embodiment, the electronic component 300 may be, for example, a semiconductor chip (e.g., a chip-type passive component or an LSI die), but is not limited thereto.

[0092] In this embodiment, the method for arranging the electronic component 300 may include the following steps: forming a first non-conductive seed layer region 125 (eg Figure 1F After that, a second dielectric layer 160 is formed on the first build-up circuit layer 150 (as shown in FIG. Figure 1G As shown in FIG, the electronic component 300 is disposed on the first build-up circuit layer 150 .

[0093] In this embodiment, because the thickness of the electronic component 300 (i.e., the vertical distance between the active surface 302 and the back surface 304) is substantially equal to the vertical distance between the upper surface 164 of the second dielectric layer 160 facing the second build-up circuit layer 190 and the upper surface 152 of the first build-up circuit layer 150, the second dielectric layer 160 does not cover the back surface 304 of the electronic component 300, and the upper surface 164 of the second dielectric layer 160 is coplanar with the back surface 304 of the electronic component 300. Therefore, the second graphene layer 170 can directly contact the electronic component 300, thereby improving the heat dissipation efficiency of the electronic component 300.

[0094] Figure 3 This is a cross-sectional view of a circuit board structure according to another embodiment of the present invention. Figure 1G and Figure 3 , Figure 3 The circuit board structure 10c and Figure 1G The main difference between the circuit board structure 10a and the circuit board structure 10b is that the circuit board structure 10b further includes a graphene oxide layer 210 .

[0095] Specifically, the graphene oxide layer 210 can be conformally disposed on the first build-up wiring layer 150, exposing a portion of the upper surface 152 of the first build-up wiring layer 150 (i.e., the portion of the upper surface 152 of the first build-up wiring layer 150 exposed by the second opening 162). The second dielectric layer 160 is disposed on the graphene oxide layer 210. The first build-up wiring layer 150 and the second dielectric layer 160 are located on opposite sides of the graphene oxide layer 210. In this embodiment, the graphene oxide layer 210 can be disposed along the contours of the first non-conductive seed layer region 125 of the first graphene layer 120 and the first build-up wiring layer 150, so that the graphene oxide layer 210 can directly contact the first non-conductive seed layer region 125. The graphene oxide layer 210 and the first dielectric layer 114 can be located on opposite sides of the first non-conductive seed layer region 125. The second opening 162 may penetrate the second dielectric layer 160 and the graphene oxide layer 210 to expose a portion of the first build-up circuit layer 150 .

[0096] In this embodiment, the method for forming the graphene oxide layer 210 may include the following steps: forming the first non-conductive seed layer region 125 (eg Figure 1F After that, a second dielectric layer 160 is formed on the first build-up circuit layer 150 (as shown in FIG. Figure 1G Before the fabrication, a graphene oxide layer 210 is conformally formed on the first build-up circuit layer 150 to cover the first build-up circuit layer 150 .

[0097] In this embodiment, because the graphene oxide layer 210 is located on the first build-up circuit layer 150, the surface of the first build-up circuit layer 150 can be flattened, thereby improving signal transmission efficiency. In addition, because the graphene material (e.g., the graphene oxide layer 210) and the dielectric material (e.g., the second dielectric layer 160) have good bonding strength, the conventional roughening step of the circuit layer before forming the dielectric material on the circuit layer can be omitted, thereby avoiding a decrease in signal transmission efficiency. Furthermore, because the graphene material itself has a two-dimensional structure and has the property of accelerating signal transmission, the design of the graphene oxide layer 210 and the first graphene layer 120 being located on opposite sides of the first build-up circuit layer 150 can achieve better signal transmission efficiency and further improve heat dissipation efficiency.

[0098] In some other embodiments, a graphene oxide layer may be disposed on each circuit layer, for example, a graphene oxide layer may be formed on the circuit layer, the first build-up circuit layer, and the second build-up circuit layer. In this way, the circuit board structure may have better heat dissipation efficiency and better signal transmission efficiency.

[0099] Figure 4 This is a cross-sectional view of a circuit board structure according to another embodiment of the present invention. Figure 2 and Figure 4 , Figure 4 The circuit board structure 10d and Figure 2 The main difference between the circuit board structure 10b and the circuit board structure 10b is that the electronic component 300a protrudes from the upper surface 164 of the second dielectric layer 160. The electronic component 300a further has a peripheral surface 306a connecting the active surface 302a and the back surface 304a. The second graphene layer 170 contacts a portion of the peripheral surface 306a.

[0100] Specifically, the thickness of electronic component 300a in this embodiment (i.e., the vertical distance between active surface 302a and back surface 304a) is greater than the vertical distance between upper surface 164 of second dielectric layer 160 and upper surface 152 of first build-up circuit layer 150. This allows electronic component 300a to protrude beyond upper surface 164 of second dielectric layer 160. Therefore, after forming second graphene layer 170 on second dielectric layer 160, second graphene layer 170 can contact back surface 304a and a portion of surrounding surface 306a of electronic component 300a, thereby improving heat dissipation efficiency. Furthermore, in the normal direction Y of circuit board structure 10d, second build-up circuit layer 190 does not overlap with electronic component 300a, but this is not a limitation.

[0101] Figure 5 This is a cross-sectional view of a circuit board structure according to another embodiment of the present invention. Figure 4 and Figure 5 , Figure 5 The circuit board structure 10e and Figure 4 The main difference between the circuit board structure 10d and the circuit board structure 10e is that the circuit board structure 10e further includes a third dielectric layer 230 , a third graphene layer 240 , a third conductive via 250 and a third build-up circuit layer 260 .

[0102] Specifically, the third dielectric layer 230 is disposed on the second build-up wiring layer 190 and covers the second non-conductive seed layer region 175. The third dielectric layer 230 has a third opening 232, and the third opening 232 exposes the second build-up wiring layer 190. The third graphene layer 240 is conformally disposed on the third dielectric layer 230 and within the third opening 232, and has a third conductive seed layer region 242 and a third non-conductive seed layer region 245. The third conductive via 250 is disposed within the third opening 232. The third build-up wiring layer 260 is disposed corresponding to the third conductive seed layer region 242. The third build-up wiring layer 260 exposes the third non-conductive seed layer region 245, and the third build-up wiring layer 260 is electrically connected to the second build-up wiring layer 190 through the third conductive via 250 and the third conductive seed layer region 242.

[0103] In some embodiments, the third build-up wiring layer 260 contacts the third conductive seed layer region 242 and may partially contact (not shown) or not contact the third non-conductive seed layer region 245 (eg, Figure 5 In addition, in the normal direction Y of the circuit board structure 10e, the orthographic projection area of the third build-up circuit layer 260 is substantially equal to the orthographic projection area of the third conductive seed layer region 242.

[0104] Figure 6 This is a cross-sectional view of a circuit board structure according to another embodiment of the present invention. Figure 1G and Figure 6 , Figure 6 The circuit board structure 10f and Figure 1G The main differences between the circuit board structure 10a and the circuit board structure 10e are that the second dielectric layer 160 further has a fourth opening 166 , and the circuit board structure 10e further includes an electronic component 300b and a fourth conductive via 270 .

[0105] Specifically, electronic component 300b is disposed on first non-conductive seed layer region 125 and has an active surface 302b and a back surface 304b facing each other. Fourth conductive via 270 is disposed within fourth opening 166. Second build-up circuit layer 190 is electrically connected to electronic component 300b through fourth conductive via 270 and second conductive seed layer region 172.

[0106] In this embodiment, the method for arranging the electronic component 300b may include the following steps: forming a first non-conductive seed layer region 125 (eg Figure 1F After that, a second dielectric layer 160 is formed on the first build-up circuit layer 150 (as shown in FIG. Figure 1G Before the fabrication process (as shown in FIG. 1 ), an electronic component 300b is disposed on the first non-conductive seed layer region 125. The electronic component 300b does not contact the first build-up circuit layer 150. Furthermore, after forming the second dielectric layer 160 on the first build-up circuit layer 150, the process further includes forming a fourth conductive via 270 within the fourth opening 166, such that the second build-up circuit layer 190 is electrically connected to the electronic component 300b through the fourth conductive via 270 and the second conductive seed layer region 172.

[0107] Figure 7 This is a cross-sectional view of a circuit board structure according to another embodiment of the present invention. Figure 6 and Figure 7 , Figure 7 The circuit board structure 10g and Figure 6 The main difference between the circuit board structure 10f and the circuit board structure 10g is that the circuit board structure 10g further includes a graphene oxide layer 280. The graphene oxide layer 280 is disposed between the electronic component 300b and the second dielectric layer 160.

[0108] Specifically, electronic device 300b further includes a peripheral surface 306b connecting active surface 302b and back surface 304b. Graphene oxide layer 280 is conformally disposed on a portion of active surface 302b and peripheral surface 306b of electronic device 300b. Fourth opening 166 may penetrate second dielectric layer 160 and graphene oxide layer 280 to expose a portion of active surface 302a.

[0109] In this embodiment, the method for forming the graphene oxide layer 280 may include the following steps: forming the first non-conductive seed layer region 125 (eg Figure 1F After that, a second dielectric layer 160 is formed on the first build-up circuit layer 150 (as shown in FIG. Figure 1G ), an electronic device 300b is first disposed on the first non-conductive seed layer region 125. Then, a graphene oxide layer 280 is conformally formed on the electronic device 300b to cover the active surface 302b and the surrounding surface 306b.

[0110] In this embodiment, since the graphene oxide layer 280 directly contacts a portion of the active surface 302 b and the surrounding surface 306 b of the electronic component 300 b , the heat dissipation efficiency of the electronic component 300 b can be further improved.

[0111] In summary, in the circuit board structure of the embodiment of the present invention, since the first non-conductive seed layer region can have good insulation properties, after forming the first build-up circuit layer, it is not necessary to perform an additional etching process to remove the first non-conductive seed layer region. In this way, the existing situation in which the seed layer exposed by the first build-up circuit layer is removed, which causes circuit undercutting, circuit peeling, or circuit shape deformation in the seed layer covered by the first build-up circuit layer, can be avoided, and the reliability of signal transmission or the yield of the product can be effectively improved. In addition, since both the oxidized graphene material and the reduced graphene material have excellent thermal conductivity, compared to the conventional method of conducting heat generated by the inner layer circuit through an embedded heat dissipation copper block, the circuit board structure of this embodiment can also conduct heat generated by the inner layer circuit through the first conductive seed layer region, the first non-conductive seed layer region, the second conductive seed layer region, and / or the second non-conductive seed layer region, thereby making the circuit board structure of this embodiment have better heat dissipation efficiency.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit board structure, characterized in that: include: a circuit layer including a plurality of connection pads; A first dielectric layer is disposed on the circuit layer and has a first opening, wherein the first opening exposes the plurality of connection pads; a first graphene layer, conformally disposed on the first dielectric layer and in the first opening, and having a first conductive seed layer region and a first non-conductive seed layer region; a first conductive hole, disposed in the first opening; a first build-up circuit layer, disposed corresponding to the first conductive seed layer region, wherein the first build-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the plurality of connection pads through the first conductive vias and the first conductive seed layer region; a second dielectric layer disposed on the first build-up circuit layer and covering the first non-conductive seed layer region, wherein the second dielectric layer has a second opening, and the second opening exposes the first build-up circuit layer; a second graphene layer, conformally disposed on the second dielectric layer and in the second opening, and having a second conductive seed layer region and a second non-conductive seed layer region; a second conductive hole, disposed in the second opening; as well as The second build-up circuit layer is arranged corresponding to the second conductive seed layer area, wherein the second build-up circuit layer exposes the second non-conductive seed layer area and is electrically connected to the first build-up circuit layer through the second conductive hole and the second conductive seed layer area.

2. The circuit board structure according to claim 1, characterized in that: The circuit board structure further includes: A graphene oxide layer is conformally disposed on the first build-up circuit layer, wherein the second opening penetrates the graphene oxide layer to expose a portion of a surface of the first build-up circuit layer.

3. The circuit board structure according to claim 1, characterized in that: The circuit board structure further includes: The insulating protection layer is disposed on the second build-up circuit layer and exposes the connection pads of the second build-up circuit layer.

4. The circuit board structure according to claim 1, characterized in that: The circuit board structure further includes: An electronic component is embedded in the second dielectric layer and has an active surface and a back surface opposite to each other, wherein the active surface of the electronic component is electrically connected to the first build-up circuit layer, and the back surface contacts the second graphene layer.

5. The circuit board structure according to claim 4, characterized in that: The electronic component protrudes from the upper surface of the second dielectric layer. The electronic component further has a peripheral surface connecting the active surface and the back surface, and the second graphene layer contacts a portion of the peripheral surface.

6. The circuit board structure according to claim 5, characterized in that: The circuit board structure further includes: a third dielectric layer disposed on the second build-up circuit layer and covering the second non-conductive seed layer region, wherein the third dielectric layer has a third opening, and the third opening exposes the second build-up circuit layer; a third graphene layer, conformally disposed on the third dielectric layer and in the third opening, and having a third conductive seed layer region and a third non-conductive seed layer region; a third conductive via, disposed in the third opening; and The third build-up circuit layer is arranged corresponding to the third conductive seed layer area, wherein the third build-up circuit layer exposes the third non-conductive seed layer area and is electrically connected to the second build-up circuit layer through the third conductive hole and the third conductive seed layer area.

7. The circuit board structure according to claim 1, characterized in that: The second dielectric layer further has a fourth opening, and the circuit board structure further includes: an electronic component disposed on the first non-conductive seed layer region and having an active surface and a back surface opposite to each other; and A fourth conductive via is disposed in the fourth opening, wherein the second build-up circuit layer is electrically connected to the electronic component through the fourth conductive via and the second conductive seed layer region.

8. The circuit board structure according to claim 7, characterized in that: The circuit board structure further includes: A graphene oxide layer is conformally disposed on the electronic component, and the graphene oxide layer is located between the electronic component and the second dielectric layer.

9. A method for manufacturing a circuit board structure, characterized in that: include: A circuit structure is provided, wherein the circuit structure includes a circuit layer and a first dielectric layer, the first dielectric layer is disposed on the circuit layer, and the circuit layer includes a plurality of connection pads; forming a first opening in the first dielectric layer to expose the plurality of connection pads; Conformally forming a first graphene layer on the first dielectric layer and in the first opening, wherein the first graphene layer has a first portion and a second portion; forming a first conductive hole in the first opening; forming a first build-up circuit layer on the first portion to expose the second portion; oxidizing the second portion of the first graphene layer to form a first non-conductive seed layer region, and defining the first portion as a first conductive seed layer region, The first build-up circuit layer is provided corresponding to the first conductive seed layer region, and is electrically connected to the plurality of connection pads through the first conductive via and the first conductive seed layer region; forming a second dielectric layer on the first build-up circuit layer to cover the first non-conductive seed layer region, wherein the second dielectric layer has a second opening to expose the first build-up circuit layer; conformally forming a second graphene layer on the second dielectric layer and in the second opening, wherein the second graphene layer has a third portion and a fourth portion; forming a second conductive hole in the second opening; and forming a second build-up circuit layer on the third portion to expose the fourth portion; and oxidizing the fourth portion of the second graphene layer to form a second non-conductive seed layer region, and defining the third portion as a second conductive seed layer region, The second build-up circuit layer is arranged corresponding to the second conductive seed layer region, and is electrically connected to the first build-up circuit layer through the second conductive via and the second conductive seed layer region.

10. The manufacturing method according to claim 9, characterized in that: The manufacturing method further comprises: An insulating protection layer is formed on the second build-up circuit layer to expose the connection pads of the second build-up circuit layer.

11. The manufacturing method according to claim 9, characterized in that: Before forming the second dielectric layer on the first build-up circuit layer, the method further includes: An electronic component is disposed on the first build-up circuit layer, wherein the electronic component has an active surface and a back surface opposite to each other, the active surface is electrically connected to the first build-up circuit layer, and the back surface faces the second graphene layer.

12. The manufacturing method according to claim 9, characterized in that The second dielectric layer further has a fourth opening, and before forming the second dielectric layer on the first build-up circuit layer, the method further includes: Disposing an electronic component on the first non-conductive seed layer region, wherein the electronic component has an active surface and a back surface opposite to each other, and a peripheral surface connecting the active surface and the back surface, the back surface facing the first non-conductive seed layer region; and Conformally forming a graphene oxide layer on the electronic component to cover the active surface and the surrounding surface; After forming the second dielectric layer on the first build-up circuit layer, the method further includes: A fourth conductive via is formed in the fourth opening, so that the second build-up circuit layer is electrically connected to the electronic component through the fourth conductive via and the second conductive seed layer region.

13. The manufacturing method according to claim 9, characterized in that Before forming the second dielectric layer on the first build-up circuit layer, the method further includes: A graphene oxide layer is conformally formed on the first build-up circuit layer to cover the first build-up circuit layer.

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