Thin film transistor and manufacturing method thereof, array substrate and display device

Abstract

The present disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device, and belongs to the field of display technology. The active layer of the thin film transistor includes at least two stacked metal oxide semiconductor layers, and the at least two oxide semiconductor layers include a channel layer and a first protective layer. The metal in the metal oxide semiconductor layer in the channel layer includes tin element, and at least one of indium element, gallium element, and zinc element. The first protective layer includes praseodymium element, and the praseodymium element in the first protective layer is used to absorb photogenerated electrons in the metal oxide semiconductor and reduce the photogenerated current caused by light. The thin film transistor has high stability and high mobility.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background Art

[0002] Thin Film Transistor (TFT) is the core device of display device. Each pixel in the display device relies on thin film transistor for switching and driving. According to the different semiconductor materials of the active layer of thin film transistor, thin film transistor mainly includes oxide thin film transistor and amorphous silicon thin film transistor. Oxide thin film transistor has high mobility, which can improve the resolution of display device and is more and more widely used in display device.

[0003] The active layer of the oxide thin film transistor is connected to the source and drain of the oxide thin film transistor respectively. When the oxide thin film transistor is working, carriers are generated in the active layer, and the source and drain connected to the active layer are turned on, so that the oxide thin film transistor is turned on and starts working.

[0004] In the related technology, the active layer of the oxide thin film transistor is an oxide semiconductor, but the oxide semiconductor is sensitive to light, and the active layer is easily affected by light. When the active layer is irradiated by light, photogenerated carriers will be generated, causing the originally non-working oxide thin film transistor to turn on, affecting the stability of the oxide thin film transistor. Summary of the invention

[0005] The embodiments of the present disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate and a display device, which improve the stability of the oxide thin film transistor. The technical solution is as follows:

[0006] On the one hand, the present disclosure provides a thin film transistor, which includes an active layer, the active layer includes at least two stacked metal oxide semiconductor layers, the at least two oxide semiconductor layers include a channel layer and a first protective layer, the metal elements in the metal oxide semiconductor layer in the channel layer include tin, and at least one of indium, gallium, and zinc; the first protective layer includes praseodymium, and the praseodymium in the first protective layer is used to absorb photogenerated electrons in the metal oxide semiconductor to reduce the photogenerated current caused by light.

[0007] In one implementation of the embodiment of the present disclosure, the metal elements in the metal oxide semiconductor layer in the channel layer include tin, indium and gallium; the number of indium atoms in the channel layer accounts for 65% to 75% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer; the number of gallium atoms in the channel layer accounts for 24% to 30% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer; the number of tin atoms in the channel layer accounts for 1% to 5% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer.

[0008] In one implementation of the embodiment of the present disclosure, the content of praseodymium atoms in the first protective layer at different thickness positions of the first protective layer is not exactly the same, and the content of praseodymium atoms on the side of the first protective layer away from the channel layer is less than the content of praseodymium atoms on the side of the first protective layer close to the channel layer.

[0009] In an implementation of the embodiment of the present disclosure, the channel layer is doped with praseodymium elements, and in the channel layer, the content of praseodymium atoms in the channel layer decreases monotonically in a direction from close to the first protective layer to far away from the first protective layer.

[0010] In one implementation of the embodiment of the present disclosure, the metal elements in the first protective layer also include at least one of tin, indium, gallium, and zinc, and the number of praseodymium atoms in the first protective layer accounts for between 1% and 50% of the total number of metal element atoms in the first protective layer.

[0011] In one implementation of the embodiment of the present disclosure, the metal elements in the first protective layer also include the indium element, the gallium element and the zinc element; the number of indium atoms in the first protective layer accounts for a ratio of 45% to 55% of the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer; the number of gallium atoms in the first protective layer accounts for a ratio of 25% to 35% of the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer; the number of zinc atoms in the first protective layer accounts for a ratio of 15% to 25% of the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer.

[0012] In an implementation of the embodiment of the present disclosure, the first protective layer is located on a surface of the channel layer away from the substrate.

[0013] In an implementation of the embodiment of the present disclosure, the at least two metal oxide semiconductor layers further include: a second protective layer located on a surface of the channel layer close to the substrate, and the second protective layer contains praseodymium.

[0014] In an implementation of the embodiment of the present disclosure, the second protective layer is an indium gallium zinc oxide layer containing praseodymium, and the number of praseodymium atoms in the second protective layer accounts for a ratio of 1% to 50% of the total number of atoms of metal elements in the second protective layer.

[0015] In one implementation of the embodiment of the present disclosure, the at least two metal oxide semiconductor layers also include: a source and drain layer, located on the surface of the first protective layer away from the substrate; a covering layer, located between the first protective layer and the source and drain layer, and the covering layer is a crystalline oxide layer not doped with praseodymium.

[0016] In an implementation of the embodiment of the present disclosure, the covering layer is a metal crystalline oxide layer, and the metal in the metal crystalline oxide layer includes at least one of indium, gallium, zinc and tin.

[0017] In an implementation of the embodiment of the present disclosure, the thin film transistor further includes: a diffusion layer, the diffusion layer is located on a side of the first protective layer away from the base substrate, and the diffusion layer is a praseodymium metal layer or a praseodymium metal oxide layer.

[0018] In an implementation of the embodiment of the present disclosure, the first protective layer is located on a surface of the channel layer close to the substrate.

[0019] In one implementation of the embodiment of the present disclosure, the thin film transistor also includes: a source electrode and a drain electrode, the source electrode and the drain electrode are located on the active layer, the source electrode and the drain electrode respectively wrap the side walls of the active layer, and the source electrode and the drain electrode are respectively connected to the side walls of the channel layer, and the source electrode and the drain electrode contain praseodymium elements.

[0020] In another aspect, the present disclosure provides a method for manufacturing a thin film transistor, the method comprising:

[0021] A base substrate is provided; at least two metal oxide semiconductor layers are sequentially formed on the base substrate to form an active layer of a thin film transistor, the at least two oxide semiconductor layers include a channel layer and a first protective layer, the metal elements in the metal oxide semiconductor layer in the channel layer include tin, and at least one of indium, gallium, and zinc; the first protective layer includes praseodymium, and the praseodymium in the first protective layer is used to absorb photogenerated electrons in the metal oxide semiconductor to reduce photogenerated current caused by light.

[0022] In an implementation of the embodiment of the present disclosure, at least two metal oxide semiconductor layers are sequentially formed on the base substrate, including: forming an indium gallium tin oxide film layer on the base substrate; forming a diffusion film layer on a side of the indium gallium tin oxide film layer away from the base substrate, wherein the diffusion film layer is a praseodymium metal film layer or a praseodymium metal oxide film layer; annealing the indium gallium tin oxide film layer and the diffusion film layer to diffuse the praseodymium element in the diffusion film layer into the indium gallium tin oxide film layer to obtain an active layer including the channel layer and the first protective layer sequentially stacked on the base substrate; and patterning the diffusion film layer to obtain a diffusion layer located on the active layer, wherein the diffusion layer is located on a side of the first protective layer away from the base substrate, and the diffusion layer is a praseodymium metal layer or a praseodymium metal oxide layer.

[0023] In an implementation manner of the embodiment of the present disclosure, the method further includes: forming a source-drain metal layer on the diffusion layer, the source-drain metal layer containing praseodymium; and patterning the source-drain metal layer to form a source electrode and a drain electrode.

[0024] On the other hand, the present disclosure provides an array substrate, comprising a base substrate and a plurality of thin film transistors on the base substrate, wherein the thin film transistors are the thin film transistors described in any one of the above aspects.

[0025] In one implementation of the embodiment of the present disclosure, the array substrate also includes: a first insulating layer, covering the first protective layer, the source and the drain; a first electrode layer, including a plurality of first electrodes, and the plurality of first electrodes are located on a side of the first insulating layer away from the base substrate; a second insulating layer, covering the plurality of first electrodes; a second electrode layer, located on a side of the second insulating layer away from the base substrate, and the second electrode layer is electrically connected to the source or drain in the corresponding thin film transistor.

[0026] On the other hand, the present disclosure provides a display device, comprising the array substrate described in any one of the above aspects.

[0027] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0028] In the disclosed embodiment, during the operation of the thin film transistor, the channel layer is the main channel region. The first protective layer protects the channel layer. When light shines from the side where the first protective layer is located to the channel layer, the light will first shine on the first protective layer. The first protective layer blocks the light, weakens the influence of the light on the channel layer, and improves the stability of the thin film transistor. When the first protective layer is irradiated with light, photogenerated carriers will also be generated. Since the first protective layer contains praseodymium, the praseodymium element will introduce an intermediate energy level state, also known as a trap state, in the internal band gap of the first protective layer. When the first protective layer is irradiated with light to generate photogenerated carriers, the photogenerated carriers will be captured by the trap state inside the first protective layer, so that the photogenerated carriers are digested inside the first protective layer, which will not affect the function of the actual channel region. In addition, the channel layer contains tin elements, which can increase the mobility of the thin film transistor, thereby increasing the reaction speed of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0031] Figure 2 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0032] Figure 3 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0034] Figure 5 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure;

[0036] Figure 7 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0037] Figure 8 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0038] Fig. 9 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment;

[0039] Fig.10 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment;

[0040] Fig.11 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment;

[0041] Fig.12 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment;

[0042] Fig.13 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment;

[0043] Fig.14 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0044] Fig.15 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0045] Fig.16 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0046] Fig.17 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0047] Fig.18 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0048] Fig.19 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0049] Fig. 20 It is a schematic diagram of the cross-sectional structure of an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0051] The present disclosure provides a thin film transistor, Figure 1 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 1The active layer 10 of the thin film transistor includes at least two stacked metal oxide semiconductor layers, and the at least two oxide semiconductor layers include at least a channel layer 101 and a first protective layer 102, wherein the metal in the metal oxide semiconductor layer in the channel layer 101 includes tin (Sn) element, and includes at least one of indium (In) element, gallium (Ga) element, and zinc (Zn) element. The first protective layer 102 includes praseodymium element, and the praseodymium element in the first protective layer 102 is used to absorb photogenerated electrons in the metal oxide semiconductor and reduce the photogenerated current caused by light.

[0052] Optionally, the thin film transistor is a top gate, bottom gate or double gate structure. The top gate structure means that the gate is located on the side of the active layer away from the substrate, the bottom gate structure means that the gate is located on the side of the active layer close to the substrate, and the double gate structure means that the thin film transistor includes two gates located in different layers, the two gates are separated by a gate insulating layer, and the two gates are both located on the side of the active layer away from the substrate or the two gates are both located on the side of the active layer close to the substrate.

[0053] In the embodiment of the present disclosure, during the operation of the thin film transistor, the channel layer 101 is the actual channel region. The first protective layer 102 protects the channel layer 101. When light is irradiated from the side where the first protective layer 102 is located to the channel layer 101, the light will first irradiate the first protective layer 102. The first protective layer 102 blocks the light, weakens the effect of the light on the channel layer 101, and improves the stability of the thin film transistor. When the first protective layer 102 is irradiated with light, photogenerated carriers will also be generated. Since the first protective layer 102 contains praseodymium, the praseodymium element will introduce an intermediate energy level state, also called a trap state, in the internal band gap of the first protective layer 102. When the first protective layer 102 is irradiated with light to generate photogenerated carriers, the photogenerated carriers will be captured by the trap state inside the first protective layer 102, so that the photogenerated carriers are digested inside the first protective layer 102, and will not affect the function of the actual channel region. Furthermore, the channel layer 101 contains tin elements, which can improve the mobility of the thin film transistor, thereby improving the response speed of the thin film transistor.

[0054] Since the active layer of the thin film transistor provided in the embodiment of the present disclosure is made of oxide, the thin film transistor is called an oxide thin film transistor.

[0055] In one implementation of the embodiment of the present disclosure, the metal elements in the metal oxide semiconductor layer in the channel layer 101 include tin, indium and gallium. The number of indium atoms in the channel layer 101 accounts for 65% to 75% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101. The number of gallium atoms in the channel layer 101 accounts for 24% to 30% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101. The number of tin atoms in the channel layer 101 accounts for 1% to 5% of the total number of indium atoms, gallium atoms and tin atoms in the channel layer 101.

[0056] In one implementation of the embodiment of the present disclosure, the ratio of the number of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is between 90:20:1 and 20:10:1. The ratio is determined based on the proportions of the indium atoms, gallium atoms, and tin atoms.

[0057] The mobility of the channel layer 101 varies with the ratio of the elements in the channel layer 101. By configuring the elements in the channel layer 101 according to the above ratios, the mobility of the thin film transistor can reach 30 square centimeters / volt·second (cm 2 / (V·S)) to 50 square centimeters / volt·second, further improving the mobility of the thin film transistor. The channel layer 101 configured with the above atomic number ratio is in a crystalline state.

[0058] In some examples, the ratio of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is 57:21:2. In other examples, the ratio of indium atoms, gallium atoms, and tin atoms in the channel layer 101 is 29:11:1.

[0059] It should be noted that, due to errors in the preparation process, the number ratio of each atom in the channel layer 101 fluctuates, and the number ratio of each atom fluctuates within the range of ±10%.

[0060] For example, in the channel layer 101, the ratio of indium atoms, gallium atoms, and tin atoms is 29:11:1, and the floating range of the ratio of indium atoms in the channel layer 101 is ±5%. At this time, in the channel layer 101, the ratio of indium atoms, gallium atoms, and tin atoms is between 27.55:11:1 and 30.45:11:1. For example, the ratio of indium atoms, gallium atoms, and tin atoms is 30:11:1.

[0061] In the embodiment of the present disclosure, the thickness of the channel layer 101 is less than 30 nanometers (nm), for example, 25 nanometers.

[0062] In the embodiment of the present disclosure, the thickness of the first protection layer 102 is less than 20 nanometers (nm), for example, 20 nanometers.

[0063] In an implementation of the embodiment of the present disclosure, the metal element of the first protective layer 102 further includes at least one of tin, indium, gallium, and zinc.

[0064] Exemplarily, the first protection layer 102 is an indium gallium zinc oxide (IGZO) layer doped with praseodymium.

[0065] Indium gallium zinc oxide is easily available, and doping the indium gallium zinc oxide with praseodymium can enable the first protective layer 102 to protect the channel layer 101 when exposed to light.

[0066] In one implementation of the embodiment of the present disclosure, the number of indium atoms in the first protective layer 102 accounts for 45% to 55% of the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102; the number of gallium atoms in the first protective layer 102 accounts for 25% to 35% of the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102; the number of zinc atoms in the first protective layer 102 accounts for 15% to 25% of the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102.

[0067] In the embodiment of the present disclosure, the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 is between 6:3:1 and 3:3:1. The ratio is determined based on the proportion of the above-mentioned indium atoms, gallium atoms, and zinc atoms.

[0068] In some examples, the ratio of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 is 46:29:21. In other examples, the ratio of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 is 23:14:10.

[0069] In an implementation of the embodiment of the present disclosure, the number of praseodymium atoms in the first protective layer 102 accounts for between 1% and 50% of the total number of metal element atoms in the first protective layer 102 .

[0070] Praseodymium is easy to obtain and cheap, which reduces the production cost. After praseodymium is doped into indium gallium zinc oxide, it will form an intermediate energy level inside the indium gallium zinc oxide, which accelerates the recombination of photogenerated carriers. This intermediate energy level is called trivalent praseodymium (Pr3 + ) trap state. The trap state can provide an electron recombination step. When InGaZnO is irradiated by light to generate photogenerated carriers (i.e., photogenerated charges), the photogenerated carriers will be quickly captured by the trivalent praseodymium trap state. The photogenerated carriers recombine with the electron recombination step, which reduces the lifetime of the photogenerated carriers, reduces the concentration of the photogenerated carriers, and allows the photogenerated carriers to be digested internally, which will not affect the channel layer, thereby improving the light stability and mobility of the thin film transistor.

[0071] At the same time, the content ratio of the doped praseodymium element is controlled to ensure that the first protective layer 102 achieves the best protective effect, protects the channel layer 101, and further improves the light stability of the thin film transistor.

[0072] Exemplarily, the number of praseodymium atoms in the first protective layer 102 accounts for 5% of the total number of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 .

[0073] In some examples, the ratio of indium atoms, gallium atoms, zinc atoms, and praseodymium atoms in the first protective layer 102 is 46:29:21:4. In other examples, the ratio of indium atoms, gallium atoms, zinc atoms, and praseodymium atoms in the first protective layer 102 is 23:14:10:2.

[0074] Likewise, the number ratio of each atom in the first protective layer 102 also fluctuates, and the number ratio of each atom also fluctuates within the range of ±10%.

[0075] In the embodiment of the present disclosure, the content ratio of the praseodymium element refers to the ratio of the number of praseodymium atoms to the number of atoms of all metal elements in the first protective layer 102 .

[0076] In the embodiment of the present disclosure, the content of praseodymium atoms in the first protective layer 102 at different thickness positions of the first protective layer 102 is not exactly the same, and the content of praseodymium atoms on the side of the first protective layer 102 away from the channel layer 101 is less than the content of praseodymium atoms on the side of the first protective layer 102 close to the channel layer 101.

[0077] Alternatively, in other implementations, the first protection layer 102 is a praseodymium oxide (Pr-Oxide) layer, for example, a praseodymium trioxide (Pr 2 O 3 ) layer.

[0078] In the embodiment of the present disclosure, the channel layer 101 contains praseodymium, and the percentage of the number of atoms of the praseodymium element in the channel layer 101 to the number of atoms of all metal elements in the channel layer 101 is smaller than the percentage of the number of atoms of the praseodymium element in the first protective layer 102 to the number of atoms of all metal elements in the first protective layer 102.

[0079] During the process of manufacturing the active layer 10, an annealing treatment is required, and the praseodymium element in the first protective layer 102 may be doped into the channel layer 101 during the annealing process, so that the channel layer 101 also contains the praseodymium element. However, since the praseodymium element is doped into the channel layer 101 from the first protective layer 102, the content ratio of the praseodymium element in the channel layer 101 is less than the content ratio of the praseodymium element in the first protective layer 102.

[0080] Meanwhile, in the channel layer 101 , the content ratio of the praseodymium element contained in the channel layer 101 decreases in a direction from close to the first protective layer 102 to far away from the first protective layer 102 .

[0081] Exemplarily, the number of praseodymium atoms in the channel layer 101 accounts for 2% of the total number of indium atoms, gallium atoms, and tin atoms in the channel layer 101 .

[0082] See again Figure 1 , the active layer 10 is located on the base substrate 30 . The first protection layer 102 is located on the surface of the channel layer 101 away from the base substrate 30 .

[0083] During the operation of the thin film transistor, more light is irradiated to the channel layer 101 from the side of the surface away from the substrate 30. The first protective layer 102 is arranged on the surface of the channel layer 101 away from the substrate 30, so that the first protective layer 102 blocks the ambient light irradiated to the channel layer 101 from the side of the surface away from the substrate 30, thereby reducing the influence of the light on the channel layer 101. At the same time, when the praseodymium element in the first protective layer 102 diffuses into the channel layer 101, the praseodymium element in the side of the channel layer 101 close to the substrate 30 is less, thereby avoiding reducing the stability of the thin film transistor.

[0084] See again Figure 1 The thin film transistor further includes a source drain (SD) layer 50. The source drain layer 50 includes a source 501 and a drain 502, the source 501 and the drain 502 are located on the active layer 10, the source 501 and the drain 502 respectively wrap the sidewalls of the active layer 10, and the source 501 and the drain 502 are respectively connected to the sidewalls of the channel layer 101.

[0085] For a thin film transistor, the source 501 and the drain 502 in the source-drain layer 50 need to be connected to the channel layer 101 respectively. When the thin film transistor is working, the source 501 and the drain 502 are connected through the channel layer 101. Figure 1 In the embodiment, since the channel layer 101 is located below the first protective layer 102, the source 501 and the drain 502 cannot be connected to the channel layer 101 from above the channel layer 101, and the source 501 and the drain 502 respectively wrap the side walls of the active layer 10, that is, the source 501 and the drain 502 are connected to the channel layer 101 through the side walls of the channel layer 101.

[0086] In the embodiment of the present disclosure, the source-drain electrode layer 50 is a metal layer or an indium tin oxide (ITO) layer to ensure the conductivity of the source-drain electrode layer 50 .

[0087] See again Figure 1The thin film transistor further includes a gate 60 and a gate insulator (GI) layer 70. The gate 60 is located on a side of the active layer 10 close to the substrate 30. The gate insulator 70 is located between the active layer 10 and the gate 60 to separate the active layer 10 from the gate 60.

[0088] Exemplarily, the gate 60 is made of metal, such as copper, or the gate 60 is made of a transparent conductive material, such as indium tin oxide.

[0089] In the embodiment of the present disclosure, the gate 60 and the first protective layer 102 are respectively located on two sides of the channel layer 101 , and the gate 60 and the first protective layer 102 can shield the channel layer 101 from light from two sides.

[0090] Exemplarily, the gate insulating layer 70 is silicon oxide, silicon nitride or epoxy resin.

[0091] like Figure 1 As shown, the thin film transistor further includes a first insulating layer (PVX) 80 . The first insulating layer 80 covers the first protection layer 102 and the source-drain electrode layer 50 .

[0092] The first insulating layer 80 is arranged to separate the source-drain electrode layer 50 from the film layer located above the source-drain electrode layer 50 to avoid affecting the transmission of electrical signals in the source-drain electrode layer 50 .

[0093] Exemplarily, the first insulating layer 80 is a silicon oxide layer.

[0094] In the embodiment of the present disclosure, since the first insulating layer 80 is generally a silicon oxide layer, the first insulating layer 80 contains silicon elements, and the channel layer 101 is an indium gallium tin oxide layer, the channel layer 101 does not contain silicon elements, if the channel layer 101 directly contacts the first insulating layer 80, an interface state will be generated at the contact surface between the channel layer 101 and the first insulating layer 80, affecting the mobility of the thin film transistor. The first insulating layer 80 and the channel layer 101 are separated by the first protective layer 102 that does not contain silicon elements, which can avoid the influence of the interface state on the mobility of the thin film transistor.

[0095] Figure 1 The thin film transistor shown is a bottom-gate thin film transistor. In other implementations, the thin film transistor may also be a top-gate thin film transistor. For specific structures, see Figure 2 .

[0096] Figure 2 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 2The gate insulating layer 70 is located on the side of the first protective layer 102 away from the base substrate 30, and the gate 60 is located on the side of the gate insulating layer 70 away from the base substrate 30, that is, the gate 60 is located above the active layer 10, which is a top-gate thin film transistor.

[0097] See again Figure 2 For a top-gate thin film transistor, the first protective layer 102 separates the gate insulating layer 70 from the channel layer 101 to prevent the channel layer 101 from directly contacting the gate insulating layer 70 and generating an interface state between the gate insulating layer 70 and the channel layer 101, thereby affecting the mobility of the thin film transistor.

[0098] See again Figure 2 The thin film transistor also includes an interlayer dielectric (ILD) layer 120 , which wraps the gate 60 and the active layer 10 , and the source-drain electrode layer 50 is located on the interlayer dielectric layer 120 , that is, the gate 60 and the source-drain electrode layer 50 are separated by the interlayer dielectric layer 120 .

[0099] By way of example, the interlayer dielectric layer 120 is a silicon oxide layer, a silicon nitride layer or an epoxy resin layer.

[0100] See again Figure 2 The thin film transistor further includes a shield layer 130 and a buffer layer 140 . The shield layer 130 and the buffer layer 140 are both located on the substrate. The shield layer 130 is opposite to the channel layer 101 , and the buffer layer 140 is located between the shield layer 130 and the channel layer 101 .

[0101] In the embodiment of the present disclosure, the light shielding layer 130 may be arranged to shield the light irradiated from one side of the light shielding layer 130 to the channel layer 101 , thereby reducing the influence of the light on the channel layer 101 .

[0102] The channel layer 101 is arranged on the buffer layer 140 to reduce the influence of impurities on the base substrate 30 on the channel layer 101 .

[0103] Figure 3 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 3 The at least two metal oxide semiconductor layers further include a second protective layer 103. The second protective layer 103 is located on a surface of the channel layer 101 close to the base substrate 30, and the second protective layer 103 contains praseodymium.

[0104] During the operation of the thin film transistor, both sides of the channel layer 101 will be exposed to light, such as ambient light, light from a light-emitting unit, or light from a backlight. A first protective layer is arranged on both surfaces of the channel layer 101, and the second protective layer 103 is also doped with praseodymium. The second protective layer 103 has the same function as the first protective layer 102. When light irradiates the channel layer 101 from two opposite surfaces of the channel layer 101, the first protective layer 102 and the second protective layer 103 can both protect the channel layer 101 and improve the stability of the thin film transistor.

[0105] In the embodiment of the present disclosure, when the first protective layer 102 and the second protective layer 103 are respectively arranged on two opposite surfaces of the channel layer 101, the first protective layer 102 separates the channel layer 101 from the first insulating layer 80, and the second protective layer 103 separates the channel layer 101 from the gate insulating layer 70, which can simultaneously avoid the formation of interface states on the two surfaces of the channel layer 101 and avoid affecting the stability of the thin film transistor.

[0106] In one implementation of the present disclosure, the second protective layer 103 is an indium gallium zinc oxide layer containing praseodymium. The number of praseodymium atoms in the second protective layer 103 accounts for between 1% and 50% of the total number of indium atoms, gallium atoms and zinc atoms in the second protective layer 103.

[0107] In the embodiment of the present disclosure, the ratio of indium atoms, gallium atoms, and zinc atoms in the second protective layer 103 is the same as the ratio of indium atoms, gallium atoms, and zinc atoms in the first protective layer 102 .

[0108] Exemplarily, the number ratio of indium atoms, gallium atoms, and zinc atoms in the second protection layer 103 is between 6:3:1 and 3:3:1.

[0109] For example, the ratio of indium atoms, gallium atoms, and zinc atoms in the second protective layer 103 is 4:3:2. The number of praseodymium atoms in the second protective layer 103 accounts for 20% of the total number of indium atoms, gallium atoms, and zinc atoms in the second protective layer 103 .

[0110] Similarly, the number ratio of each atom in the second protective layer 103 also fluctuates, and the number ratio of each atom also fluctuates within the range of ±10%.

[0111] Alternatively, the second protective layer 103 is a praseodymium oxide layer, for example, a praseodymium trioxide layer.

[0112] Figure 4 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 4The at least two metal oxide semiconductor layers further include a capping layer 104. The capping layer 104 is located on a side of the first protective layer 102 away from the substrate 30. The capping layer 104 is a crystalline oxide layer not doped with praseodymium. The capping layer 104 is located between the source and drain electrode layer 50 and the first protective layer 102.

[0113] In the embodiment of the present disclosure, a capping layer 104 is arranged on the first protective layer 102, and the capping layer 104 can improve the stability of the thin film transistor under high temperature and high voltage. At the same time, when the source and drain are etched, the crystalline oxide layer can reduce the impact of etching on the active layer 10, thereby improving the stability of the thin film transistor.

[0114] In the embodiment of the present disclosure, the capping layer 104 is a metal crystalline oxide layer, and the metal in the metal crystalline oxide layer includes at least one of indium, gallium, zinc and tin.

[0115] Exemplarily, the capping layer 104 is any one of an indium gallium zinc oxide (IGZO) layer, an indium gallium oxide (IGZ) layer, an indium gallium zinc tin oxide (IGZTO) layer, an indium tin oxide (ITO) layer, and an indium zinc oxide (IZO) layer.

[0116] Indium gallium zinc oxide, indium gallium oxide, indium gallium zinc tin oxide, indium tin oxide and indium zinc oxide are all commonly used materials for making thin film transistors. They are easy to obtain and reduce the cost of production.

[0117] Figure 5 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 5 The thin film transistor further includes a diffusion layer 40. The diffusion layer 40 is located on a side of the first protective layer 102 away from the base substrate 30, and the diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.

[0118] In the embodiment of the present disclosure, the diffusion layer 40 is a product of manufacturing the first protective layer 102. The diffusion layer 40 is arranged on an untreated carrier transport film layer. When the untreated carrier transport film layer is subjected to high-temperature annealing, during the annealing process, the praseodymium element in the diffusion layer 40 will be doped into the untreated active layer, so that the untreated carrier transport film layer forms a first protective layer 102 containing praseodymium elements on a side close to the diffusion layer 40, and forms a channel layer 101 serving as a channel region on a side away from the diffusion layer 40.

[0119] See again Figure 5 , and the diffusion layer 40 wraps the side wall of the active layer 10 , and when the source and drain layer 50 is etched, the diffusion layer 40 can protect the active layer 10 .

[0120] See again Figure 5The diffusion layer 40 includes two parts disconnected from each other, and the diffusion layer 40 is located between the source-drain electrode layer 50 and the active layer 10. Since the two parts of the diffusion layer 40 are disconnected from each other, the diffusion layer 40 is prevented from connecting the source electrode 501 and the drain electrode 502 in the source-drain electrode layer 50. In this case, the diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.

[0121] Alternatively, in other implementations, the diffusion layer 40 may also be an integral structure, that is, covering the first protective layer 102 . In this case, the diffusion layer is a praseodymium metal oxide layer.

[0122] It should be noted that, in other embodiments, Figure 5 The diffusion layer 40 is not removed on the basis of the present invention, but the praseodymium element is included in the source electrode 501 and the drain electrode 502. The praseodymium element in the source electrode 501 and the drain electrode 502 is diffused into the active layer 10. Exemplarily, the source and drain electrode layers are a metal compound doped with praseodymium metal, or a praseodymium metal film superimposed with other metal film layers, such as a praseodymium metal layer and a copper metal layer superimposed.

[0123] It should be noted that, in other embodiments, the diffusion layer 40 may not wrap the side wall of the active layer 10, the diffusion layer 40 is stacked with the active layer 10, and the diffusion layer 40 is located on the side of the active layer 10 away from the base substrate 30. The source electrode 501 and the drain electrode 502 wrap the side walls of the active layer 10 and the diffusion layer 40 respectively.

[0124] Figure 6 is a schematic diagram of a cross-sectional structure of a thin film transistor provided by an embodiment of the present disclosure. Figure 1 The structure shown differs in that Figure 6 The first protection layer 102 is located on a surface of the channel layer 101 close to the base substrate 30 .

[0125] The present disclosure also provides a method for manufacturing a thin film transistor. Figure 7 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. Figure 7 , the method comprising:

[0126] In step S11 , a base substrate is provided.

[0127] In step S12, at least two metal oxide semiconductor layers are sequentially formed on the substrate to form an active layer of a thin film transistor, wherein the at least two oxide semiconductor layers include a channel layer and a first protective layer, wherein the metal in the metal oxide semiconductor layer in the channel layer includes tin and at least one of indium, gallium, and zinc; and the first protective layer includes praseodymium, and the praseodymium in the first protective layer is used to absorb photogenerated electrons in the metal oxide semiconductor to reduce photogenerated current caused by light.

[0128] Figure 8 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. Figure 8 , the method comprising:

[0129] In step S21 , a base substrate is provided.

[0130] Figures 9 to 13 1 is a process diagram of a method for manufacturing a thin film transistor provided in a disclosed embodiment. Figures 9 to 13 The manufacturing process of the substrate is introduced.

[0131] See also Fig. 9 , providing a base substrate 30.

[0132] In step S22, a gate is formed on the base substrate.

[0133] See also Fig.10 , a gate 60 is manufactured on the base substrate 30 .

[0134] In the embodiment of the present disclosure, the gate 60 is a metal electrode.

[0135] For example, a gate film layer may be fabricated on the base substrate 30 by a deposition method, and then the gate film layer may be patterned to obtain the gate 60 .

[0136] In step S23 , a gate insulating layer is formed on the gate.

[0137] See also Fig.11 , a gate insulating layer 70 is formed on the gate 60 , and the gate insulating layer 70 wraps the gate 60 .

[0138] In the embodiment of the present disclosure, the gate insulating layer 70 is a silicon oxide layer.

[0139] For example, the gate insulating layer 70 may be formed on the gate 60 by a deposition method.

[0140] In step S24 , an active layer is formed on the gate insulating layer.

[0141] See also Fig.12 , an active layer 10 is formed on the gate insulating layer 70 .

[0142] In the embodiment of the present disclosure, the active layer 10 includes a channel layer 101 and a first protective layer 102 . The channel layer 101 is made of indium gallium tin oxide, and the first protective layer 102 is made of indium gallium zinc oxide containing praseodymium.

[0143] For example, a layer of indium gallium tin oxide film may be sputtered on the gate insulating layer 70, and then an indium gallium zinc oxide film containing praseodymium may be formed on the indium gallium tin oxide film layer. Then, the indium gallium tin oxide film layer and the indium gallium zinc oxide film layer containing praseodymium may be patterned to obtain the following: Fig.12 The channel layer 101 and the first protective layer 102 are shown.

[0144] In step S25 , a source-drain layer is formed on the active layer.

[0145] See also Fig.13 A source-drain electrode layer 50 is fabricated on the active layer 10 , and the source-drain electrode layer 50 includes a source electrode 501 and a drain electrode 502 . The source electrode 501 and the drain electrode 502 are located on the active layer 10 , and the source electrode 501 and the drain electrode 502 respectively wrap the side walls of the active layer 10 , and the source electrode 501 and the drain electrode 502 are respectively connected to the side walls of the channel layer 101 .

[0146] In the embodiment of the present disclosure, the source-drain electrode layer 50 is a metal layer, and a metal film layer can be formed on the active layer 10 by sputtering, and then the metal film layer is patterned to obtain Fig.13 A source 501 and a drain 502 are shown.

[0147] In step S26 , a first insulating layer is formed on the source and drain electrode layer.

[0148] A first insulating layer 80 is sequentially formed on the source-drain electrode layer 50 to obtain Figure 1 The substrate substrate is shown.

[0149] Fig.14 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. Fig.14 , the method comprising:

[0150] In step S31 , a base substrate is provided.

[0151] In step S32, a gate is formed on the base substrate.

[0152] In step S33 , a gate insulating layer is formed on the gate.

[0153] In step S34, an indium gallium tin oxide film layer is formed on the gate insulating layer.

[0154] Figures 15 to 19 1 is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. Figures 15 to 19 This article introduces the manufacturing process of thin film transistors. Fig.15 , an indium gallium tin oxide film layer 170 is formed on the gate insulating layer 70 .

[0155] In step S35, a diffusion film layer is formed on a side of the InGaSnO film layer away from the substrate. The diffusion film layer is a praseodymium metal film layer or a praseodymium metal oxide film layer.

[0156] See also Fig.16 , a diffusion film layer 180 is formed on the InGaTnO film layer 170 .

[0157] In step S36, the InGaSnO film layer and the diffusion film layer are annealed to diffuse the praseodymium element in the diffusion film layer into the InGaSnO film layer, thereby obtaining an active layer including a channel layer and a first protective layer sequentially stacked on the substrate.

[0158] See also Fig.17 The InGaSnO film layer 170 and the diffusion film layer 180 are annealed simultaneously to diffuse the praseodymium element in the diffusion film layer 180 into the InGaSnO film layer 170 , thereby forming an active layer including the channel layer 101 and the first protective layer 102 in the InGaSnO film layer 170 .

[0159] In step S37, the diffusion film layer is patterned to obtain a diffusion layer located on the active layer.

[0160] See also Fig.18 The diffusion film layer is patterned to obtain a diffusion layer 40 located on the active layer. The diffusion layer 40 is located on the side of the first protective layer 102 away from the base substrate 30, and the diffusion layer 40 wraps the side wall of the active layer 10. The diffusion layer 40 is a praseodymium metal layer or a praseodymium metal oxide layer.

[0161] It should be noted that, in other embodiments, the InGaSn oxide film layer 170 and the diffusion film layer 180 can be etched at the same time to simplify the manufacturing process. That is, a diffusion film layer 180 is directly formed on the InGaSn oxide film layer 170, and then the InGaSn oxide film layer 170 and the diffusion film layer 180 are patterned at the same time to form the active layer 10 and the diffusion layer 40. At this time, the diffusion layer 40 does not wrap the side wall of the active layer 10, the diffusion layer 40 is stacked with the active layer 10, and the diffusion layer 40 is located on the side of the active layer 10 away from the base substrate 30.

[0162] In step S38 , a source-drain metal layer is formed on the diffusion film layer.

[0163] In step S39, the source-drain metal layer is patterned to form a source electrode and a drain electrode.

[0164] See also Fig.19 After the source-drain metal layer is formed on the diffusion film layer 180, the source-drain metal layer is patterned to obtain the following Fig.19 The source and drain layer 50 is shown.

[0165] In step S40 , a first insulating layer is formed on the source and drain electrode layer.

[0166] A first insulating layer 80 is formed on the source-drain electrode layer 50 to obtain Figure 5 The substrate substrate is shown.

[0167] It should be noted that, in other embodiments, steps S35 to S37 may be omitted, and a source-drain metal layer may be directly formed on the InGaTnOx film layer, the source-drain metal layer may contain praseodymium, and then the source-drain metal layer may be patterned, the praseodymium in the source-drain metal layer may be diffused into the InGaTnOx film layer, and an active layer including a channel layer and a first protective layer may be formed in the InGaTnOx film layer.

[0168] The embodiment of the present disclosure also provides an array substrate, which includes a stacked base substrate 30 and a plurality of thin film transistors. Figures 1 to 7 A thin film transistor as shown in any of the figures.

[0169] Fig. 20 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure. Fig. 20 The array substrate further includes: a first electrode layer 90, a second insulating layer 100, and a second electrode layer 110. The first electrode layer 90 includes a plurality of first electrodes, and the plurality of first electrodes are located on a side of the first insulating layer 80 away from the base substrate 30. The second insulating layer 100 covers the plurality of first electrodes. The second electrode layer 110 is located on a side of the second insulating layer 100 away from the base substrate 30, and the second electrode layer 110 is electrically connected to the source 501 or the drain 502 in the corresponding thin film transistor.

[0170] The array substrate provided in the embodiment of the present disclosure can be used in a liquid crystal display (LCD) device. In this case, one of the first electrode layer 90 and the second electrode layer 110 is a pixel electrode layer, and the other is a common electrode layer. The second insulating layer 100 separates the first electrode layer 90 and the second electrode layer 110.

[0171] In the embodiment of the present disclosure, the first electrode layer 90 and the second electrode layer 110 are indium tin oxide layers, which ensures the conductivity and transparency of the first electrode layer 90 and the second electrode layer 110 .

[0172] See again Fig. 20 The array substrate further includes a planarization layer 150, which is located between the first insulating layer 80 and the first electrode layer 90. The planarization layer 150 can make the surface on which the first insulating layer 80 is arranged more flat, and facilitates the manufacture of the first electrode layer 90.

[0173] In the embodiment of the present disclosure, the planarization layer 150 is a resin layer.

[0174] See again Fig. 20 The first insulating layer 80 , the planarizing layer 150 and the second insulating layer 100 have via holes 160 , and the second electrode layer 110 is electrically connected to the source electrode 501 or the drain electrode 502 in the source-drain electrode layer 50 through the via holes 160 .

[0175] The present disclosure also provides a display device, which includes Fig. 20 The array substrate shown.

[0176] In specific implementation, the display device provided in the embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0177] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A thin film transistor, characterized in that: The thin film transistor comprises an active layer (10), the active layer comprises at least two stacked metal oxide semiconductor layers, the at least two metal oxide semiconductor layers comprise a channel layer (101) and a first protective layer (102), the metal element in the metal oxide semiconductor layer in the channel layer (101) comprises tin, and comprises at least one of indium, gallium and zinc; the first protective layer (102) comprises praseodymium, and the praseodymium in the first protective layer (102) is used to absorb photogenerated electrons in the metal oxide semiconductor to reduce photogenerated current caused by light; The content of praseodymium atoms in the first protective layer (102) at different thickness positions of the first protective layer (102) is not completely the same, and the content of praseodymium atoms on a side of the first protective layer (102) away from the channel layer (101) is less than the content of praseodymium atoms on a side of the first protective layer (102) close to the channel layer (101).

2. The thin film transistor according to claim 1, characterized in that: The metal elements in the metal oxide semiconductor layer in the channel layer (101) include tin, indium and gallium; The ratio of the number of indium atoms in the channel layer (101) to the total number of indium atoms, gallium atoms and tin atoms in the channel layer (101) is between 65% and 75%; The ratio of the number of gallium atoms in the channel layer (101) to the total number of indium atoms, gallium atoms and tin atoms in the channel layer (101) is between 24% and 30%; The ratio of the number of tin atoms in the channel layer (101) to the total number of indium atoms, gallium atoms and tin atoms in the channel layer (101) is between 1% and 5%.

3. The thin film transistor according to claim 1, characterized in that: The channel layer (101) is doped with praseodymium elements, and in the channel layer (101), in a direction from close to the first protective layer (102) to far away from the first protective layer (102), the content of praseodymium atoms in the channel layer (101) decreases monotonically.

4. The thin film transistor according to claim 2, characterized in that: The channel layer (101) is doped with praseodymium elements, and in the channel layer (101), in a direction from close to the first protective layer (102) to far away from the first protective layer (102), the content of praseodymium atoms in the channel layer (101) decreases monotonically.

5. The thin film transistor according to any one of claims 1 to 4, characterized in that: The metal element in the first protective layer (102) further comprises at least one of tin, indium, gallium and zinc, and the number of praseodymium atoms in the first protective layer (102) accounts for between 1% and 50% of the total number of metal element atoms in the first protective layer (102).

6. The thin film transistor according to claim 5, characterized in that: The metal elements in the first protective layer (102) further include the indium element, the gallium element and the zinc element; The ratio of the number of indium atoms in the first protective layer (102) to the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer (102) is between 45% and 55%; The ratio of the number of gallium atoms in the first protective layer (102) to the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer (102) is between 25% and 35%; The ratio of the number of zinc atoms in the first protective layer (102) to the total number of indium atoms, gallium atoms and zinc atoms in the first protective layer (102) is between 15% and 25%.

7. The thin film transistor according to any one of claims 1 to 4, characterized in that: The first protective layer (102) is located on a surface of the channel layer (101) that is away from the substrate (30).

8. The thin film transistor according to claim 6, characterized in that: The first protective layer (102) is located on a surface of the channel layer (101) that is away from the substrate (30).

9. The thin film transistor according to claim 7, characterized in that: The at least two metal oxide semiconductor layers further include: The second protective layer (103) is located on a surface of the channel layer (101) close to the substrate (30), and the second protective layer (103) contains praseodymium.

10. The thin film transistor according to claim 9, characterized in that: The second protective layer (103) is an indium gallium zinc oxide layer containing praseodymium; The ratio of the number of praseodymium atoms in the second protective layer (103) to the total number of atoms of metal elements in the second protective layer (103) is between 1% and 50%.

11. The thin film transistor according to claim 7, characterized in that: The at least two metal oxide semiconductor layers further include: A source-drain electrode layer (50) located on a surface of the first protective layer (102) away from the substrate (30); The covering layer (104) is located between the first protection layer (102) and the source-drain electrode layer (50), and the covering layer (104) is a crystalline oxide layer not doped with praseodymium.

12. The thin film transistor according to claim 11, characterized in that: The covering layer (104) is a metal crystalline oxide layer, and the metal in the metal crystalline oxide layer includes at least one of indium, gallium, zinc and tin.

13. The thin film transistor according to claim 7, characterized in that: The thin film transistor further comprises: A diffusion layer (40), the diffusion layer (40) being located on a side of the first protective layer (102) away from the base substrate (30), and the diffusion layer (40) being a praseodymium metal layer or a praseodymium metal oxide layer.

14. The thin film transistor according to any one of claims 1 to 4, characterized in that: The first protective layer (102) is located on a surface of the channel layer (101) close to the substrate (30).

15. The thin film transistor according to claim 6, characterized in that: The first protective layer (102) is located on a surface of the channel layer (101) close to the substrate (30).

16. The thin film transistor according to claim 7, characterized in that: The thin film transistor further comprises: A source electrode (501) and a drain electrode (502), the source electrode (501) and the drain electrode (502) being located on the active layer (10), the source electrode (501) and the drain electrode (502) respectively wrapping the side wall of the active layer (10), and the source electrode (501) and the drain electrode (502) are respectively connected to the side wall of the channel layer (101), and the source electrode (501) and the drain electrode (502) contain praseodymium element.

17. A method for manufacturing a thin film transistor, characterized in that: The method comprises: Providing a substrate; At least two metal oxide semiconductor layers are sequentially formed on the substrate to form an active layer of a thin film transistor, wherein the at least two metal oxide semiconductor layers include a channel layer and a first protective layer, wherein the metal elements in the metal oxide semiconductor layer in the channel layer include tin and at least one of indium, gallium and zinc; the first protective layer includes praseodymium, and the praseodymium in the first protective layer is used to absorb photogenerated electrons in the metal oxide semiconductor to reduce the photogenerated current caused by light; wherein the content of praseodymium atoms in the first protective layer at different thickness positions of the first protective layer is not completely the same, and the content of praseodymium atoms on the side of the first protective layer away from the channel layer is less than the content of praseodymium atoms on the side of the first protective layer close to the channel layer.

18. The method according to claim 17, characterized in that At least two metal oxide semiconductor layers are sequentially formed on the substrate, including: forming an indium gallium tin oxide film layer on the substrate; Forming a diffusion film layer on a side of the indium gallium tin oxide film layer away from the substrate, wherein the diffusion film layer is a praseodymium metal film layer or a praseodymium metal oxide film layer; Annealing the indium gallium tin oxide film layer and the diffusion film layer to diffuse the praseodymium element in the diffusion film layer into the indium gallium tin oxide film layer, thereby obtaining an active layer including the channel layer and the first protective layer sequentially stacked on the base substrate; The diffusion film layer is patterned to obtain a diffusion layer located on the active layer. The diffusion layer is located on a side of the first protective layer away from the base substrate. The diffusion layer is a praseodymium metal layer or a praseodymium metal oxide layer.

19. The method according to claim 18, characterized in that The method further comprises: forming a source-drain metal layer on the diffusion layer, wherein the source-drain metal layer contains praseodymium; The source-drain metal layer is patterned to form a source electrode and a drain electrode.

20. An array substrate, characterized in that: The array substrate comprises a base substrate (30) and a plurality of thin film transistors on the base substrate, wherein the thin film transistors are the thin film transistors according to any one of claims 1 to 16.

21. The array substrate according to claim 20, characterized in that: The array substrate further includes: A first insulating layer (80) covering the first protective layer (102), the source electrode (501) and the drain electrode (502); A first electrode layer (90), comprising a plurality of first electrodes, wherein the plurality of first electrodes are located on a side of the first insulating layer (80) away from the substrate (30); A second insulating layer (100), covering the plurality of first electrodes; The second electrode layer (110) is located on a side of the second insulating layer (100) away from the base substrate (30), and the second electrode layer (110) is electrically connected to a source electrode (501) or a drain electrode (502) in a corresponding thin film transistor.

22. A display device, characterized in that: The display device comprises the array substrate as claimed in claim 20 or 21.

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