Frequency signal acquisition system and frequency signal acquisition method

Abstract

The present invention provides a frequency signal acquisition system, including a timer and a processor CPU, the timer including an input terminal TI, an edge detection module, a counter TCR, a control register and an interrupt output terminal INTTM, the timer works in an event counting mode, the input terminal TI is used to input the frequency signal as an external event, the interrupt output terminal INTTM is used to output an interrupt signal to the processor CPU when the external event counts to a first count value CV, the number of interrupt signals received by the processor CPU within a first cycle T is N, and the frequency F of the frequency signal is: N*CV / T. The present invention provides a frequency signal acquisition method. The frequency signal acquisition system and frequency signal acquisition method provided by the present invention set the timer to an external event counting mode or an external clock frequency division mode, and divide the frequency signal in this way, so that the processor can accurately acquire signals with higher frequencies.

Description

Technical Field

[0001] The present invention relates to the field of automobiles, and in particular to a frequency signal acquisition system and a frequency signal acquisition method. Background Art

[0002] The vehicle speed and rotation speed signals are both frequency signals:

[0003] The frequency of the vehicle speed signal = PPK*vehicle speed / 3600;

[0004] The frequency of the speed signal = M*speed / 60;

[0005] Among them, PPK is the number of pulses per kilometer, and M is the number of revolutions per minute. These parameters are usually adjusted by keys, and the adjusted values ​​are stored in the EEPROM of the instrument controller.

[0006] For the processor in the instrument controller, if the operating cycle is 25 milliseconds, one operating cycle can identify a maximum of 50 pulses, there are 40 operating cycles in 1 second, and the maximum frequency signal that can be reliably identified is 50*40=2000. When the frequency of the vehicle speed signal or the rotation speed signal is greater than 2000Hz, for example 4000Hz, the processor may not be able to reliably identify the number of pulses, and pulses may be lost, resulting in inaccurate vehicle speed or rotation speed display.

[0007] The frequency signal needs to be divided, but ordinary hardware dividers cannot meet the current needs. If the hardware divider used divides the frequency too much, the precision will be lost; if the hardware divider used divides the frequency too little, it cannot complete the current maximum frequency input. Summary of the invention

[0008] In view of the problems existing in the prior art, the problem to be solved by the present invention is to provide a frequency signal acquisition system, set the timer to external event counting mode or external clock division mode, and divide the frequency signal in this way, so that the processor can accurately acquire higher frequency signals.

[0009] The present invention provides a frequency signal acquisition system, comprising a timer and a processor CPU. The timer comprises an input terminal TI, an edge detection module, a counter TCR, a control register and an interrupt output terminal INTTM. The timer works in an event counting mode. The input terminal TI is used to input the frequency signal as an external event. The interrupt output terminal INTTM is used to output an interrupt signal to the processor CPU when the external event counts to a first count value CV. The number of interrupt signals received by the processor CPU within a first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0010] Furthermore, the control register includes a mode register TMR and a data register TDR, the channel operation mode in the mode register TMR is set to the event counting mode, the counting clock selection in the mode register TMR is set to select the TI input valid edge, and CV-1 is written into the data register TDR in hexadecimal data.

[0011] Further, the first count value CV is determined by the maximum frequency value Fmax of the frequency signal and the maximum frequency of the frequency signal that can be reliably identified by the processor.

[0012] Further, the timer is a separate timer or a timer in a timer array.

[0013] Further, the frequency signal is a vehicle speed signal, and the greater the number of pulses per kilometer of the vehicle, the greater the first count value CV; or the frequency signal is a speed signal, and the greater the number of revolutions per minute of the vehicle, the greater the first count value CV.

[0014] The present invention also provides a frequency signal acquisition method. The frequency signal acquisition system includes a timer and a processor CPU. The timer includes an input terminal TI, a control register and an interrupt output terminal INTTM. The method includes the following steps:

[0015] Connecting the frequency signal to the input terminal TI of the timer;

[0016] Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU;

[0017] Set the timer to event counting mode;

[0018] Write CV-1 into the data register TDR in hexadecimal format, where CV is the first count value;

[0019] Start event counting,

[0020] The value in the data register TDR is added by 1 and loaded into the counter TCR;

[0021] When the valid edge of the input terminal TI is detected, the counter TCR decreases by 1;

[0022] When the event count reaches the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU to repeat the event counting;

[0023] The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0024] The present invention also provides a frequency signal acquisition system, including a timer and a processor CPU, the timer including an input terminal TI, a control register, an interrupt output terminal INTTM and a waveform output terminal TO, the timer works in a frequency division mode, the input terminal TI is used to input the frequency signal as an external clock, when the external clock pulse count reaches a first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU, the number of interrupt signals received by the processor CPU within a first cycle T is N, and the frequency F of the frequency signal is: N*CV / T;

[0025] Or when the external clock pulse counts to the first count value CV, the waveform output terminal TO switches the output waveform, and the number of waveforms received by the processor CPU within the first period T is M. When the TI input edge in the mode register TMR is set to detect the rising edge or the falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TI input edge in the mode register TMR is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

[0026] Furthermore, the control register includes a mode register TMR and a data register TDR, the channel operation mode in the mode register TMR is the interval timer mode, the count clock selection in the mode register TMR is set to select the TI input valid edge, and CV-1 is written into the data register TDR in hexadecimal data.

[0027] The present invention also provides a frequency signal acquisition method. The frequency signal acquisition system includes a timer and a processor CPU. The timer includes an input terminal TI, a control register and an interrupt output terminal INTTM and a waveform output terminal TO. The method includes the following steps:

[0028] Connecting the frequency signal to the input terminal TI of the timer;

[0029] Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU, or connect the waveform output terminal TO to the corresponding input terminal of the processor CPU;

[0030] Set the timer to frequency division mode;

[0031] Write CV-1 into the data register TDR in hexadecimal format, where CV is the first count value;

[0032] Start external clock division,

[0033] Add 1 to the value in the data register TDR and load it into the counter TCR;

[0034] When the valid edge of the input terminal TI is detected, the counter TCR decreases by 1;

[0035] When the external clock counts to the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU; the number of interrupt signals received by the processor CPU within the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T;

[0036] or

[0037] When the external clock counts to the first count value CV, the waveform output terminal TO switches the signal, and the number of waveform signals received by the processor CPU in the first cycle T is M. When the TI input edge in the mode register TMR is set to detect the rising edge or the falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TI input edge in the mode register TMR is set to detect two edges,

[0038] The frequency F of the frequency signal is: M*CV / T.

[0039] Compared with the prior art, the frequency signal acquisition system and frequency signal acquisition method provided by the present invention have the following beneficial effects: the timer is set to an external event counting mode or an external clock division mode, and the frequency signal is divided in this way, so that the processor can accurately acquire signals with higher frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of a frequency signal acquisition system according to an embodiment of the present invention;

[0041] Figure 2 It is a block diagram of the timer Tmn working in the external event counting mode;

[0042] Figure 3 It is a configuration diagram of the timer Tmn working in the external event counting mode register TMRmn;

[0043] Figure 4 This is the timing diagram of timer Tmn working in external event counting mode;

[0044] Figure 5 It is a configuration diagram of the timer Tmn working in the frequency division mode register TMRmn;

[0045] Figure 6 It is the timing diagram of timer Tmn working in frequency division mode;

[0046] Figure 7 This is a block diagram of timer Tmn operating in frequency division mode. DETAILED DESCRIPTION

[0047] like Figure 1As shown, a frequency signal acquisition system of an embodiment of the present invention, for example, adopts a Renesas single-chip microcontroller, and the frequency signal acquisition system includes a timer and a processor CPU. The timer is a timer Tmn in a timer array, wherein m is a unit number, n is a channel number, m=0~2, n=0~7.

[0048] In this embodiment, the timer is a timer Tmn in the timer array, the timer works in an event counting mode, and the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU.

[0049] One or more timers in a timer array may be used to acquire a frequency signal, for example, Figure 1 As shown, Tmn is used to collect the frequency signal Sn, and Tmn+1 is used to collect the frequency signal Sn+1.

[0050] In this embodiment, a timer T11 (m=1, n=1) is used to collect the vehicle speed signal. In other embodiments, the timer T11 can also be used to collect the speed signal, and the timer T12 can be used to collect the vehicle speed signal.

[0051] The timer T11 includes an input terminal TI11, an edge detection module, a counter TCR11, a control register and an interrupt output terminal INTTM11.

[0052] In the frequency signal acquisition system of this embodiment, the timer T11 operates in the event counting mode, the input terminal TI11 is used to input the frequency signal as an external event, and the interrupt output terminal INTTM11 is used to output an interrupt signal to the processor CPU when the external event counts to the first count value CV. The number of interrupt signals received by the processor CPU within the first period T is N, and the frequency F of the frequency signal is: N*CV / T, where the first period T is the acquisition period of the frequency signal S, for example 1 millisecond.

[0053] like Figure 2 As shown, the frequency signal S is connected to the input terminal TI11 of the timer T11, and the interrupt output terminal INTTM11 is connected to the corresponding input terminal P1 of the processor CPU, and the input terminal P1 is the interrupt signal input terminal of the processor CPU.

[0054] The control register of the timer T11 includes a mode register TMR11, a counter TCR11 and a data register TDR11. The mode register TMR11 is used to set the working mode of the timer T11, the counter TCR11 is used for counting, and the data register TDR11 is used to set the counting data.

[0055] Figure 3The setting contents of the mode register TMRmn are shown. Accordingly, the n-channel operation mode in the mode register TMR11 is set to the event counting mode (011B, that is, bit 3 is set to 0, bit 2 is set to 1, and bit 1 is set to 1), and the counting clock selection in the mode register TMR11 is set to select the TI11 input valid edge (bit 12 is set to 1).

[0056] like Figure 4 As shown, the data register TDR11 is used to set the counting data, and CV-1 is written into the data register TDR11 in hexadecimal data, where CV is the first counting value.

[0057] In this embodiment, when the first count value CV is 4, 3 (i.e., CV-1) is written into the data register TDR11 as hexadecimal data (0003H), and when the first count value CV is 3, 2 (i.e., CV-1) is written into the data register TDR11 as hexadecimal data (0002H).

[0058] During the frequency signal acquisition process, the first count value CV can be dynamically adjusted and rewritten into the data register TDR to take effect in the next acquisition cycle, for example Figure 4 0002H is written into the data register TDR11, and when three external events are collected in the next collection cycle, the interrupt output terminal INTTM11 outputs an interrupt signal.

[0059] The frequency signal is a vehicle speed signal, and the PPK (pulses per kilometer) of different vehicles is different. The larger the PPK, the larger the first count value CV; or the frequency signal is a speed signal, and the M (revolutions per minute) of different vehicles is different. The larger the M, the larger the first count value CV.

[0060] PPK or M can be dynamically set according to the value stored in the EEPROM of the instrument controller, so that the technical solution in this embodiment can be adapted to various vehicles and accurately collect frequency signals.

[0061] The first count value CV can also be determined by the maximum frequency value Fmax of the frequency signal (for example, 40000 Hz) and the maximum frequency of the frequency signal that the processor can reliably identify (for example, 2000 Hz), that is, the maximum frequency value Fmax is adjusted to the frequency range that the processor can reliably identify by frequency division.

[0062] like Figure 4 As shown in the figure, when the software sets the TS11 bit to 1, TE11 is high level after being triggered, and the external event counting starts. Since TS11 is a trigger bit, it automatically returns to 0 after being triggered.

[0063] The edge detection module of timer T11 is used to detect the effective edge of the external event signal. Whenever a valid edge is detected at TI11, counter TCR11 is reduced by 1. When counter TCR11 is reduced to 0000H, that is, when it counts to the first count value CV (0004H, 4 external events), the interrupt output terminal INTTM11 generates an interrupt signal, and counter TCR11 reloads the value of data register TDR11 + 1. Here, the value of data register TDR11 is 0003H, and counter TCR11 is reloaded with 0004H to continue counting.

[0064] When the external event count reaches the first count value CV, the interrupt output terminal INTTM11 outputs an interrupt signal to the processor CPU. The frequency Fc of the signal received by the processor CPU is 1 / CV of the frequency F of the frequency signal S, that is, the frequency is divided into CV.

[0065] The number of interrupt signals received by the processor CPU in the first cycle T is N, Fc=N / T, and the frequency of the frequency signal is F=Fc*CV=N*CV / T.

[0066] Using the frequency signal acquisition system in this embodiment, the frequency signal acquisition method includes the following steps:

[0067] Connect the frequency signal S to the input terminal TI11 of the timer T11 of the timer array, and connect the interrupt output terminal INTTM11 to the corresponding input terminal P1 of the processor CPU;

[0068] Set timer T11 in the timer array to event counting mode;

[0069] Write CV-1 into data register TDR11 in hexadecimal format, where CV is the first count value;

[0070] Start event counting,

[0071] The value in data register TDR11 is added by 1 and loaded into counter TCR11;

[0072] When the valid edge of input terminal TI11 is detected, counter TCR11 is reduced by 1;

[0073] When the external event count reaches the first count value CV, the interrupt output terminal INTTM11 outputs an interrupt signal to the processor CPU to repeat the event counting;

[0074] The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0075] In this way, the processor CPU can accurately acquire signals with higher frequencies, that is, signals whose frequencies are higher than the maximum frequency that the processor can reliably identify.

[0076] In yet another embodiment, the timer is a timer Tmn in a timer array, the timer operates in a frequency division mode, and the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU.

[0077] The frequency signal acquisition system in this embodiment includes a timer and a processor CPU, and the timer is a timer Tmn in the timer array.

[0078] The timer Tmn includes an input terminal TImn, an edge detection module, a counter TCRmm, a control register, and an interrupt output terminal INTTMmn. The timer Tmn works in a frequency division mode. The input terminal TImn is used to input the frequency signal as an external clock. When the external clock pulse counts to a first count value CV, the interrupt output terminal INTTMmn outputs an interrupt signal to the processor CPU. The number of interrupt signals received by the processor CPU within the first period T is N, and the frequency F of the frequency signal is: N*CV / T.

[0079] The control register includes a mode register TMRmn and a data register TDRmn. The n-channel operation mode in the mode register TMRmn is the interval timer mode. The count clock selection in the mode register TMRmn is set to select the TImn input valid edge. CV-1 is written into the data register TDRmn in hexadecimal data.

[0080] Figure 5 The setting contents of the mode register TMRmn are shown. Accordingly, the n-channel operation mode in the mode register TMR11 is set to the division mode (000B, that is, bit 3 is set to 0, bit 2 is set to 0, and bit 1 is set to 0), and the counting clock selection in the mode register TMR11 is set to select the TI11 input valid edge (bit 12 is set to 1).

[0081] The data register TDR11 is used to set the count data. CV-1 is written into the data register TDR11 in hexadecimal format. In this embodiment, Figure 6 As shown, when the first count value CV is 3, 2 (ie, CV-1) is written into the data register TDR11 as hexadecimal data (0002H), and when the first count value CV is 2, 1 (ie, CV-1) is written into the data register TDR11 as hexadecimal data (0001H).

[0082] like Figure 6 As shown in the figure, when the software sets the TS11 bit to 1, TE11 is triggered to a high level, and the external clock division starts. Since TS11 is a trigger bit, it automatically returns to 0 after being triggered.

[0083] Whenever a valid edge is detected at TI11, the counter TCR11 is decremented by 1. When the counter TCR11 is decremented to 0000H, that is, when it counts to the first count value CV (0003H), the interrupt output terminal INTTM11 generates an interrupt signal, and the counter TCR11 is reloaded with the value of the data register TDR11 + 1. Here, the value of the data register TDR11 is 0002H, and the counter TCR11 is reloaded with 0003H and continues counting. The value of the data register TDR11 is 0001H, and the counter TCR11 is reloaded with 0003H.

[0084] The present invention also provides a frequency signal acquisition method. The frequency signal acquisition system includes a timer and a processor CPU. The timer is a timer Tmn in a timer array, including an input terminal TImn, a control register and an interrupt output terminal INTTMmn. The method includes the following steps:

[0085] Connect the frequency signal to the input terminal TImn of the timer Tmn, and connect the interrupt output terminal INTTMmn to the corresponding input terminal of the processor CPU;

[0086] Set the timer Tmn in the timer array to the frequency division mode;

[0087] Write CV-1 into the data register TDRmn in hexadecimal format, where CV is the first count value;

[0088] Start external clock division,

[0089] Add 1 to the value in data register TDRmn and load it into counter TCRmn;

[0090] When the valid edge of the input terminal TImn is detected, the counter TCRmn is reduced by 1;

[0091] When the external clock counts to the first count value CV, the interrupt output terminal INTTMmn outputs an interrupt signal to the processor CPU;

[0092] The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0093] In yet another embodiment, the timer is a timer Tmn in a timer array, the timer operates in a frequency division mode, and the waveform output terminal TOmn outputs a waveform signal to a processor.

[0094] The timer Tmn includes an input terminal TImn, an edge detection module, a counter TCRmm, a control register and a waveform output terminal TOmn. The timer Tmn works in a frequency division mode. The input terminal TImn is used to input the frequency signal as an external clock. When the external clock pulse counts to a first count value CV, the waveform output terminal TOmn switches the output waveform, such as Figure 6 shown.

[0095] like Figure 7 As shown, the timer T11 also includes an edge detection module for detecting the effective edge of the external clock pulse. Figure 6 As shown, whenever a valid edge is detected at TI11, the counter TCR11 is reduced by 1. When the counter TCR11 is reduced to 0000H, that is, the count reaches the first count value CV (0003H), the waveform output terminal TO11 switches the output signal, and the counter TCR11 reloads the value of the data register TDR11 + 1. Here, the value of the data register TDR11 is 0002H, and the counter TCR11 is reloaded with 0003H to continue counting.

[0096] The control register includes a mode register TMRmn and a data register TDRmn. The n-channel operation mode in the mode register TMRmn is the interval timer mode. The count clock selection in the mode register TMRmn is set to select the TImn input valid edge. CV-1 is written into the data register TDRmn in hexadecimal data.

[0097] When the TImn input edge in the mode register TMRmn is set to detect a rising edge or a falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TImn input edge in the mode register TMRmn is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

[0098] Using the frequency signal acquisition system in this embodiment, the frequency signal acquisition method includes the following steps:

[0099] Connect the frequency signal to the input terminal TImn of the timer Tmn, and connect the waveform output terminal TOmn to the corresponding input terminal of the processor CPU;

[0100] Set the timer Tmn in the timer array to the frequency division mode;

[0101] Write CV-1 into the data register TDRmn in hexadecimal format, where CV is the first count value;

[0102] Start external clock division,

[0103] Add 1 to the value in data register TDRmn and load it into counter TCRmn;

[0104] When the valid edge of the input terminal TImn is detected, the counter TCRmn is reduced by 1;

[0105] When the external clock counts to the first count value CV, the waveform output terminal TOmn switches the signal;

[0106] The number of waveform signals received by the processor CPU within the first cycle T is M. When the TImn input edge in the mode register TMRmn is set to detect a rising edge or a falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TImn input edge in the mode register TMRmn is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

[0107] In yet another embodiment, the timer is a separate timer, the timer operates in an event counting mode, and the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU.

[0108] In this embodiment, the timer is a separate timer, which includes an input terminal TI, an edge detection module, a counter TCR, a control register and an interrupt output terminal INTTM. The timer operates in an event counting mode. The input terminal TI is used to input the frequency signal as an external event. The interrupt output terminal INTTM is used to output an interrupt signal to the processor CPU when the external event counts to a first count value CV. The number of interrupt signals received by the processor CPU within the first period T is N, and the frequency F of the frequency signal is: N*CV / T.

[0109] The control register includes a mode register TMR and a data register TDR. The channel operation mode in the mode register TMR is set to the event counting mode. The count clock selection in the mode register TMR is set to select the TI input valid edge. CV-1 is written into the data register TDR in hexadecimal data.

[0110] The frequency signal acquisition method comprises the following steps:

[0111] Connecting the frequency signal to the input terminal TI of the timer;

[0112] Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU;

[0113] Set the timer to event counting mode;

[0114] Write CV-1 into the data register TDR in hexadecimal format, where CV is the first count value;

[0115] Start event counting,

[0116] The value in the data register TDR is added by 1 and loaded into the counter TCR;

[0117] When the valid edge of the input terminal TI is detected, the counter TCR decreases by 1;

[0118] When the event count reaches the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU to repeat the event counting;

[0119] The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0120] In yet another embodiment, the timer is a separate timer, the timer operates in a frequency division mode, and the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU.

[0121] In this embodiment, the timer is a separate timer, which includes an input terminal TI, a control register, an interrupt output terminal INTTM and a waveform output terminal TO. The timer operates in a frequency division mode. The input terminal TI is used to input the frequency signal as an external clock. When the external clock pulse counts to a first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU.

[0122] The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0123] The frequency signal acquisition method comprises the following steps:

[0124] Connecting the frequency signal to the input terminal TI of the timer;

[0125] Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU;

[0126] Set the timer to frequency division mode;

[0127] Write CV-1 into the data register TDR in hexadecimal format, where CV is the first count value;

[0128] Start external clock division,

[0129] Add 1 to the value in the data register TDR and load it into the counter TCR;

[0130] When the valid edge of the input terminal TI is detected, the counter TCR decreases by 1;

[0131] When the external clock counts to the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU; the number of interrupt signals received by the processor CPU within the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

[0132] In yet another embodiment, the timer is a separate timer, the timer operates in a frequency division mode, and the waveform output terminal TO outputs a waveform signal to the processor CPU.

[0133] The difference from the previous embodiment is that the waveform output terminal TO is connected to the corresponding input terminal of the processor CPU, and when the external clock counts to the first count value CV, the waveform output terminal TO switches the signal.

[0134] The frequency signal acquisition system includes a timer and a processor CPU. The timer includes an input terminal TI, a control register, an interrupt output terminal INTTM and a waveform output terminal TO. The timer works in a frequency division mode. The input terminal TI is used to input the frequency signal as an external clock. When the external clock pulse counts to a first count value CV, the waveform output terminal TO switches the output waveform. The number of waveforms received by the processor CPU within the first period T is M. When the TI input edge in the mode register TMR is set to detect an upward edge or a downward edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TI input edge in the mode register TMR is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

[0135] The frequency signal acquisition method comprises the following steps:

[0136] Connecting the frequency signal to the input terminal TI of the timer;

[0137] Connect the waveform output terminal TO to the corresponding input terminal of the processor CPU;

[0138] Set the timer to frequency division mode;

[0139] Write CV-1 into the data register TDR in hexadecimal format, where CV is the first count value;

[0140] Start external clock division,

[0141] Add 1 to the value in the data register TDR and load it into the counter TCR;

[0142] When the valid edge of the input terminal TI is detected, the counter TCR decreases by 1;

[0143] When the external clock counts to the first count value CV, the waveform output terminal TO switches the signal, and the number of waveform signals received by the processor CPU within the first period T is M. When the TI input edge in the mode register TMR is set to detect the rising edge or the falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TI input edge in the mode register TMR is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

[0144] Although the present invention has been disclosed as above with preferred embodiments, the present invention is not limited thereto. Any changes and modifications made by any person skilled in the art without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention, and therefore the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A frequency signal acquisition system, characterized in that: The frequency signal acquisition system includes a timer and a processor CPU. The timer includes an input terminal TI, an edge detection module, a counter TCR, a control register and an interrupt output terminal INTTM. The control register includes a mode register TMR and a data register TDR. The input terminal TI is connected to the edge detection module, the edge detection module is connected to the counter TCR, the data register TDR is connected to the counter TCR, the counter TCR is connected to the interrupt output terminal INTTM, and the interrupt output terminal INTTM is connected to the processor CPU. The timer works in an event counting mode. The input terminal TI is used to input the frequency signal as an external event. The mode register TMR is used to input the frequency signal as an external event. The channel operation mode in the device TMR is set to the event counting mode, the counting clock selection in the mode register TMR is set to select the effective edge of the frequency signal input at the input terminal TI, the first count value CV is subtracted by 1 and written into the data register TDR in hexadecimal data, the edge detection module is used to detect the effective edge of the frequency signal, the counter TCR is used for counting, the interrupt output terminal INTTM is used to output an interrupt signal to the processor CPU when the counter TCR counts the external event to the first count value CV, the number of interrupt signals received by the processor CPU within the first period T is N, and the frequency F of the frequency signal is: N*CV / T.

2. The frequency signal acquisition system according to claim 1, characterized in that: The first count value CV is determined by the maximum frequency value Fmax of the frequency signal and the maximum frequency of the frequency signal that can be reliably identified by the processor.

3. The frequency signal acquisition system according to claim 1, characterized in that: The timer is either an individual timer or a timer in a timer array.

4. The frequency signal acquisition system according to claim 1, characterized in that: The frequency signal is a vehicle speed signal, and the greater the number of pulses per kilometer of the vehicle, the greater the first count value CV; or the frequency signal is a speed signal, and the greater the number of revolutions per minute of the vehicle, the greater the first count value CV.

5. A frequency signal acquisition method, characterized in that: Applied to the frequency signal acquisition system according to any one of claims 1 to 4, the method comprises the following steps: Connecting the frequency signal to the input terminal TI of the timer; Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU; Set the timer to event counting mode; Subtract 1 from the first count value CV and write it into the data register TDR in hexadecimal format, where CV is the first count value; Start event counting, The value in the data register TDR is added by 1 and loaded into the counter TCR; When the effective edge of the frequency signal inputted by the input terminal TI is detected, the counter TCR is reduced by 1; When the event count reaches the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU to repeat the event counting; The number of interrupt signals received by the processor CPU in the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T.

6. A frequency signal acquisition system, characterized in that: The frequency signal acquisition system includes a timer and a processor CPU, the timer includes an input terminal TI, an edge detection module, a counter TCR, a control register, an interrupt output terminal INTTM and a waveform output terminal TO, the control register includes a mode register TMR and a data register TDR, the input terminal TI is connected to the edge detection module, the edge detection module is connected to the counter TCR, the data register TDR is connected to the counter TCR, the counter TCR is respectively connected to the interrupt output terminal INTTM and the waveform output terminal TO, and the interrupt output terminal INTTM and the waveform output terminal TO are connected to the processor CPU; The timer works in the frequency division mode, the input terminal TI is used to input the frequency signal as an external clock, the edge detection module is used to detect the effective edge of the frequency signal, the counter TCR is used to count, the channel operation mode in the mode register TMR is the interval timer mode, the counting clock selection in the mode register TMR is set to select the effective edge of the frequency signal input at the input terminal TI, and the first count value CV is subtracted by 1 and written into the data register TDR in hexadecimal data; When the external clock pulse count reaches the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU. The number of interrupt signals received by the processor CPU within the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T; or When the external clock pulse counts to the first count value CV, the waveform output terminal TO switches the output waveform, and the number of waveforms received by the processor CPU within the first period T is M. When the input edge of the frequency signal inputted by the input terminal TI in the mode register TMR of the control register is set to detect the rising edge or the falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the input edge of the frequency signal inputted by the input terminal TI in the mode register TMR is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

7. A frequency signal acquisition method, characterized in that: Applied to the frequency signal acquisition system of claim 6, the method comprises the following steps: Connecting the frequency signal to the input terminal TI of the timer; Connect the interrupt output terminal INTTM to the corresponding input terminal of the processor CPU, or connect the waveform output terminal TO to the corresponding input terminal of the processor CPU; Set the timer to frequency division mode; Subtract 1 from the first count value CV and write it into the data register TDR in hexadecimal format, where CV is the first count value; Start external clock division, Add 1 to the value in the data register TDR and load it into the counter TCR; When the effective edge of the frequency signal inputted by the input terminal TI is detected, the counter TCR is reduced by 1; When the external clock counts to the first count value CV, the interrupt output terminal INTTM outputs an interrupt signal to the processor CPU; the number of interrupt signals received by the processor CPU within the first cycle T is N, and the frequency F of the frequency signal is: N*CV / T; or When the external clock counts to the first count value CV, the waveform output terminal TO switches the signal, and the number of waveform signals received by the processor CPU within the first period T is M. When the input edge of the frequency signal input at the input terminal TI in the mode register TMR is set to detect the rising edge or the falling edge, the frequency F of the frequency signal is: M*CV*2 / T; when the TI input edge in the mode register TMR is set to detect two edges, the frequency F of the frequency signal is: M*CV / T.

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