Control Circuit and Conversion Circuit of a Forced Resonant Soft-Switching Flyback Power Converter

Abstract

The control circuit and conversion circuit of the forced resonance soft-switching flyback power converter of the present invention. The input ends of the Schmidt inverter U2 in the control circuit are all connected to the anode of the diode D2, one end of the resistor R2, and one end of the resonance capacitor C2. The output end of the Schmidt inverter U2 is connected to the input end of the Schmidt inverter U3. The input ends of the Schmidt inverter U1 are all connected to the anode of the diode D1, one end of the resistor R1, and one end of the resonance capacitor C1. The output end of the Schmidt inverter U1 is connected to the input end of the high-speed AND gate U4. It is not restricted by the bus voltage and switching frequency, has a fast signal conversion speed, good waveform quality, simple application circuit, and low cost, and can meet the drive control application of the forced resonance soft-switching flyback power converter. The conversion circuit includes the control circuit of the forced resonance soft-switching flyback power converter and a single-ended flyback converter described above.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and specifically relates to a control circuit and a conversion circuit for a forced resonance soft-switching flyback power converter. Technical Background

[0002] The single-ended flyback power conversion topology has the characteristics of simple circuit structure, few components, and mature technology, and is widely used in low-power power supply products within 100W. In recent years, aiming at the miniaturization and high efficiency of power supplies, the switching frequency of power supplies has been continuously increased. In order to reduce switching losses, people have improved on the basis of the single-ended flyback power conversion topology, and a forced resonance flyback conversion power topology has been generated. The resonance capacitor, resonance switch, and auxiliary winding of the transformer are connected in series. By triggering the resonance switch at an appropriate time, the drain voltage of the main power switch tube is forced to resonate to zero before turning on, so as to realize the zero-voltage turn-on of the main power switch tube.

[0003] The internal principle of the forced resonance soft-switching flyback power converter is as Figure 1 shown. It internally includes: a power unit 1, a sampling isolation unit 2, and a PWM control unit 3. The power unit 1 is a common single-ended flyback power conversion topology, including an input filter L1, Cin, a power transformer T1, an output rectifier filter D2, Co, a front-stage power switch MOS transistor Q1, and a transformer leakage inductance spike absorption circuit composed of R1, C1, and D1. The auxiliary winding T1-5 of the power transformer T1, the capacitor C2, and the switching MOS transistor Q2 form a zero-voltage turn-on forced resonance circuit. The common functions of the sampling isolation unit 2 are output voltage sampling, error signal amplification, and error signal isolation and transmission, including a sampling circuit composed of R2 and R3, a loop compensation circuit composed of an operational amplifier, R4, and C3, and an isolation optocoupler. The PWM control unit 3 obtains the error signal transmitted by the isolation optocoupler through the FB terminal, and converts the feedback signal into two drive signals through the internal logic processing circuit. OUT1 is a PWM signal to drive the front-stage main power MOS transistor Q1, and OUT2 is a resonance switch control signal to drive the resonance MOS transistor Q2. The specific working process of the forced resonance soft-switching flyback power converter is as Figure 2 shown. It can be divided into five stages t0-t5 within one cycle. Among them, OUT1 is the gate drive signal of the front-stage main power switch Q1, OUT2 is the gate drive signal of the resonance circuit switch Q2, V_Q1ds is the drain-source voltage of the front-stage main power switch Q1, I_Q1ds is the drain-source current of the front-stage main power switch Q1, and I_D2 is the current of the output rectifier diode D2, where the direction from the anode to the cathode is positive, and this current is equal to the secondary winding current of the power transformer T1. Specifically:

[0004] t0 - t1: Before time t0, the primary main power switch Q1 is turned on, the resonant circuit switch Q2 remains off, and the drain voltage V_Q1ds of the primary main power switch Q1 drops to 0 and remains until time t1; the current in the primary side winding of the transformer is equal to the drain - source current I_Q1ds of the primary main power switch Q1 and starts to rise from 0, reaching the maximum value at time t1. t1 - t2: At time t1, the primary main power switch Q1 is turned off, the resonant circuit switch Q2 remains off, the current I_Q1ds in the primary side winding of the transformer gradually drops from the maximum value to 0 and remains until time t2; the drain voltage V_Q1ds of the primary main power switch Q1 flybacks to the maximum value and is flyback - output through the secondary side windings T1 - 3 and T1 - 4 of the power transformer T1. The current in the secondary side winding linearly drops until time t2 when the secondary current drops to 0; the auxiliary winding T1 - 5 of the power transformer and T1 - 2 are of the same name terminal, V T1-5 remains at a high level and charges the resonant capacitor C1 through the source - drain parasitic diode of the resonant circuit switch Q2, with the voltage of the resonant capacitor C1 being positive at the top and negative at the bottom. t2 - t3: The primary main power switch Q1 and the resonant circuit switch Q2 continue to remain off. At time t2, the current in the secondary winding of the power transformer drops to 0, and the output voltage, the parasitic capacitance of the rectifier diode D2, the inductance of the primary winding of the power transformer, and the parasitic capacitance between the drain and source of the VDMOS transistor Q1 resonate freely, causing the drain - source voltage V_Q1ds of the primary power switch Q1 to vary sinusoidally. t3 - t4: At time t3, the resonant circuit switch Q2 is turned on, the primary main power switch Q1 remains off, and the resonant capacitor C1 discharges through the auxiliary winding T1 - 5, T1 - 6 of the power transformer and the resonant circuit switch Q2. The voltage applied to the auxiliary winding T1 - 5 of the power transformer is at a high level. Since the auxiliary winding T1 - 5 of the power transformer and T1 - 2 are of the same name terminal, T1 - 2 is forced to rise to a high level. T4 - t5: At time t4, the resonant circuit switch Q2 is turned off, the primary main power switch Q1 remains off, the discharge path of the resonant capacitor C1 to the auxiliary winding T1 - 5 of the power transformer T1 is disconnected, and the auxiliary winding T1 - 5 of the power transformer T1 charges the resonant capacitor C1 in the reverse direction through the source - drain parasitic diode of the resonant circuit switch Q2, and the current flows outwards through the auxiliary winding T1 - 5 of the power transformer T1. Due to the coupling principle between transformer windings, a current flowing into T1 - 2 is formed in the primary winding of the power transformer T1, and the current flow direction is: source - drain parasitic diode of Q1 → T1 - 2 → T1 - 1. At this time, since the current flow direction of the primary main power switch Q1 is from the source to the drain, the drain voltage of the primary main power switch Q1 is forced to be clamped to 0. By the time the primary main power switch Q1 is turned on again at time t5, zero - voltage turn - on can be achieved.

[0005] Based on the working process of the above-mentioned forced-resonance soft-switching flyback power converter, the control circuit needs to generate two precisely delayed driving signals. Among them, OUTA is a pulse-width modulation signal, and its duty cycle can be adjusted accordingly with the feedback signal of the control loop; OUTB is a narrow-pulse signal, where the pulse width (t3 - t4) can be adjusted, and the signal delay (t4 - t5) can be adjusted. The existing control method uses an integrated controller to implement the control of these two driving signals. For example, the forced-resonance flyback controller of the XDPS21071 model from Infineon Technologies. This device is in the peak current control mode and outputs two driving signals, GD0 and GD1. The specific application circuit principle is as Figure 3 shown, and the driving signals are as Figure 4 shown. Among them, the GD0 terminal outputs a PWM driving signal, and its duty cycle is adjusted accordingly with the voltage-loop control signal at the MFIO terminal and the current-loop control signal at the CS terminal; the GD1 terminal outputs a narrow-pulse driving signal for the resonance circuit, and the width t GD1on and the leading time t ZVSdead of this signal can be set according to the corresponding parameters of the converter.

[0006] Currently, there are very few integrated controllers for the application of forced-resonance soft-switching flyback power converters, and they are expensive; the forced-resonance flyback controller of the XDPS21071 model from Infineon Technologies is developed for AC / DC power adapters, with a high starting voltage of up to 600V and a maximum switching frequency of only 140kHz, which cannot meet the applications with higher switching frequencies and lower bus voltages in reality. Summary of the Invention

[0007] Aiming at the application limitations of the existing technology, which cannot adapt to applications with higher frequencies and lower bus voltages, the present invention provides a control circuit and a conversion circuit for a forced-resonance soft-switching flyback power converter. It is not limited by the bus voltage and switching frequency, has a fast signal conversion speed, good waveform quality, a simple application circuit, and low cost, and can meet the drive control applications of forced-resonance soft-switching flyback power converters.

[0008] The present invention is realized through the following technical solutions:

[0009] The control circuit of the forced-resonance soft-switching flyback power converter includes a Schmitt inverter U1, a Schmitt inverter U2, a Schmitt inverter U3, and a high-speed AND gate U4;

[0010] The input terminals of the Schmitt inverter U2 are all connected to the anode of the diode D2, one end of the resistor R2, and one end of the resonance capacitor C2. The output terminal of the Schmitt inverter U2 is connected to the input terminal of the Schmitt inverter U3;

[0011] The input terminals of the Schmitt inverter U1 are all connected to the anode of the diode D1, one end of the resistor R1, and one end of the resonant capacitor C1. The output terminal of the Schmitt inverter U1 is connected to the input terminal of the high-speed AND gate U4.

[0012] Preferably, the models of the Schmitt inverter U1, the Schmitt inverter U2, and the Schmitt inverter U3 are all SN74HC14.

[0013] Preferably, the model of the high-speed AND gate U4 is SN74HC08.

[0014] Preferably, both the diode D1 and the diode D2 are high-speed switching diodes.

[0015] Preferably, the resistor R1 and the resonant capacitor C1 form a delay-on circuit.

[0016] Preferably, the resistor R2 and the resonant capacitor C2 form a delay-on circuit.

[0017] Preferably, the other ends of the resonant capacitor C1 and the resonant capacitor C2 are both grounded.

[0018] Preferably, the resistance values of the resistor R1 and the resistor R2 are both 1k - 10k ohms.

[0019] A forced-resonance soft-switching flyback power conversion circuit includes the control circuit of the above-mentioned forced-resonance soft-switching flyback power converter and a single-ended flyback converter;

[0020] In the single-ended flyback converter, the output terminal of the PWM controller is simultaneously connected to the cathode of the diode D2, the other end of the resistor R2, the cathode of the diode D1, and the other end of the resistor R1. The output terminal of the Schmitt inverter U3 is connected to the front-stage power MOS transistor Q1, and the output terminal of the high-speed AND gate U4 is connected to the forced-resonance switch Q2.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects:

[0022] The control circuit of the forced-resonance soft-switching flyback power converter of the present invention. On the one hand, the input terminals of the Schmidt inverter U2 are all connected to the anode of the diode D2, one end of the resistor R2, and one end of the resonant capacitor C2. In this way, the PWM signal can be connected to the cathode of the diode D2 and the other end of the resistor R2. The output terminal of the Schmidt inverter U2 is connected to the input terminal of the Schmidt inverter U3. At this time, the Schmidt inverter U3 can output a delayed PWM signal. On the other hand, the input terminals of the Schmidt inverter U1 are all connected to the anode of the diode D1, one end of the resistor R1, and one end of the resonant capacitor C1. In this way, the PWM signal can be connected to the cathode of the diode D1 and the other end of the resistor R1. The output terminal of the Schmidt inverter U1 is connected to the input terminal of the high-speed AND gate U4, and the PWM signal can be connected to the other input terminal of the high-speed AND gate U4, so that the high-speed AND gate U4 outputs a forced-resonance switch drive narrow pulse signal. The present invention is composed of basic components such as general-purpose devices Schmidt inverters, high-speed AND gates, resistors, resonant capacitors, and diodes. The circuit structure is simple and easy to implement, and the component cost is low. It can be used in cooperation with traditional single-output PWM controllers, and it is very easy to implement forced-resonance soft-switching control. By collecting, delaying, and logically transforming the PWM signal, the present invention forms two independent drive signals, namely, a forced-resonance switch drive narrow pulse signal and a delayed PWM drive signal. Through the adjustment of two sets of delay turn-on circuits formed in the circuit, on the one hand, the width of the narrow pulse signal can be accurately adjusted; on the other hand, the accurate delay of the PWM signal can be achieved.

[0023] The forced-resonance soft-switching flyback power conversion circuit of the present invention includes a single-ended flyback converter. The PWM signal output by the PWM controller in the single-ended flyback converter can be input to the PWM terminal of the control circuit of the forced-resonance soft-switching flyback power converter. After the transformation and transmission of the circuit, two signals OUT1 and OUT2 are output. OUT1 can drive the front-stage power MOS transistor Q1 in the single-ended flyback converter, and OUT2 can drive the forced-resonance switch Q2. Description of the Drawings

[0024] Figure 1 It is the internal principle circuit diagram of the existing forced-resonance soft-switching flyback power converter.

[0025] Figure 2 It is the waveform diagram of the key nodes inside the existing forced-resonance soft-switching flyback power converter.

[0026] Figure 3 It is the application principle diagram of the existing forced-resonance flyback controller of model XDPS21071.

[0027] Figure 4 It is the drive waveform diagram of the existing forced-resonance flyback controller of model XDPS21071.

[0028] Figure 5 This is the control circuit diagram of the forced resonant soft-switching flyback power converter according to the present invention.

[0029] Figure 6 This is the key-point waveform diagram of the forced resonant soft-switching flyback power converter according to the present invention.

[0030] Figure 7 This is the circuit diagram of the control circuit of the forced resonant soft-switching flyback power converter according to the present invention during specific implementation.

[0031] In the figure: power unit 1, sampling isolation unit 2, PWM control unit 3. Specific implementation mode

[0032] The following further elaborates on the present invention in detail in conjunction with specific embodiments, which is an explanation rather than a limitation of the present invention.

[0033] A control circuit of a forced resonant soft-switching flyback power converter according to the present invention, as Figure 5 shown, U1, U2, and U3 are all high-speed Schmitt inverters, with the model numbers all being SN74HC14. "High-speed" means that the signal delay time of the Schmitt inverter is in the nanosecond level, much faster than that of ordinary Schmitt inverters. U4 is a high-speed AND gate, with the model number being SN74HC08. Diodes D1 and D2 are both high-speed switching diodes. V_PWM is the PWM signal output by the DC / DC converter control loop. OUT1 is the delayed PWM signal, and OUT2 is the narrow pulse signal for driving the forced resonant switch.

[0034] Delayed PWM signal generation circuit: The V_PWM signal is connected to the cathode of the high-speed switching diode D2 and one end of the resistor R2 at point A. The resistance value of the resistor R2 is 1 kΩ - 10 kΩ. The anode of the high-speed switching diode D2, the other end of the resistor R2, and one end of the resonant capacitor C2 are jointly connected to the input terminal (i.e., point D) of the high-speed Schmitt inverter U2. The other end of C2 is grounded. The output terminal (i.e., point E) of the high-speed Schmitt inverter U2 is connected to the input terminal of the high-speed Schmitt inverter U3, and the high-speed Schmitt inverter U3 outputs the delayed PWM signal OUT1.

[0035] Forced resonant switch drive narrow pulse signal generation circuit: The V_PWM signal is connected to the cathode of the high-speed switching diode D1 and one end of the resistor R1 at point A. The resistance value of the resistor R1 is 1 kΩ - 10 kΩ. The anode of the high-speed switching diode D1, the other end of the resistor R1, and one end of the resonant capacitor C1 are jointly connected to the input terminal (i.e., point B) of the high-speed Schmitt inverter U1. The other end of C1 is grounded. The output terminal of the high-speed Schmitt inverter U1 is connected to one input terminal of the high-speed AND gate U4. The V_PWM signal is connected to the other input terminal of the high-speed AND gate U4 at point A. The high-speed AND gate U4 outputs the forced resonant switch drive narrow pulse signal OUT2.

[0036] A control circuit for a forced resonant soft-switching flyback power converter according to the present invention has the following specific working process:

[0037] The key waveforms of the present invention are as Figure 6 shown. The input V_PWM signal is a square-wave voltage with a fixed frequency, fixed amplitude, and a duty cycle that is adjusted in real time output by a PWM controller.

[0038] In the first case, when the input signal V_PWM changes from low to high, the delay turn-on circuit composed of the resistor R1 and the resonant capacitor C1 slowly charges the resonant capacitor C1. The voltage at point B rises slowly. The voltage rise rate is determined by the time constant composed of the resistor R1 and the resonant capacitor C1. After a time Δa1 (t0 - t1), the voltage at point B is greater than Vth (Vth is the input high-level threshold voltage of the Schmitt inverter). The Schmitt inverter U1 outputs a low level at point C. When the input signal V_PWM changes from high to low, due to the presence of the diode D1, the resonant capacitor C1 discharges quickly, and the voltage at point B is rapidly pulled down. The Schmitt inverter U1 outputs a high level at point C. The V_PWM signal and the low-level or high-level signal output at point C are logically operated through the high-speed AND gate U4 to output the narrow pulse signal OUT2.

[0039] In the second case, when the input signal V_PWM changes from low to high, the delay turn-on circuit composed of the resistor R2 and the resonant capacitor C2 slowly charges the resonant capacitor C2. The voltage at point D rises slowly. The voltage rise rate is determined by the time constant composed of the resistor R2 and the resonant capacitor C2. After a time Δb1 (t0 - t2), the voltage at point D is greater than Vth. The Schmitt inverter U2 outputs a low level at point E. When the input signal V_PWM changes from high to low, due to the presence of the diode D2, the resonant capacitor C2 discharges quickly, and the voltage at point D is rapidly pulled down. The Schmitt inverter U2 outputs a high level at point E. The signal at point E passes through the Schmitt inverter U3 again to output the inverted signal OUT1. The falling edge of OUT1 and the falling edge of V_PWM occur simultaneously at time t3, and the time t2 - t3 is automatically adjusted according to the duty cycle of the PWM signal in the circuit.

[0040] The response times of the high-speed Schmitt inverters U1, U2, U3, the high-speed AND gate U4, the switching diodes D1 and D2 are very short, generally not exceeding a few nanoseconds, which are ignored here. The delay-on circuit composed of the resistor R1 and the resonant capacitor C1 determines the pulse width Δa1 of the forced-resonant switch drive narrow pulse signal OUT2, and the delay-on circuit composed of the resistor R2 and the resonant capacitor C2 determines the delay time Δb1 of the delayed PWM signal OUT1. When the voltage at point B or point D rises to reach Vth, the output of the Schmitt inverter flips. Therefore, the time required for the capacitor C1 or C2 in the delay-on circuit to charge to Vth is the narrow pulse time, that is, the delay time. The pulse width Δa1 is in a proportional relationship with the resistor R1 and the resonant capacitor C1, and the delay time Δb1 is in a proportional relationship with the resistor R2 and the resonant capacitor C2, where V th is the input high-level threshold voltage of the Schmitt inverter, V th = 2.5V, V in is the high-level voltage of the V_PWM signal.

[0041]

[0042]

[0043] The control circuit of the forced-resonant soft-switching flyback power converter of the present invention is shown in the forced-resonant soft-switching flyback power conversion circuit diagram during specific implementation as Figure 7 shown. The dashed box 1 in the figure is a common single-ended flyback converter, which includes a power conversion circuit, a sampling error amplification circuit, and a PWM modulation circuit. The PWM signal output by the PWM controller in the circuit is input to the V_PWM terminal in the present invention. After being transformed and transmitted by the circuit of the present invention, two signals OUT1 and OUT2 are output. OUT1 is used to drive the front-stage power MOS transistor Q1 in the single-ended flyback converter, and OUT2 is used to drive the forced-resonant switch Q2.

Claims

1. A forced-resonance soft-switching flyback power conversion circuit, characterized in that A control circuit and a single-ended flyback converter including a forced-resonance soft-switching flyback power converter. The control circuit includes a Schmitt inverter U1, a Schmitt inverter U2, a Schmitt inverter U3, and a high-speed AND gate U4; The input terminals of the Schmitt inverter U2 are all connected to the anode of the diode D2, one end of the resistor R2, and one end of the resonant capacitor C2. The output terminal of the Schmitt inverter U2 is connected to the input terminal of the Schmitt inverter U3; The input terminals of the Schmitt inverter U1 are all connected to the anode of the diode D1, one end of the resistor R1, and one end of the resonant capacitor C1. The output terminal of the Schmitt inverter U1 is connected to the input terminal of the high-speed AND gate U4; The other ends of the resonant capacitor C1 and the resonant capacitor C2 are both grounded; The output terminal of the PWM controller in the single-ended flyback converter is simultaneously connected to the cathode of the diode D2, the other end of the resistor R2, the cathode of the diode D1, the other end of the resistor R1, and the input terminal of the high-speed AND gate U4. The output terminal of the Schmitt inverter U3 is connected to the front-stage power MOS transistor Q1. The output terminal of the high-speed AND gate U4 is connected to the forced-resonance switch Q2.

2. The forced resonant soft-switching flyback power conversion circuit according to claim 1, wherein The models of the Schmitt inverter U1, the Schmitt inverter U2, and the Schmitt inverter U3 are all SN74HC14.

3. The forced-resonant soft-switching flyback power conversion circuit according to claim 1, wherein The model of the high-speed AND gate U4 is SN74HC08.

4. The forced resonant soft-switching flyback power conversion circuit according to claim 1, characterized in that, The diodes D1 and D2 are both high-speed switching diodes.

5. The forced resonant soft-switching flyback power conversion circuit according to claim 1, wherein The resistor R1 and the resonant capacitor C1 form a delay turn-on circuit.

6. The forced resonant soft-switching flyback power conversion circuit according to claim 1, wherein The resistor R2 and the resonant capacitor C2 form a delay turn-on circuit.

7. The forced-resonance soft-switching flyback power conversion circuit according to claim 1, wherein The resistance values of the resistor R1 and the resistor R2 are both 1k - 10k ohms.

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