A gain-adjustable active balun circuit

Abstract

The present invention provides a gain-adjustable active balun circuit, which relates to the technical field of semiconductor devices. It includes an input matching network, a gain control circuit, a phase compensation balun, a first bias circuit, and a second bias circuit. By introducing a three-bit digital control structure, the present invention realizes 8 amplification states of the active balun, and solves the applicability problem of receiving / transmitting strong and weak signals of a radio frequency transceiver in different working environments according to different application scenarios. The phase compensation balun circuit adopts a cascaded structure of three active baluns, which can greatly reduce the phase error and amplitude error brought by a single balun, solve the amplitude imbalance and phase imbalance problems of the traditional active balun structure at high frequencies, and has high practical application value.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a three-bit numerically controlled active balun circuit, which can be applied to radio and baseband video, radar, transmitters, satellites, telephone networks, and wireless network modems. Background Art

[0002] In a radio frequency transceiver system, the receiving front end is one of the key modules. However, signal transmitters usually emit single-ended signals. In order to eliminate the glitches and interference in the signals and enhance the system's control over common-mode signals, it is necessary to convert the received signals into differential signals. For example, differential signals can enhance the fundamental wave suppression in a balanced frequency doubler, the port-to-port isolation in a mixer, and the bandwidth in a balanced amplifier. A balun circuit is a good choice. Nowadays, mobile terminals are widely popularized, and the working environments of devices are diverse. In order to adapt to the normal operation of devices in various signal receiving and transmitting environments, when the received signal is weak, it is necessary to increase the overall gain of the radio frequency transceiver, and when the received signal is strong, it is necessary to appropriately reduce the gain. Therefore, according to the differences in the device working environments, it is necessary to adjust the gain of the radio frequency transceiver to cope with the working situations in different environments. Summary of the Invention

[0003] In view of this, the present invention provides a gain-adjustable active balun circuit, which introduces a three-bit numerically controlled structure to achieve 8 amplification states of the active balun, and sets the active balun in different gain states according to different application scenarios. When receiving and transmitting weak signals, the active balun is set to the high-gain mode. At the same time, a phase compensation technology is introduced to reduce the amplitude imbalance and phase imbalance at high frequencies; a bias circuit based on diode connection is used to provide a stable gate bias. By introducing a three-bit numerically controlled structure and three baluns with the same structure, 8 amplification states of the active balun are realized, solving the applicability problem of the radio frequency transceiver for receiving and transmitting strong and weak signals in different working environments, and solving the amplitude imbalance and phase imbalance problems of the traditional active balun structure at high frequencies.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] A gain-adjustable active balun circuit includes an input matching network, a gain control circuit, a phase compensation balun, a first bias circuit, and a second bias circuit;

[0006] The input signal is connected to the input end of the input matching network, and the output end of the input matching network is connected to the signal input end of the gain control circuit; the control input end of the gain control circuit is connected externally, and the signal output end is connected to the input end of the phase compensation balun; the first bias circuit is connected to the gain control circuit and the phase compensation balun respectively, and the second bias circuit is connected to the phase compensation balun; the output end of the phase compensation balun is connected to the output signal end;

[0007] The input signal flows into the gain control circuit through the input matching network. The first bias circuit provides a controllable bias voltage for the gain control circuit and the phase compensation balun. The gain control circuit amplifies the signal through gain control, and the amplified signal is transmitted to the phase compensation balun. The second bias circuit provides a controllable bias voltage for the phase compensation balun, and the phase compensation balun finally realizes differential signal output.

[0008] Among them, the gain control circuit includes three cascode amplifier circuits with the same structure, three signal control circuits with the same structure, and a first load resistor RL1;

[0009] The first cascode amplifier circuit includes a common-source transistor M1 and a common-gate transistor M2. The first signal control circuit includes an AC ground capacitor C1 and a high resistance R S1 ; the gate terminal of the common-source transistor M1 is connected to the output end of the input matching network, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M2; the drain terminal of the common-gate transistor M2 is connected to one end of the first load resistor R L1 , the gate terminal is simultaneously connected to one end of the AC ground capacitor C1 and the high resistance R S1 , the other end of the first load resistor R L1 is connected to the power supply voltage VDD, the other end of the AC ground capacitor C1 is connected to GND, and the other end of the high resistance R S1 is connected to the control signal S1;

[0010] The second cascode amplifier circuit includes a common-source transistor M3 and a common-gate transistor M4. The second signal control circuit includes an AC ground capacitor C2 and a high resistance R S2 ; the gate terminal of the common-source transistor M3 is connected to the gate terminal of the common-source transistor M1, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M4; the drain terminal of the common-gate transistor M4 is connected to the drain terminal of the common-gate transistor M2, the gate terminal is simultaneously connected to one end of the AC ground capacitor C2 and the high resistance R S2 , the other end of the AC ground capacitor C2 is connected to GND, and the other end of the high resistance R S2 is connected to the control signal S2;

[0011] The third cascode amplifier circuit includes a common-source transistor M5 and a common-gate transistor M6. The third signal control circuit includes an AC ground capacitor C3 and a high resistance R S3; The gate terminal of the common-source transistor M5 is connected to the gate terminal of the common-source transistor M3, the gate terminal of the common-source transistor M1, and one end of the first bias resistor R1 respectively, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M6; the drain terminal of the common-gate transistor M6 is connected to the drain terminal of the common-gate transistor M4, and the gate terminal is connected to the AC ground capacitor C3 and the high impedance R S3 at one end, the other end of the AC ground capacitor C3 is connected to the ground GND, and the high impedance R S3 at the other end is connected to the control signal S3; the drain terminal of the transistor M6 is connected to the drain terminal of the transistor M2 in the first common-source-common-gate amplifier circuit, one end of the first load resistor R L1 and the drain terminal of the transistor M4 in the second common-source-common-gate amplifier circuit respectively as the output terminal of the gain control circuit to be connected to the phase compensation balun, and the other end of the first bias resistor R1 is connected to the first bias circuit.

[0012] Among them, the phase compensation balun is composed of three common-source-common-source structure active baluns a, b, and c connected; the input terminal of the common-source-common-source structure active balun a is connected to the output terminal of the gain control circuit, and the differential output terminals are connected to the input terminals of the active balun b and the active balun c respectively; the in-phase output terminals of the active balun b and the active balun c are connected together and connected to the output signal terminal;

[0013] The common-source-common-source structure active balun a includes the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourth DC-blocking capacitor C4, the fifth DC-blocking capacitor C5, the second load resistor R L2 , the second 'load resistor R' L2 , the second bias resistor R2, the third bias resistor R3, the eighth bias resistor R8, and the ninth bias resistor R9; the common-source-common-source structure active balun b includes the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the sixth DC-blocking capacitor C6, the seventh DC-blocking capacitor C7, the third load resistor R L3 , the third 'load resistor R' L3 , the fourth bias resistor R4, the fifth bias resistor R5, the tenth bias resistor R10, and the eleventh bias resistor R11; the common-source-common-source structure active balun c includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the eighth DC-blocking capacitor C8, the ninth DC-blocking capacitor C9, the sixth bias resistor R6, the seventh bias resistor R7, the twelfth bias resistor R12, and the thirteenth bias resistor R13;

[0014] One end of the fourth DC-blocking capacitor C4 is connected to the output terminal of the gain control circuit. The gate terminal of the seventh transistor M7 is simultaneously connected to the other end of the fourth DC-blocking capacitor C4 and one end of the second bias resistor R2. The other end of the second bias resistor R2 is respectively connected to one end of the first bias resistor R1, one end of the third bias resistor R3, one end of the fourth bias resistor R4, one end of the fifth bias resistor R5, one end of the sixth bias resistor R6, one end of the seventh bias resistor R7, and the first bias circuit. The drain terminal of the seventh transistor M7 is simultaneously connected to the source terminal of the ninth transistor M9 and one end of the fifth DC-blocking capacitor C5. The gate terminal of the eighth transistor M8 is simultaneously connected to the other end of the fifth DC-blocking capacitor C5 and the other end of the third bias resistor R3. The gate terminal of the ninth transistor M9 is connected to one end of the eighth bias resistor R8. The gate terminal of the tenth transistor M10 is connected to one end of the ninth bias resistor R9. The source terminal of the tenth transistor M10 is connected to the drain terminal of the eighth transistor M8. One end of the second load resistor R L2 is connected to the drain terminal of the ninth transistor M9. One end of the second 'load resistor R' L2 is respectively connected to one end of the eighth DC-blocking capacitor C8 and the drain terminal of the tenth transistor M10. One end of the second load resistor R L2 and the other end of the second 'load resistor R'L2 are respectively connected to VDD. The gate terminal of the eleventh transistor M11 is simultaneously connected to one end of the sixth DC-blocking capacitor C6 and the other end of the fourth bias resistor R4. The other end of the sixth DC-blocking capacitor C6 is connected to the drain terminal of the ninth transistor M9. The drain terminal of the eleventh transistor M11 is simultaneously connected to one end of the seventh DC-blocking capacitor C7 and the source terminal of the thirteenth transistor M13. The gate terminal of the twelfth transistor M12 is simultaneously connected to the other end of the seventh DC-blocking capacitor C7 and the other end of the fifth bias resistor R5. The drain terminal of the twelfth transistor M12 is connected to the source terminal of the fourteenth transistor M14. The gate terminal of the thirteenth transistor M13 is connected to one end of the tenth bias resistor R10. The gate terminal of the fourteenth transistor M14 is connected to one end of the eleventh bias resistor R11. One end of the third load resistor R L3 is connected to the drain terminal of the thirteenth transistor M13. One end of the third 'load resistor R' L3 is connected to the drain terminal of the fourteenth transistor M14. One end of the third load resistor R L3 and the third 'load resistor R' L3The other ends are respectively connected to VDD; the gate terminal of the fifteenth transistor M15 is simultaneously connected to the other end of the eighth DC-blocking capacitor C8 and the other end of the sixth bias resistor R6, the drain terminal of the fifteenth transistor M15 is simultaneously connected to one end of the ninth DC-blocking capacitor C9 and the source terminal of the seventeenth transistor M17, the gate terminal of the sixteenth transistor M16 is simultaneously connected to the other end of the ninth DC-blocking capacitor C9 and the other end of the seventh bias resistor R7, the drain terminal of the sixteenth transistor M16 is connected to the source terminal of the eighteenth transistor M18, the gate terminal of the seventeenth transistor M17 is connected to one end of the twelfth bias resistor R12, the gate terminal of the eighteenth transistor M18 is connected to one end of the thirteenth bias resistor R13, the other end of the eighth bias resistor R8 is respectively connected to the other end of the ninth bias resistor R9, the other end of the tenth bias resistor R10, the other end of the eleventh bias resistor R11, the other end of the twelfth bias resistor R12, the other end of the thirteenth bias resistor R13 and the second bias circuit, and one end of the third load resistor R L3 is respectively connected to one end of the third 'load resistor R' L3 and the power supply VDD, and the other end of the third load resistor R L3 is respectively connected to the drain terminal of the thirteenth transistor M13 and the drain terminal of the eighteenth transistor M18 and outputs as one end of the differential output signal, and the other end of the third 'load resistor R' L3 is respectively connected to the drain terminal of the fourteenth transistor M14 and the drain terminal of the seventeenth transistor M17 and outputs as the other end of the differential output signal.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] First, since the present invention adopts a three-way cascode circuit structure in the gain control circuit, and the drain terminals of the cascode transistors in the three-way cascode amplifier circuit are connected in sequence, and these three-way signals are output and added through the drain terminals, the gain of the device of the present invention is improved.

[0017] Second, since the present invention adds a three-way signal control circuit structure to the traditional active balun structure, and realizes the gain change through three-way control signals. According to different application environments, when receiving and transmitting weak signals, all three-way control signals are turned on to achieve high gain; when receiving and transmitting strong signals, only the first control signal is turned on, and the second and third control signals are turned off to achieve low gain.

[0018] Third, since the present invention introduces a phase compensation circuit, the differential signal generated by the first-stage balun is input to the second-stage balun to generate two-way differential signals, and they are cross-synthesized pairwise, optimizing the amplitude imbalance and phase imbalance problems of the device of the present invention.

[0019] Fourth, since the present invention adopts an input impedance matching network and optimizes the input matching of the entire inventive device by adjusting the resonance point of the matching network. Description of the Drawings

[0020] Figure 1 It is a structural block diagram of a gain-adjustable active balun circuit in an embodiment of the present invention.

[0021] Figure 2 It is a specific implementation schematic diagram of a gain-adjustable active balun circuit in an embodiment of the present invention.

[0022] Figure 3 It is the simulation result of phase error in an embodiment of the present invention.

[0023] Figure 4 It is the simulation result of amplitude error in an embodiment of the present invention.

[0024] Figure 5 It is the simulation result of S21 parameter in an embodiment of the present invention. Detailed Description of the Invention

[0025] The working principle of the present invention will be described in detail below with reference to the drawings.

[0026] Figure 1 It is a structural block diagram of a gain-adjustable active balun circuit of the present invention. The present invention includes an input matching network 1, a gain control circuit 2, a phase compensation balun 3, a first bias circuit 4, and a second bias circuit 5.

[0027] The input signal is connected to the input end of the input matching network. The output end of the input matching network 1 is connected to the signal input end of the gain control circuit 2; the control input end of the gain control circuit 2 is connected to the outside, and the signal output end is connected to the input end of the phase compensation balun 3; the first bias circuit 4 is respectively connected to the gain control circuit 2 and the phase compensation balun 3, and the second bias circuit 5 is connected to the phase compensation balun 3; the output end of the phase compensation balun 3 is connected to the output signal end;

[0028] The input signal flows into the gain control circuit 2 through the input matching network 1. The first bias circuit 4 provides a controllable bias voltage for the gain control circuit 2 and the phase compensation balun 3. The gain control circuit 2 amplifies the signal through gain control, and the amplified signal is transmitted to the phase compensation balun 3. The second bias circuit 5 provides a controllable bias voltage for the phase compensation balun 3, and the phase compensation balun 3 finally realizes differential signal output.

[0029] Figure 2 Shown is a specific implementation schematic diagram of a gain-adjustable active balun circuit of the present invention. The input matching circuit 1 consists of an input inductor L P , an input capacitor C PThey are connected in series in turn to form a resonant network. By adjusting the inductance value of the input inductor LP, series resonance is generated at the center frequency point to cancel the parasitic capacitance of the circuit and improve the matching degree. In this example, the input inductor L is taken but not limited to P The inductance value is 2 nH, and the input capacitance C P The value is 6 pF.

[0030] The gain control circuit 2 includes three cascode amplifier circuits with the same structure, three signal control circuits with the same structure, and a first load resistor RL1;

[0031] The first cascode amplifier circuit includes a common-source transistor M1 and a common-gate transistor M2. The first signal control circuit includes an AC ground capacitor C1 and a high resistor R S1 ; The gate terminal of the common-source transistor M1 is connected to the output terminal of the input matching network, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M2; The drain terminal of the common-gate transistor M2 is connected to one end of the first load resistor R L1 and the gate terminal is simultaneously connected to one end of the AC ground capacitor C1 and the high resistor R S1 ; The other end of the first load resistor R L1 is connected to the power supply voltage VDD, the other end of the AC ground capacitor C1 is connected to GND, and the other end of the high resistor R S1 is connected to the control signal S1;

[0032] The second cascode amplifier circuit includes a common-source transistor M3 and a common-gate transistor M4. The second signal control circuit includes an AC ground capacitor C2 and a high resistor R S2 ; The gate terminal of the common-source transistor M3 is connected to the gate terminal of the common-source transistor M1, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M4; The drain terminal of the common-gate transistor M4 is connected to the drain terminal of the common-gate transistor M2, and the gate terminal is simultaneously connected to one end of the AC ground capacitor C2 and the high resistor R S2 ; The other end of the AC ground capacitor C2 is connected to GND, and the other end of the high resistor R S2 is connected to the control signal S2;

[0033] The third cascode amplifier circuit includes a common-source transistor M5 and a common-gate transistor M6. The third signal control circuit includes an AC ground capacitor C3 and a high resistor R S3 ; The gate terminal of the common-source transistor M5 is respectively connected to the gate terminal of the common-source transistor M3, the gate terminal of the common-source transistor M1, and one end of the first bias resistor R1. The source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M6; The drain terminal of the common-gate transistor M6 is connected to the drain terminal of the common-gate transistor M4, and the gate terminal is simultaneously connected to one end of the AC ground capacitor C3 and the high resistor R S3 ; The other end of the AC ground capacitor C3 is connected to GND, and the other end of the high resistor R S3The other end is connected to the control signal S3; the drain ends of the transistors M6 are respectively connected to the drain end of the transistor M2 in the first cascode amplifier circuit and one end of the first load resistor R L1 One end of and the drain end of the transistor M4 in the second cascode amplifier circuit are connected as the output end of the gain control circuit and connected to the phase compensation balun, and the other end of the first bias resistor R1 is connected to the first bias circuit.

[0034] The width-to-length ratio dimensions of the cascode transistors and the cascode transistors in each path are the same. In this example, the width and length of the cascode transistor M1 in the first cascode amplifier circuit are 20um and 60nm respectively; the width and length of the cascode transistor M3 in the second cascode amplifier circuit are 40um and 120nm respectively; the width and length of the cascode transistor M5 in the third cascode amplifier circuit are 60um and 180nm respectively.

[0035] When the control signal of the first path signal control circuit is turned on, S1 is 1.4V, and when it is turned off, S1 is 0V. The control signal states of the second and third path signal control circuits are the same as those of the first path.

[0036] (end)The phase compensation balun 3 is composed of three cascode-cascode structure active baluns a, b, and c connected; the input end of the cascode-cascode structure active balun a is connected to the output end of the gain control circuit, and the differential output ends are respectively connected to the input ends of the cascode-cascode structure active balun b and the cascode-cascode structure active balun c; the in-phase output ends of the cascode-cascode structure active balun b and the cascode-cascode structure active balun c are connected together and connected to the output signal end;

[0037] The cascode-cascode structure active balun a includes the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourth DC-blocking capacitor C4, the fifth DC-blocking capacitor C5, the second load resistor R L2 And the second load resistor R' L2 The cascode-cascode structure active balun b includes the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the sixth DC-blocking capacitor C6, the seventh DC-blocking capacitor C7, the third load resistor R L3 And the third load resistor R' L3, the fourth bias resistor R4, the fifth bias resistor R5, the tenth bias resistor R10, and the eleventh bias resistor R11; the common-source common-source structure active balun c includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the eighth DC-blocking capacitor C8, the ninth DC-blocking capacitor C9, the sixth bias resistor R6, the seventh bias resistor R7, the twelfth bias resistor R12, and the thirteenth bias resistor R13;

[0038] One end of the fourth DC-blocking capacitor C4 is connected to the output end of the gain control circuit. The gate terminal of the seventh transistor M7 is simultaneously connected to the other end of the fourth DC-blocking capacitor C4 and one end of the second bias resistor R2. The other end of the second bias resistor R2 is respectively connected to one end of the first bias resistor R1, one end of the third bias resistor R3, one end of the fourth bias resistor R4, one end of the fifth bias resistor R5, one end of the sixth bias resistor R6, one end of the seventh bias resistor R7, and the first bias circuit. The drain terminal of the seventh transistor M7 is simultaneously connected to the source terminal of the ninth transistor M9 and one end of the fifth DC-blocking capacitor C5. The gate terminal of the eighth transistor M8 is simultaneously connected to the other end of the fifth DC-blocking capacitor C5 and the other end of the third bias resistor R3. The gate terminal of the ninth transistor M9 is connected to one end of the eighth bias resistor R8. The gate terminal of the tenth transistor M10 is connected to one end of the ninth bias resistor R9. The source terminal of the tenth transistor M10 is connected to the drain terminal of the eighth transistor M8. One end of the second load resistor R L2 is connected to the drain terminal of the ninth transistor M9. One end of the second 'load resistor R' L2 is respectively connected to one end of the eighth DC-blocking capacitor C8 and the drain terminal of the tenth transistor M10. One end of the second load resistor R L2 and the other end of the second 'load resistor R' L2 are respectively connected to VDD; The gate terminal of the eleventh transistor M11 is simultaneously connected to one end of the sixth DC-blocking capacitor C6 and the other end of the fourth bias resistor R4. The other end of the sixth DC-blocking capacitor C6 is connected to the drain terminal of the ninth transistor M9. The drain terminal of the eleventh transistor M11 is simultaneously connected to one end of the seventh DC-blocking capacitor C7 and the source terminal of the thirteenth transistor M13. The gate terminal of the twelfth transistor M12 is simultaneously connected to the other end of the seventh DC-blocking capacitor C7 and the other end of the fifth bias resistor R5. The drain terminal of the twelfth transistor M12 is connected to the source terminal of the fourteenth transistor M14. The gate terminal of the thirteenth transistor M13 is connected to one end of the tenth bias resistor R10. The gate terminal of the fourteenth transistor M14 is connected to one end of the eleventh bias resistor R11. One end of the third load resistor R L3 is connected to the drain terminal of the thirteenth transistor M13. One end of the third 'load resistor R' L3 is connected to the drain terminal of the fourteenth transistor M14. One end of the third load resistor R L3 and the third 'load resistor R' L3The other ends are respectively connected to VDD; the gate terminal of the fifteenth transistor M15 is simultaneously connected to the other end of the eighth DC-blocking capacitor C8 and the other end of the sixth bias resistor R6, the drain terminal of the fifteenth transistor M15 is simultaneously connected to one end of the ninth DC-blocking capacitor C9 and the source terminal of the seventeenth transistor M17, the gate terminal of the sixteenth transistor M16 is simultaneously connected to the other end of the ninth DC-blocking capacitor C9 and the other end of the seventh bias resistor R7, the drain terminal of the sixteenth transistor M16 is connected to the source terminal of the eighteenth transistor M18, the gate terminal of the seventeenth transistor M17 is connected to one end of the twelfth bias resistor R12, the gate terminal of the eighteenth transistor M18 is connected to one end of the thirteenth bias resistor R13, the other end of the eighth bias resistor R8 is respectively connected to the other end of the ninth bias resistor R9, the other end of the tenth bias resistor R10, the other end of the eleventh bias resistor R11, the other end of the twelfth bias resistor R12, the other end of the thirteenth bias resistor R13 and the second bias circuit, and one end of the third load resistor R L3 is respectively connected to one end of the third' load resistor R' L3 and the power supply VDD, and the other end of the third load resistor R L3 is respectively connected to the drain terminal of the thirteenth transistor M13 and the drain terminal of the eighteenth transistor M18 as one end of the differential output signal for output, and the other end of the third' load resistor R' L3 is respectively connected to the drain terminal of the fourteenth transistor M14 and the drain terminal of the seventeenth transistor M17 as the other end of the differential output signal for output.

[0039] In this embodiment, the power supply voltage VDD is set to 1.8V, the width-to-length ratio of the seventh transistor M7 is 80um / 60nm, the width-to-length ratio of the eighth transistor M8 is 64um / 60nm, the width-to-length ratio of the eleventh transistor M11 is 16um / 60nm, the width-to-length ratio of the twelfth transistor M12 is 32um / 60nm, the width-to-length ratio of the fifteenth transistor M15 is 16um / 60nm, and the width-to-length ratio of the sixteenth transistor M16 is 32um / 60nm. The second load resistor R L2 and the third load resistor R L3 are both 100 ohms.

[0040] The first bias circuit 4 includes a first bias transistor M B1 , a second bias transistor M B2 , and a first bias resistor R B1 .

[0041] The second bias circuit 5 includes a third bias transistor M B3 , a fourth bias transistor M B4 , a fifth bias transistor M B5 , and a second bias resistor R B2 .

[0042] The specific working principle of the above gain-adjustable active balun circuit is as follows:

[0043] In each individual balun structure of the phase compensation balun, a common-gate transistor is added on the basis of the traditional cascode structure balun circuit, effectively improving the isolation of the output differential signal. At the same time, it also forms a cascode structure, improving the isolation between the front and rear stages and enhancing stability. Adjust the sizes of the bias transistors and bias resistors in the first bias circuit and the second bias circuit so that the gate input bias voltage of the common-gate transistor is 1.4V and the gate input bias voltage of the cascode transistor is 700mV.

[0044] As Figure 2 shown, the single-ended input signal flows into the cascode balun a to obtain a pair of differential signals, and the flowing currents are set as II and I Q . These differential signals flow into the cascode balun b and the cascode balun c respectively to obtain two pairs of differential signals, and the flowing currents are set as I1, I2, I3, and I4. And the signals with the same phase are synthesized to generate the output differential signals I out+ , I out- . As the frequency increases, the existence of parasitic capacitance brings phase error and amplitude error. Assume the input signal is sin(wt), the cascode balun a will generate a phase error θ A , an amplitude error G A . The cascode balun b and the cascode balun c have the same structure and will generate a phase error θ B , an amplitude error G B . The following expressions can be obtained:

[0045] I1 = sinwt

[0046] I2 = (1 + G A )(1 + G B )sin(wt + θ A + θ B )

[0047] I3 = -(1 + G B )sin(wt + θ B )

[0048] I4 = -(1 + G A )sin(wt + θ A )

[0049]

[0050]

[0051] PE (Phase error) = ∠Iout+ -∠I out- -180°

[0052] It can be seen from the above formula that by adopting this active balun structure, that is, a cascaded structure of three active baluns, the large phase error and amplitude error caused by a single balun can be greatly reduced.

[0053] The sizes of the cascode transistors in the gain control circuit follow a ratio of 1:2:4, achieving relatively evenly spaced gain steps; through the on / off arrangement combinations of the three control signals (1 for on and 0 for off), 8 gain states are obtained, and one unstable gain state is discarded, finally obtaining 7 gain states. State 1 exhibits the lowest gain and the lowest power consumption, while state 7 achieves the best gain at the cost of greater power consumption. The gain state of the gain control circuit can ensure that the gain of the overall inventive device is reconfigured according to the requirements of the working environment.

[0054] The effects of the present invention will be further described below in conjunction with simulation experiments.

[0055] Simulation 1: An input port and an output port are respectively added to the input end and the output end of the circuit. The AC level of the input RF signal is set to 1V, and the frequency scanning range is [1G, 8G] Hz with a step of 100MHz. The phase and voltage gain of the output differential signal of the inventive device are simulated, and the phase error and amplitude error graphs are obtained by processing the data. The results are as Figure 3 and Figure 4 shown. Figure 3 The abscissa represents the frequency of the input RF signal, with the unit of GHz, and the ordinate represents the phase error, with the unit of °. Figure 4 The abscissa represents the frequency of the input RF signal, with the unit of GHz, and the ordinate represents the amplitude error, with the unit of mdB. It can be seen from Figure 5 that the phase error of the overall inventive device in Simulation Experiment 1 is less than 0.1°, and is less than 0.05° between 2GHz and 6GHz; the amplitude error of the overall inventive device in Simulation Experiment 1 is less than 150 mdB, meeting the high-precision requirements.

[0056] Simulation 2: An input port and an output port are respectively added to the input end and the output end of the circuit. The frequency scanning range of the input RF signal is set to [1G, 8G] Hz with a step of 100MHz. The gain of the inventive device is simulated. The results are as shown, where the abscissa represents the frequency of the input RF signal, with the unit of GHz, and the ordinate represents the gain of the circuit, with the unit of dB. It can be seen from Figure 5 Figure 5 that the gain of the active phase shifter of the present invention has a total of 7 curves, with the highest curve gain of 26 dB and the lowest curve gain of 16 dB, meeting the requirements of high gain and large step.

[0057] The above theoretical analysis and simulation results show that the gain-adjustable active balun circuit adopting the phase compensation balun structure in the present invention can, while achieving high precision, meet the gain requirements under different working environments by adjusting different gain states.

[0058] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those of ordinary skill in the art according to the disclosure of the present invention shall be included in the protection scope recorded in the claims.

Claims

1. An active balun circuit with adjustable gain, characterized in that, It includes an input matching network, a gain control circuit, a phase compensation balun, a first bias circuit, and a second bias circuit; The input signal is connected to the input terminal of the input matching network, and the output terminal of the input matching network is connected to the signal input terminal of the gain control circuit; the control input terminal of the gain control circuit is connected externally, and the signal output terminal is connected to the input terminal of the phase compensation balun; The first bias circuit is respectively connected to the gain control circuit and the phase compensation balun, and the second bias circuit is connected to the phase compensation balun; the output terminal of the phase compensation balun is connected to the output signal terminal; The input signal flows into the gain control circuit through the input matching network. The first bias circuit provides a controllable bias voltage for the gain control circuit and the phase compensation balun. The gain control circuit amplifies the signal through gain control. The amplified signal is transmitted to the phase compensation balun. The second bias circuit provides a controllable bias voltage for the phase compensation balun. The phase compensation balun finally realizes differential signal output; Among them, the gain control circuit includes three cascode amplifier circuits with the same structure, three signal control circuits with the same structure, and a first load resistor RL1; The phase compensation balun is composed of three cascode active baluns a, b, and c connected; the input terminal of the cascode active balun a is connected to the output terminal of the gain control circuit, and the differential output terminals are respectively connected to the input terminals of the active balun b and the active balun c; the in-phase output terminals of the active balun b and the active balun c are connected and connected to the output signal terminal.

2. The gain-adjustable active balun circuit according to claim 1, wherein The specific structure of the gain control circuit includes: The first common-source-common-gate amplifier circuit includes a common-source transistor M1 and a common-gate transistor M2, and the first signal control circuit includes an AC ground capacitor C1 and a high-resistance R S1 The gate terminal of the common-source transistor M1 is connected to the output terminal of the input matching network, the source terminal is grounded GND, and the drain terminal is connected to the source terminal of the common-gate transistor M2; the drain terminal of the common-gate transistor M2 is connected to the first load resistor R L1 One end is connected to the gate terminal, and the gate terminal is connected to the AC ground capacitor C1 and the high resistance R S1 One end of the first load resistor R L1 The other end of the AC capacitor C1 is connected to the ground GND, and the high resistance R S1 The other end is connected to the control signal S1; The second common-source common-gate amplifier circuit includes a common-source transistor M3 and a common-gate transistor M4, and the second signal control circuit includes an AC ground capacitor C2 and a high resistor R S2 ; the gate terminal of the common-source transistor M3 is connected to the gate terminal of the common-source transistor M1, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M4; the drain terminal of the common-gate transistor M4 is connected to the drain terminal of the common-gate transistor M2, and the gate terminal is simultaneously connected to one end of the AC ground capacitor C2 and the high resistor R S2 ; the other end of the AC ground capacitor C2 is connected to the ground GND, and the other end of the high resistor R S2 is connected to the control signal S2; The third common-source common-gate amplifier circuit includes a common-source transistor M5 and a common-gate transistor M6, and the third signal control circuit includes an AC ground capacitor C3 and a high impedance R. S3 The gate terminal of the common-source transistor M5 is respectively connected to the gate terminal of the common-source transistor M3, the gate terminal of the common-source transistor M1, and one end of the first bias resistor R1, the source terminal is grounded to GND, and the drain terminal is connected to the source terminal of the common-gate transistor M6; the drain terminal of the common-gate transistor M6 is connected to the drain terminal of the common-gate transistor M4, and the gate terminal is simultaneously connected to the AC ground capacitor C3 and the high impedance R. S3 One end is connected, the other end of the AC ground capacitor C3 is connected to the ground GND, and the other end of the high impedance R. S3 The other end is connected to the control signal S3; the drain terminal of the transistor M6 is respectively connected to the drain terminal of the transistor M2 in the first common-source common-gate amplifier circuit, one end of the first load resistor R. L1 One end and the drain terminal of the transistor M4 in the second common-source common-gate amplifier circuit are connected, and are used as the output terminal of the gain control circuit to be connected to the phase compensation balun, and the other end of the first bias resistor R1 is connected to the first bias circuit.

3. The gain-adjustable active balun circuit according to claim 2, wherein The specific structure of the phase compensation balun includes: The common-source / common-source structure active balun a includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a fourth DC-blocking capacitor C4, a fifth DC-blocking capacitor C5, a second load resistor R L2 , a second load resistor R' L2 , a second bias resistor R2, a third bias resistor R3, an eighth bias resistor R8, and a ninth bias resistor R9; the common-source / common-source structure active balun b includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a sixth DC-blocking capacitor C6, a seventh DC-blocking capacitor C7, a third load resistor R L3 , a third load resistor R' L3 , a fourth bias resistor R4, a fifth bias resistor R5, a tenth bias resistor R10, and an eleventh bias resistor R11; the common-source / common-source structure active balun c includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, an eighth DC-blocking capacitor C8, a ninth DC-blocking capacitor C9, a sixth bias resistor R6, a seventh bias resistor R7, a twelfth bias resistor R12, and a thirteenth bias resistor R13; One end of the fourth DC-blocking capacitor C4 is connected to the output terminal of the gain control circuit. The gate terminal of the seventh transistor M7 is simultaneously connected to the other end of the fourth DC-blocking capacitor C4 and one end of the second bias resistor R2. The other end of the second bias resistor R2 is respectively connected to one end of the first bias resistor R1, one end of the third bias resistor R3, one end of the fourth bias resistor R4, one end of the fifth bias resistor R5, one end of the sixth bias resistor R6, one end of the seventh bias resistor R7, and the first bias circuit. The drain terminal of the seventh transistor M7 is simultaneously connected to the source terminal of the ninth transistor M9 and one end of the fifth DC-blocking capacitor C5. The gate terminal of the eighth transistor M8 is simultaneously connected to the other end of the fifth DC-blocking capacitor C5 and the other end of the third bias resistor R3. The gate terminal of the ninth transistor M9 is connected to one end of the eighth bias resistor R8. The gate terminal of the tenth transistor M10 is connected to one end of the ninth bias resistor R9. The source terminal of the tenth transistor M10 is connected to the drain terminal of the eighth transistor M8. One end of the second load resistor R L2 is connected to the drain terminal of the ninth transistor M9. One end of the second 'load resistor R' L2 is respectively connected to one end of the eighth DC-blocking capacitor C8 and the drain terminal of the tenth transistor M10. One end of the second load resistor R L2 and the other end of the second 'load resistor R'L2 are respectively connected to VDD. The gate terminal of the eleventh transistor M11 is simultaneously connected to one end of the sixth DC-blocking capacitor C6 and the other end of the fourth bias resistor R4. The other end of the sixth DC-blocking capacitor C6 is connected to the drain terminal of the ninth transistor M9. The drain terminal of the eleventh transistor M11 is simultaneously connected to one end of the seventh DC-blocking capacitor C7 and the source terminal of the thirteenth transistor M13. The gate terminal of the twelfth transistor M12 is simultaneously connected to the other end of the seventh DC-blocking capacitor C7 and the other end of the fifth bias resistor R5. The drain terminal of the twelfth transistor M12 is connected to the source terminal of the fourteenth transistor M14. The gate terminal of the thirteenth transistor M13 is connected to one end of the tenth bias resistor R10. The gate terminal of the fourteenth transistor M14 is connected to one end of the eleventh bias resistor R11. One end of the third load resistor R L3 is connected to the drain terminal of the thirteenth transistor M13. One end of the third 'load resistor R' L3 is connected to the drain terminal of the fourteenth transistor M14. One end of the third load resistor R L3 and the third 'load resistor R' L3 The other ends are respectively connected to VDD; the gate terminal of the fifteenth transistor M15 is simultaneously connected to the other end of the eighth DC-blocking capacitor C8 and the other end of the sixth bias resistor R6, the drain terminal of the fifteenth transistor M15 is simultaneously connected to one end of the ninth DC-blocking capacitor C9 and the source terminal of the seventeenth transistor M17, the gate terminal of the sixteenth transistor M16 is simultaneously connected to the other end of the ninth DC-blocking capacitor C9 and the other end of the seventh bias resistor R7, the drain terminal of the sixteenth transistor M16 is connected to the source terminal of the eighteenth transistor M18, the gate terminal of the seventeenth transistor M17 is connected to one end of the twelfth bias resistor R12, the gate terminal of the eighteenth transistor M18 is connected to one end of the thirteenth bias resistor R13, the other end of the eighth bias resistor R8 is respectively connected to the other end of the ninth bias resistor R9, the other end of the tenth bias resistor R10, the other end of the eleventh bias resistor R11, the other end of the twelfth bias resistor R12, the other end of the thirteenth bias resistor R13 and the second bias circuit, and one end of the third load resistor R L3 is respectively connected to one end of the third' load resistor R' L3 and the power supply VDD, and one end of the third load resistor R L3 is respectively connected to the drain terminal of the thirteenth transistor M13 and the drain terminal of the eighteenth transistor M18 to output as one end of the differential output signal, and one end of the third' load resistor R' L3 is respectively connected to the drain terminal of the fourteenth transistor M14 and the drain terminal of the seventeenth transistor M17 to output as the other end of the differential output signal.

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