A high-voltage side current comparison circuit

Abstract

The present application discloses a high-voltage side current comparison circuit. By adding a first transistor, a second transistor, a first control voltage input port, and an offset voltage generation module to the current comparison circuit, the first transistor is connected to the first voltage input port, the second transistor is connected to the second voltage input port, and the offset voltage generation module is connected to the current mirror module, so that the first transistor and the second transistor form a high-voltage input pair of transistors, forming a high-voltage resistant structure to block high voltage. At the same time, an offset voltage is built in through the offset voltage generation module to effectively control the flip threshold.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and particularly to a high-voltage side current comparison circuit. Background Art

[0002] In recent years, current-mode circuits have received increasing attention due to their advantages such as small area, high speed, and low power consumption. A very important basic unit in current-mode circuits is the current comparator, which has now been widely used in various linear and non-linear integrated circuits, such as analog-to-digital converters (A / D converters), flip-flops, voltage-controlled oscillators, etc. However, traditional comparators cannot support high-voltage structures and are not suitable for the special application environments of automotive electronics. Therefore, how to provide a current comparator that can support high-voltage structures has become a technical problem to be solved at present. Summary of the Invention

[0003] In view of the above problems, the present application provides a high-voltage side current comparison circuit to overcome or at least partially solve the above problems. The specific solutions are as follows:

[0004] In a first aspect, an embodiment of the present application discloses a high-voltage side current comparison circuit, which includes: a first voltage input port, a second voltage input port, a first transistor, a second transistor, a first control voltage input port, a current mirror module, an offset voltage generation module, a third transistor, a fourth transistor, a second control voltage input port, and an output port of the circuit;

[0005] The first voltage input port is connected to the drain terminal of the first transistor;

[0006] The gate terminal of the first transistor is connected to the first control voltage input port, and the source terminal of the first transistor is connected to the current mirror module;

[0007] The second voltage input port is connected to the drain terminal of the second transistor;

[0008] The gate terminal of the second transistor is connected to the first control voltage input port, and the source terminal of the second transistor is connected to the current mirror module;

[0009] The current mirror module is connected to the output port of the circuit; the current mirror module is connected to the drain terminal and the gate terminal of the third transistor; the current mirror module is connected to the offset voltage generation module; the current mirror module is used to generate a mirror current;

[0010] The offset voltage generation module is used to generate a built-in offset voltage;

[0011] The gate terminal of the third transistor is connected to the gate terminal of the fourth transistor, and the source terminal of the third transistor is connected to the second control voltage input port;

[0012] The second control voltage input port is connected to the source terminal of the fourth transistor, and the drain terminal of the fourth transistor is connected to the output port of the circuit.

[0013] Optionally, the current mirror module includes:

[0014] A fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0015] The drain terminal of the fifth transistor is connected to the source terminal of the first transistor, the gate terminal of the fifth transistor is connected to the gate terminal of the seventh transistor, and the source terminal of the fifth transistor is connected to the source terminal of the seventh transistor;

[0016] The source terminal of the sixth transistor is connected to the source terminal of the fifth transistor, the gate terminal of the sixth transistor is connected to the gate terminal of the seventh transistor, and the drain terminal of the sixth transistor is connected to the drain terminal of the third transistor;

[0017] The drain terminal of the seventh transistor is connected to the offset voltage generation module and the gate terminal of the seventh transistor;

[0018] The drain terminal of the eighth transistor is connected to the source terminal of the second transistor, the gate terminal of the eighth transistor is connected to the gate terminal of the ninth transistor, and the source terminal of the eighth transistor is connected to the source terminal of the ninth transistor;

[0019] The source terminal of the ninth transistor is connected to the source terminal of the tenth transistor, and the drain terminal of the ninth transistor is connected to the offset voltage generation module;

[0020] The gate terminal of the tenth transistor is connected to the gate terminal of the ninth transistor, and the drain terminal of the tenth transistor is connected to the output port of the circuit.

[0021] Optionally, the offset voltage generation module includes:

[0022] A first resistor, an eleventh transistor, a third voltage input port, and a first tail current source;

[0023] The gate terminal of the tenth transistor is connected to the drain terminal of the ninth transistor;

[0024] The first resistor is connected to the drain terminal of the ninth transistor, the first resistor is connected to the drain terminal of the seventh transistor, and the first resistor is connected to the drain terminal of the eleventh transistor;

[0025] The gate terminal of the eleventh transistor is connected to the third voltage input port, and the source terminal of the eleventh transistor is connected to the first tail current source;

[0026] The first tail current source is grounded.

[0027] Optionally, the offset voltage generation module includes:

[0028] A second resistor, a twelfth transistor, a fourth voltage input port, and a second tail current source;

[0029] The gate terminal of the ninth transistor is connected to the second resistor and the drain terminal of the seventh transistor, and the drain terminal of the ninth transistor is connected to the second resistor;

[0030] The second resistor is connected to the drain terminal of the twelfth transistor;

[0031] The gate terminal of the twelfth transistor is connected to the fourth voltage input port, and the source terminal of the twelfth transistor is connected to the second tail current source;

[0032] The second tail current source is grounded.

[0033] Optionally, the first transistor and the second transistor are high-voltage P-type field effect transistors; the third transistor and the fourth transistor are low-voltage N-type field effect transistors.

[0034] Optionally, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are low-voltage P-type field effect transistors.

[0035] Optionally, the eleventh transistor is a high-voltage N-type field effect transistor.

[0036] Optionally, the twelfth transistor is a high-voltage N-type field effect transistor.

[0037] Optionally, when the voltage input at the first voltage input port is greater than the voltage input at the second voltage input port, the output port of the circuit outputs a high level.

[0038] Optionally, when the voltage input at the second voltage input port is greater than the voltage input at the first voltage input port, the output port of the circuit outputs a low level.

[0039] Compared with the prior art, the present application has the following beneficial effects:

[0040] In this application, the drain terminal of the first transistor is connected to the first voltage input port, the gate terminal of the first transistor is connected to the first control voltage input port, the source terminal of the first transistor is connected to the current mirror module, the drain terminal of the second transistor is connected to the second voltage input port, the gate terminal of the second transistor is connected to the first control voltage input port, and the source terminal of the second transistor is connected to the current mirror module. Thus, by connecting the first transistor to the first voltage input port and the second transistor to the second voltage input port, the first transistor and the second transistor form a high-voltage-resistant structure, avoiding damage to circuit devices caused by excessive input voltage of the circuit. Moreover, the built-in offset voltage is generated by the offset voltage generation module, effectively controlling the flip threshold of the circuit. Brief Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative efforts.

[0042] Figure 1 Structural schematic diagram of a high-side current comparison circuit provided by an embodiment of the present application;

[0043] Figure 2 Structural schematic diagram of another high-side current comparison circuit provided by an embodiment of the present application;

[0044] Figure 3 Structural schematic diagram of yet another high-side current comparison circuit provided by an embodiment of the present application. Detailed Description of the Embodiments

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0046] In the description, claims, and the above-mentioned drawings of this application, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0047] When there is a need to compare currents or voltages, a current comparator is usually used to compare the magnitudes of input currents and determine the comparison result based on the signal output by the comparator, thereby achieving current comparison. However, existing current comparators cannot support high-voltage structures and are not suitable for applications in high-voltage environments.

[0048] In view of this, as Figure 1 shown, an embodiment of this application provides a high-side current comparison circuit, which includes: a first voltage input port INN, a second voltage input port INP, a first transistor M1, a second transistor M2, a first control voltage input port VL-1, a current mirror module 101, an offset voltage generation module 102, a third transistor M3, a fourth transistor M4, a second control voltage input port VL-2, and an output port OUT of the circuit;

[0049] The first voltage input port is connected to the drain terminal of the first transistor M1;

[0050] The gate terminal of the first transistor M1 is connected to the first control voltage input port VL-1, and the source terminal of the first transistor M1 is connected to the current mirror module 101;

[0051] The second voltage input port is connected to the drain terminal of the second transistor M2;

[0052] The gate terminal of the second transistor M2 is connected to the first control voltage input port VL-1, and the source terminal of the second transistor M2 is connected to the current mirror module 101;

[0053] The current mirror module 101 is connected to the output port OUT of the circuit; the current mirror module 101 is connected to the drain terminal and the gate terminal of the third transistor M3; the current mirror module 101 is connected to the offset voltage generation module 102; the current mirror module 101 is used to generate a mirror current;

[0054] The offset voltage generation module 102 is used to generate a built-in offset voltage;

[0055] The gate terminal of the third transistor M3 is connected to the gate terminal of the fourth transistor M4, and the source terminal of the third transistor M3 is connected to the second control voltage input port VL-2;

[0056] The second control voltage input port VL-2 is connected to the source terminal of the fourth transistor M4, and the drain terminal of the fourth transistor M4 is connected to the output port OUT of the circuit.

[0057] By connecting the gate terminal of the third transistor M3 to the gate terminal of the fourth transistor M4, and the source terminals of the third transistor M3 and the fourth transistor M4 are respectively connected to the second control voltage input port, that is, the third transistor M3 and the fourth transistor M4 adopt a cascode structure to form a current mirror. The current mirror module 101 mirrors the current I1 in the branch where the first transistor is located and the current I2 in the branch where the second transistor is located respectively to obtain the mirror currents I1_mirror and I2_mirror. The current mirror formed by the third transistor M3 and the fourth transistor M4 mirrors I1_mirror from the branch where the third transistor M3 is located to the branch where the fourth transistor M4 is located to form I3_mirror. I3_mirror corresponds to the first voltage input port INN, so that I3_mirror is compared with I2_mirror to obtain the corresponding output result.

[0058] It should be noted that the voltage input through the first control voltage input port VL-1 is lower than the voltages input through the first voltage input port and the second voltage input port, so as to ensure the normal operation of the first transistor M1 and the second transistor M2. Since the first transistor M1 and the second transistor M2 are connected back-to-back, the first transistor M1 and the second transistor M2 form a high-voltage-resistant structure to avoid damage to the circuit devices due to too high input voltage of the circuit.

[0059] As Figure 2 shown, in a possible implementation manner, the current mirror module includes:

[0060] A fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

[0061] The drain terminal of the fifth transistor M5 is connected to the source terminal of the first transistor M1, the gate terminal of the fifth transistor M5 is connected to the gate terminal of the seventh transistor M7, and the source terminal of the fifth transistor M5 is connected to the source terminal of the seventh transistor M7;

[0062] The source terminal of the sixth transistor M6 is connected to the source terminal of the fifth transistor M5, the gate terminal of the sixth transistor M6 is connected to the gate terminal of the seventh transistor M7, and the drain terminal of the sixth transistor M6 is connected to the drain terminal of the third transistor M3;

[0063] The drain terminal of the seventh transistor M7 is connected to the offset voltage generation module 102 and the gate terminal of the seventh transistor M7;

[0064] The drain terminal of the eighth transistor M8 is connected to the source terminal of the second transistor M2, the gate terminal of the eighth transistor M8 is connected to the gate terminal of the ninth transistor M9, and the source terminal of the eighth transistor M8 is connected to the source terminal of the ninth transistor M9;

[0065] The source terminal of the ninth transistor M9 is connected to the source terminal of the tenth transistor M10, and the drain terminal of the ninth transistor M9 is connected to the offset voltage generation module 102;

[0066] The gate terminal of the tenth transistor M10 is connected to the gate terminal of the ninth transistor M9, and the drain terminal of the tenth transistor M10 is connected to the output port OUT of the circuit.

[0067] The fifth transistor M5 and the seventh transistor M7 are connected in a back-to-back manner, and the sixth transistor M6 and the seventh transistor M7 form a proportional current mirror. The eighth transistor M8 and the ninth transistor M9 are connected in a back-to-back manner, and the ninth transistor M9 and the tenth transistor M10 form a proportional current mirror. Thus, the current mirror module generates mirror currents corresponding to the voltage V1 input by the first voltage input port INN and the voltage V2 input by the second input port INP respectively, so as to perform comparison of the mirror currents subsequently.

[0068] In a possible implementation manner, the offset voltage generation module 102 includes:

[0069] A first resistor R1, an eleventh transistor M11, a third voltage input port VCC-1, and a first tail current source IB-1;

[0070] The gate terminal of the tenth transistor M10 is connected to the drain terminal of the ninth transistor M9;

[0071] The first resistor R1 is connected to the drain terminal of the ninth transistor M9, the first resistor R1 is connected to the drain terminal of the seventh transistor, and the first resistor R1 is connected to the drain terminal of the eleventh transistor M11;

[0072] The gate terminal of the eleventh transistor M11 is connected to the third voltage input port VCC-1, and the source terminal of the eleventh transistor M11 is connected to the first tail current source IB-1;

[0073] The first tail current source IB-1 is grounded.

[0074] It should be noted that the first resistor R1 is used to generate the built-in offset voltage VOS, so as to effectively control the switching threshold of the circuit by establishing the offset voltage.

[0075] When the voltage input at the first voltage input port INN is greater than the voltage input at the second voltage input port INP, the output port of the circuit outputs a high level.

[0076] When the voltage input at the second voltage input port INP is greater than the voltage input at the first voltage input port INN, the output port of the circuit outputs a low level.

[0077] In the above circuit, the relationship between the result output by the output port of the circuit and the voltages input at the first voltage input port INN and the second voltage input port INP is specifically as follows: When the voltage value V1 input at the first voltage input port INN is greater than the sum of the voltage value V2 input at the second voltage input port INP and the built-in offset voltage VOS, it is determined that the current of the seventh transistor M7 is greater than the current of the ninth transistor M9, then the current mirrored by the corresponding sixth transistor M6 is greater than the current mirrored by the tenth transistor M10, and the output port OUT of the circuit outputs a high level.

[0078] When the voltage value V2 input at the second voltage input port INP is greater than the sum of the voltage value V1 input at the first voltage input port INN and the built-in offset voltage VOS, it is determined that the current of the ninth transistor M9 is greater than the current of the seventh transistor M7, then the current mirrored by the corresponding tenth transistor M10 is greater than the current mirrored by the sixth transistor M6, and the output port OUT of the circuit outputs a low level.

[0079] For ease of understanding, the relationship between the voltage V1 input at the first voltage input port INN, the voltage V2 input at the second voltage input port INP, the built-in offset voltage VOS, and the result output by the output port OUT of the circuit can be expressed as:

[0080] If V1 > V2 + VOS, the output port OUT of the circuit outputs a high level;

[0081] If V2 > V1 + VOS, the output port OUT of the circuit outputs a low level.

[0082] Thus, the relationship between the voltage value V1 input at the first voltage input port INN and the voltage value V2 input at the second voltage input port INP is determined according to the result output by the output port of the circuit.

[0083] As shown Figure 3 In a possible implementation, the offset voltage generation module 102 includes:

[0084] A second resistor R2, a twelfth transistor M12, a fourth voltage input port VCC-2, and a second tail current source IB-2;

[0085] The gate terminal of the ninth transistor M9 is connected to the second resistor R2 and the drain terminal of the seventh transistor M7, and the drain terminal of the ninth transistor M9 is connected to the second resistor R2;

[0086] The second resistor R2 is connected to the drain terminal of the twelfth transistor M12;

[0087] The gate terminal of the twelfth transistor M12 is connected to the fourth voltage input port VCC-2, and the source terminal of the twelfth transistor M12 is connected to the second tail current source IB-2;

[0088] The second tail current source IB-2 is grounded.

[0089] It should be noted that the second resistor R2 is used to generate the built-in offset voltage VOS. The relationship between the voltage V1 input by the first voltage input port INN, the voltage V2 input by the second voltage input port INP, the built-in offset voltage VOS, and the result output by the output port OUT of the circuit is the same as the above relationship principle and will not be elaborated here.

[0090] In a possible implementation, the first transistor and the second transistor M2 are high-voltage P-type field effect transistors; the third transistor M3 and the fourth transistor are low-voltage N-type field effect transistors.

[0091] By using high-voltage P-type field effect transistors as the first transistor and the second transistor M2, the first transistor and the second transistor M2 form an anti-high-voltage structure, avoiding damage to circuit devices caused by too high input voltage.

[0092] In a possible implementation, the fifth transistor, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are low-voltage P-type field effect transistors. Thus, the current mirror module 101 can accurately generate mirror currents corresponding to the first voltage input port INN and the second voltage input port INP respectively.

[0093] In a possible implementation, the eleventh transistor M11 is a high-voltage N-type field effect transistor.

[0094] In a possible implementation, the twelfth transistor M12 is a high-voltage N-type field effect transistor.

[0095] In the embodiment of the present application, the drain terminal of the first transistor is connected to the first voltage input port, the gate terminal of the first transistor is connected to the first control voltage input port, the source terminal of the first transistor is connected to the current mirror module, the drain terminal of the second transistor is connected to the second voltage input port, the gate terminal of the second transistor is connected to the first control voltage input port, and the source terminal of the second transistor is connected to the current mirror module. Thus, by connecting the first transistor to the first voltage input port and the second transistor to the second voltage input port, the first transistor and the second transistor form a high-voltage resistant structure, avoiding damage to circuit devices caused by too high input voltage of the circuit. Moreover, the built-in offset voltage is generated by the offset voltage generation module to effectively control the switching threshold of the circuit.

[0096] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0097] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-voltage side current comparison circuit, characterized in that, The circuit includes: a first voltage input port, a second voltage input port, a first transistor, a second transistor, a first control voltage input port, a current mirror module, an offset voltage generation module, a third transistor, a fourth transistor, a second control voltage input port, and an output port of the circuit; The first voltage input port is connected to the drain terminal of the first transistor; The gate terminal of the first transistor is connected to the first control voltage input port, and the source terminal of the first transistor is connected to the current mirror module; The second voltage input port is connected to the drain terminal of the second transistor; The gate terminal of the second transistor is connected to the first control voltage input port, and the source terminal of the second transistor is connected to the current mirror module; The current mirror module is connected to the output port of the circuit; the current mirror module is connected to the drain terminal and the gate terminal of the third transistor; the current mirror module is connected to the offset voltage generation module; the current mirror module is used to generate a mirror current; The offset voltage generation module is used to generate a built-in offset voltage; The gate terminal of the third transistor is connected to the gate terminal of the fourth transistor, and the source terminal of the third transistor is connected to the second control voltage input port; The second control voltage input port is connected to the source terminal of the fourth transistor, and the drain terminal of the fourth transistor is connected to the output port of the circuit.

2. The circuit according to claim 1, wherein The current mirror module includes: A fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The drain terminal of the fifth transistor is connected to the source terminal of the first transistor, the gate terminal of the fifth transistor is connected to the gate terminal of the seventh transistor, and the source terminal of the fifth transistor is connected to the source terminal of the seventh transistor; The source terminal of the sixth transistor is connected to the source terminal of the fifth transistor, the gate terminal of the sixth transistor is connected to the gate terminal of the seventh transistor, and the drain terminal of the sixth transistor is connected to the drain terminal of the third transistor; The drain terminal of the seventh transistor is connected to the offset voltage generation module and the gate terminal of the seventh transistor; The drain terminal of the eighth transistor is connected to the source terminal of the second transistor, the gate terminal of the eighth transistor is connected to the gate terminal of the ninth transistor, and the source terminal of the eighth transistor is connected to the source terminal of the ninth transistor; The source terminal of the ninth transistor is connected to the source terminal of the tenth transistor, and the drain terminal of the ninth transistor is connected to the offset voltage generation module; The gate terminal of the tenth transistor is connected to the gate terminal of the ninth transistor, and the drain terminal of the tenth transistor is connected to the output port of the circuit.

3. The circuit according to claim 2, wherein The offset voltage generation module includes: A first resistor, an eleventh transistor, a third voltage input port, and a first tail current source; The gate terminal of the tenth transistor is connected to the drain terminal of the ninth transistor; The first resistor is connected to the drain terminal of the ninth transistor, the first resistor is connected to the drain terminal of the seventh transistor, and the first resistor is connected to the drain terminal of the eleventh transistor; The gate terminal of the eleventh transistor is connected to the third voltage input port, and the source terminal of the eleventh transistor is connected to the first tail current source; The first tail current source is grounded.

4. The circuit according to claim 2, wherein, The offset voltage generation module includes: A second resistor, a twelfth transistor, a fourth voltage input port, and a second tail current source; The gate terminal of the ninth transistor is connected to the second resistor and the drain terminal of the seventh transistor, and the drain terminal of the ninth transistor is connected to the second resistor; The second resistor is connected to the drain terminal of the twelfth transistor; The gate terminal of the twelfth transistor is connected to the fourth voltage input port, and the source terminal of the twelfth transistor is connected to the second tail current source; The second tail current source is grounded.

5. The circuit according to claim 1, wherein The first transistor and the second transistor are high-voltage P-type field effect transistors; the third transistor and the fourth transistor are low-voltage N-type field effect transistors.

6. The circuit according to claim 2, wherein The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are low-voltage P-type field effect transistors.

7. The circuit according to claim 3, characterized in that, The eleventh transistor is a high-voltage N-type field effect transistor.

8. The circuit according to claim 4, wherein The twelfth transistor is a high-voltage N-type field effect transistor.

9. The circuit according to claim 3 or 4, characterized in that, When the voltage input at the first voltage input port is greater than the voltage input at the second voltage input port, the output port of the circuit outputs a high level.

10. The circuit according to claim 3 or 4, characterized in that, When the voltage input at the second voltage input port is greater than the voltage input at the first voltage input port, the output port of the circuit outputs a low level.

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