Gate drive integrated circuit

Abstract

The application relates to a gate drive integrated circuit, which receives and outputs a command signal through an isolation transmission module, then controls an upper bridge drive module to turn on or turn off an upper tube and controls a lower bridge drive module to turn on or turn off a lower tube according to the command signal by a dead zone control module, wherein the upper tube and the lower tube are not turned on at the same time; thus, the on-off states of two switch tubes in a half-bridge circuit are cooperatively controlled, the integrated degree of the whole circuit is high, the half-bridge circuit is more easily monitored by the upper tube and the lower tube, and therefore the safety is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a gate drive integrated circuit. BACKGROUND

[0002] The gate drive circuit is used for driving a half-bridge circuit. In driving the half-bridge circuit, the conventional way is usually to control the upper tube and the lower tube of the half-bridge circuit respectively by two independent drives, however, in order to realize the selective conduction of the upper tube and the lower tube, two independent drive processes need to be coordinated with each other.

[0003] The independent drive coordination process of the conventional way is not easy to control, and the upper tube and the lower tube are easy to be conducted at the same time, which is low in safety. SUMMARY

[0004] The present application provides a gate drive integrated circuit with high safety.

[0005] A gate drive integrated circuit applied to a half-bridge circuit, the gate drive integrated circuit comprising:

[0006] an upper bridge drive module connected with a gate of an upper tube of the half-bridge circuit;

[0007] a lower bridge drive module connected with a gate of a lower tube of the half-bridge circuit;

[0008] an isolation transmission module for receiving and outputting an instruction signal;

[0009] a dead zone control module connected with the isolation transmission module, the upper bridge drive module and the lower bridge drive module respectively, for controlling the upper bridge drive module to turn on or turn off the upper tube and controlling the lower bridge drive module to turn on or turn off the lower tube according to the instruction signal; wherein the upper tube and the lower tube are not conducted at the same time.

[0010] In one of the embodiments, the gate drive integrated circuit further comprises:

[0011] an over-temperature and over-current protection module connected with the dead zone control module, for instructing the dead zone control module to control the upper bridge drive module to turn off the upper tube and control the lower bridge drive module to turn off the lower tube if at least one of the temperature of the gate drive integrated circuit exceeding a temperature threshold or the current flowing through the lower tube exceeding a current threshold is detected.

[0012] In one of the embodiments, the dead zone control module is further used for generating an upper bridge control signal according to the instruction signal, and the upper bridge drive module comprises:

[0013] a high voltage level conversion unit connected with the dead zone control module, for outputting a first high voltage domain signal according to the upper bridge control signal.

[0014] The upper bridge negative voltage level conversion unit is connected with the high voltage level conversion unit, and is configured to output a first negative voltage domain signal according to the first high voltage domain signal.

[0015] The upper bridge gate drive unit is connected with the upper bridge negative voltage level conversion unit, and is configured to turn on or turn off the upper tube according to the first negative voltage domain signal.

[0016] In one embodiment, the upper bridge gate drive unit is further configured to: sequentially pull the gate voltage of the upper tube from a first voltage to a second voltage, and from the second voltage to a third voltage according to the first negative voltage domain signal, so as to turn on the upper tube; or

[0017] sequentially pull the gate voltage of the upper tube from the third voltage to the second voltage, and from the second voltage to the first voltage according to the first negative voltage domain signal, so as to turn off the upper tube.

[0018] The first voltage is the gate voltage when the upper tube is turned off, the third voltage is the gate voltage when the upper tube is turned on, and the voltage value of the second voltage is located in the voltage value range of the first voltage and the third voltage.

[0019] In one of the embodiments, the dead zone control module is further configured to generate a lower bridge control signal according to the instruction signal, and the lower bridge drive module comprises:

[0020] The lower bridge negative voltage level conversion unit is connected with the dead zone control module, and is configured to output a second negative voltage domain signal according to the lower bridge control signal.

[0021] The lower bridge gate drive unit is connected with the lower bridge negative voltage level conversion unit, and is configured to turn on or turn off the lower tube according to the second negative voltage domain signal.

[0022] In one of the embodiments, the lower bridge gate drive unit is further configured to:

[0023] sequentially pull the gate voltage of the lower tube from a fourth voltage to a fifth voltage, and from the fifth voltage to a sixth voltage according to the second negative voltage domain signal, so as to turn on the lower tube; or

[0024] sequentially pull the gate voltage of the lower tube from the sixth voltage to the fifth voltage, and from the fifth voltage to the fourth voltage according to the second negative voltage domain signal, so as to turn off the lower tube.

[0025] The fourth voltage is the gate voltage when the lower tube is turned off, the sixth voltage is the gate voltage when the lower tube is turned on, and the voltage value of the fifth voltage is located in the voltage value range of the fourth voltage and the sixth voltage.

[0026] In one of the embodiments, the gate drive integrated circuit further comprises:

[0027] a gate protection module, connected with the gate of the lower transistor and the upper bridge drive module respectively, for controlling the upper bridge drive module to turn off the upper transistor if the lower transistor is in the on state.

[0028] In one of the embodiments, the dead-time control module comprises a dead-time resistor; the dead-time control module is further used for controlling the upper bridge drive module to turn on the upper transistor after a delay of a dead-time, and controlling the lower bridge drive module to turn on the lower transistor after a delay of the dead-time, wherein the dead-time corresponds to the resistance of the dead-time resistor.

[0029] In one of the embodiments, the dead-time control module is further used for, if the instruction signal represents that the upper transistor and the lower transistor are to be turned on at the same time, controlling the upper bridge drive module to turn off the upper transistor, and controlling the lower bridge drive module to turn off the lower transistor.

[0030] In one of the embodiments, the isolation transmission module comprises a modulation sending unit, a high-voltage isolation capacitor and a signal demodulation unit.

[0031] The modulation sending unit is used for receiving the instruction signal, and modulating the instruction signal to obtain a high-frequency signal.

[0032] The high-voltage isolation capacitor is connected with the modulation sending unit, for coupling and transmitting the high-frequency signal to the signal demodulation unit.

[0033] The signal demodulation unit is connected with the high-voltage isolation capacitor and the dead-time control module respectively, for demodulating the high-frequency signal to obtain the instruction signal, and transmitting the instruction signal to the dead-time control module.

[0034] The gate drive integrated circuit described above receives and outputs the instruction signal through the isolation transmission module, and then controls the upper bridge drive module to turn on or turn off the upper transistor, and controls the lower bridge drive module to turn on or turn off the lower transistor according to the instruction signal by the dead-time control module, wherein the upper transistor and the lower transistor are not turned on at the same time; thereby realizing the cooperative control of the on states of the two transistors in the half-bridge circuit, and the integrated degree of the whole circuit is high, and it is easier to realize the simultaneous monitoring of the upper transistor and the lower transistor in the half-bridge circuit, so the safety is higher. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 a structural block diagram of the gate drive integrated circuit of one embodiment of the present application;

[0036] Figure 2 a structural block diagram of the gate drive integrated circuit of another embodiment of the present application;

[0037] Figure 3 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0038] Figure 4 A circuit structure schematic diagram of an upper bridge gate drive unit according to an embodiment of the present application;

[0039] Figure 5 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0040] Figure 6 A structure block diagram of a high voltage level conversion unit according to an embodiment of the present application;

[0041] Figure 7 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0042] Figure 8 A structure block diagram of an upper bridge negative voltage level conversion unit according to an embodiment of the present application;

[0043] Figure 9 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0044] Figure 10 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0045] Figure 11 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0046] Figure 12 A structure block diagram of a lower bridge negative voltage level conversion unit according to an embodiment of the present application;

[0047] Figure 13 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application;

[0048] Figure 14 A structure block diagram of a gate drive integrated circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0049] It should be understood that the specific embodiments described herein merely exemplify the application and do not limit the application.

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0051] It should be noted that all the direction indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the direction indications also change accordingly. The connection can be direct connection or indirect connection.

[0052] In addition, the descriptions such as "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0053] Figure 1 The structural block diagram of a gate drive integrated circuit of an embodiment is applied to a half-bridge circuit, as shown in the figure. Figure 1 The gate drive integrated circuit includes an upper bridge drive module 110, a lower bridge drive module 120, an isolation transmission module 130 and a dead zone control module 140. The upper bridge drive module 110 is connected to the gate of the upper tube M1 of the half-bridge circuit, the lower bridge drive module 120 is connected to the gate of the lower tube M2 of the half-bridge circuit, and the isolation transmission module 130 is used to receive and output a command signal. The dead zone control module 140 is connected to the isolation transmission module 130, the upper bridge drive module 110 and the lower bridge drive module 120, respectively, and is used to control the upper bridge drive module 110 to turn on or turn off the upper tube M1 and control the lower bridge drive module 120 to turn on or turn off the lower tube M2 according to the command signal. Wherein, the upper tube M1 and the lower tube M2 are not turned on at the same time.

[0054] It can be understood that the command signal can be sent by an external control host, and after the isolation transmission module 130 receives the command signal, the isolation transmission module 130 transmits the command signal to the dead zone control module 140 in an isolated communication mode. Wherein, the source of the upper tube M1 is connected to the positive power supply VDD, and the voltage of the positive power supply VDD is large, which means that the driving voltage transmitted by the upper bridge drive module 110 to the upper tube M1 is also large, which belongs to the high-voltage side, and the voltage value of the command signal is small, so the external control host sending the command signal can belong to the low-voltage side, and the isolation transmission module 130 can transmit the command signal in a capacitive isolation mode, so as to isolate the oscillation interference of the high-voltage side, and also avoid the influence of the overvoltage of the high-voltage side on the low-voltage side, thereby improving the anti-interference ability and safety of the whole circuit.

[0055] The isolation transmission module 130 can adopt a capacitive isolation mode to transmit the instruction signal. The instruction signal is modulated, transmitted through capacitive isolation, demodulated, and then transmitted to the dead-time control module 140.

[0056] The dead-time control module 140 can be connected to a resistor. By adjusting the resistance value of the resistor, the dead-time of the dead-time control module 140 can be adjusted. During the dead-time period, the dead-time control module 140 controls the upper tube M1 and the lower tube M2 to be both disconnected. In this way, the dead-time control module 140 can realize the selective conduction of the upper tube M1 and the lower tube M2 after receiving the instruction signal, thereby avoiding the damage of the upper tube M1 and the lower tube M2 caused by the straight-through condition.

[0057] Specifically, the instruction signal can include an upper tube M1 instruction signal and a lower tube M2 instruction signal. The upper tube M1 instruction signal is used to indicate the conduction or disconnection of the upper tube M1, and the lower tube M2 instruction signal is used to indicate the conduction or disconnection of the lower tube M2. The dead-time control module 140 can control the upper bridge drive module 110 to conduct the upper tube M1 and control the lower bridge drive module 120 to disconnect the lower tube M2 according to the instruction signal, or control the upper bridge drive module 110 to disconnect the upper tube M1 and control the lower bridge drive module 120 to conduct the lower tube M2 according to the instruction signal. In this way, the simultaneous control of the upper tube M1 and the lower tube M2 can be realized, thereby facilitating the cooperative operation of the upper tube M1 and the lower tube M2 and avoiding the straight-through condition of the upper tube M1 and the lower tube M2.

[0058] The upper tube M1 and the lower tube M2 can be MOS tubes, triodes, etc. Specifically, they can be wide-bandgap semiconductor tubes, such as GaN (gallium nitride) MOS tubes.

[0059] The gate drive integrated circuit of the embodiment receives and outputs the instruction signal through the isolation transmission module 130, and then controls the upper bridge drive module to conduct or disconnect the upper tube M1 and controls the lower bridge drive module to conduct or disconnect the lower tube M2 according to the instruction signal by the dead-time control module 140. The upper tube M1 and the lower tube M2 are not conducted at the same time, thereby realizing the cooperative control of the conduction states of the two switching tubes in the half-bridge circuit. The overall integration degree of the circuit is high, and the simultaneous monitoring of the upper tube M1 and the lower tube M2 in the half-bridge circuit is more easily realized, thereby being safer.

[0060] In one embodiment, the gate drive integrated circuit further includes an over-temperature and over-current protection module 150, as shown in Figure 2 The over-temperature and over-current protection module 150 is connected with the dead-time control module 140. If at least one of the temperature of the gate drive integrated circuit exceeding the temperature threshold or the current flowing through the lower bridge exceeding the current threshold is detected, the dead-time control module 140 is instructed to control the upper bridge drive module 110 to disconnect the upper tube M1 and control the lower bridge drive module to disconnect the lower tube M2.

[0061] The over-temperature and over-current protection module 150 can also be connected to the source of the lower transistor M2 to detect the current flowing through the lower transistor M2. The over-temperature and over-current protection module 150 can include a temperature sensing unit and an over-current detection unit. The temperature sensing unit can sense the temperature of the circuit and transmit the sensed temperature value to the dead-time control module 140. The over-current detection unit can be connected to the source of the lower transistor M2 to detect the current flowing through the lower bridge and transmit the detected current value to the dead-time control module 140. The dead-time control module 140 monitors the temperature and the current. When either of the temperature value and the current value is abnormal, the upper transistor M1 and the lower transistor M2 are simultaneously turned off. In this way, the over-temperature and over-current protection module 150 is used to monitor the current flowing through the lower bridge and the temperature of the entire gate drive integrated circuit, which can ensure that the circuit operates in a safe state.

[0062] In one embodiment, the dead-time control module 140 is also configured to generate an upper bridge control signal according to the instruction signal. The upper bridge drive module 110 includes a high-voltage level conversion unit 111, an upper bridge negative voltage level conversion unit 112, and an upper bridge gate drive unit 113, as shown in FIG. 1B. Figure 3 The high-voltage level conversion unit 111 is connected to the dead-time control module 140 and is configured to output a first high-voltage domain signal according to the upper bridge control signal. The upper bridge negative voltage level conversion unit 112 is connected to the high-voltage level conversion unit 111 and is configured to output a first negative voltage domain signal according to the first high-voltage domain signal. The upper bridge gate drive unit 113 is connected to the upper bridge negative voltage level conversion unit 112 and is configured to turn on or turn off the upper transistor M1 according to the first negative voltage domain signal.

[0063] It can be understood that the source of the upper transistor M1 is connected to the positive power supply VDD, and the voltage of the positive power supply VDD is relatively large, usually several hundred volts. The upper bridge control signal is usually several volts. Therefore, in order to control the drive of the upper transistor M1, the upper bridge control signal needs to be boosted. The high-voltage level conversion unit 111 converts the upper bridge control signal to obtain a first high-voltage domain signal. The first high-voltage domain signal can include a high-level signal and a low-level signal. The high-voltage level conversion unit 111 can include two output terminals to output the high-level signal and the low-level signal, respectively. When the voltage value of the upper bridge control signal jumps, the outputs of the two output terminals of the high-voltage level conversion unit 111 also alternately change.

[0064] The upper bridge negative voltage level conversion unit 112 can output a first negative voltage domain signal according to the first high voltage domain signal, wherein the first negative voltage domain signal can include a high voltage level signal and a negative voltage level signal, the upper bridge negative voltage level conversion unit 112 can include at least one input terminal and two output terminals, one input terminal of the upper bridge negative voltage level conversion unit 112 is connected with one output terminal of the high voltage level conversion unit 111, when the output of the output terminal of the high voltage level conversion unit 111 changes, the outputs of the two output terminals of the upper bridge negative voltage level conversion unit 112 also change, thereby controlling the upper bridge gate drive unit 113 to switch the conduction state of the upper tube M1.

[0065] In one embodiment, the upper bridge gate drive unit 113 can be used to control the gate of the upper tube M1 to be connected with a first power supply (for example, a positive voltage power supply VDD) to turn on the upper tube M1, and to control the gate of the upper tube M1 to be connected with a second power supply (for example, a negative voltage power supply VEE) to turn off the upper tube M1. As shown in Figure 4 The upper bridge gate drive unit 113 can include a switch tube Ma and a switch tube Mb, the gates of the switch tube Ma and the switch tube Mb are connected with the upper bridge negative voltage level conversion unit 112 respectively, the drains of the switch tube Ma and the switch tube Mb are connected, the source of the switch tube Ma is connected with the positive voltage power supply VDD, and the source of the switch tube Mb is connected with the negative voltage power supply VEE, the upper bridge negative voltage level conversion unit 112 controls the gate of the upper tube M1 to be connected with the positive voltage power supply VDD or the negative voltage power supply VEE by controlling the switch tube Ma and the switch tube Mb to be turned on alternatively, thereby realizing the turn-on or turn-off of the upper tube M1.

[0066] In one embodiment, the upper bridge gate drive unit 113 can also be used to pull the gate voltage of the upper tube M1 from a first voltage to a second voltage and from the second voltage to a third voltage in sequence according to the first negative voltage domain signal to turn on the upper tube M1, or to pull the gate of the upper tube M1 from the third voltage to the second voltage and from the second voltage to the first voltage in sequence according to the first negative voltage domain signal to turn off the upper tube M1, wherein the first voltage is the gate voltage when the upper tube M1 is turned off, the third voltage is the gate voltage when the upper tube M1 is turned on, and the voltage value of the second voltage is within the voltage value range of the first voltage and the third voltage.

[0067] It can be understood that the upper tube M1 usually includes a blocking capacitance C, as shown in Figure 4As shown, one end of the switch Ma tube is connected to the positive power supply VDD, and one end of the switch tube Mb is connected to the negative power supply VEE. When the switch Ma tube is turned on, the upper tube M1 is pulled up to VDD, at which time the capacitor C is charged to VDD, and Vc=VDD. When the switch tube Mb is turned on, the upper tube M1 is pulled down to the negative voltage VEE, and then the capacitor C forms a loop to the negative power supply, and the capacitor C discharges to the negative power supply, and the discharge amount is from VDD to VEE, resulting in a large amount of power consumption of the negative power supply. Similarly, the capacitor C is VEE at this time, and when the Ma tube is turned on again, the upper tube M1 is pulled up to VDD, and then VDD forms a loop to the capacitor C, and VDD charges the capacitor C from VEE to VDD, consuming a large amount of positive power. Therefore, the embodiment of the present application can discharge the gate control end to ground (the second voltage) first, and then use the negative voltage to pull down the gate control end, thereby reducing the power consumption of the negative power supply. When the gate is opened, the gate control end is discharged from the negative voltage (the third voltage) to the ground (the second voltage) first, and then the gate control end is pulled up to VDD (the first voltage), thereby reducing the power consumption of the positive power supply.

[0068] The upper bridge gate drive unit 113 switches the state of the upper tube M1 according to the high voltage level signal and the negative voltage level signal output by the upper bridge negative voltage level conversion unit 112, and through the adoption of the three-stage gate drive, when discharging the gate control end (the gate of the upper tube M1), the gate control end is discharged to the second voltage first, and then the gate control end is pulled down by the negative voltage, thereby reducing the power consumption of the negative power supply; or the gate control end is discharged from the negative voltage to the second voltage first, and then the gate control end is pulled up to VDD, thereby reducing the power consumption of the positive power supply. The second voltage can be the ground voltage.

[0069] Therefore, the upper bridge gate drive unit 113 can also adopt the three-stage control gate voltage, adjust the size of each stage of the drive voltage, thereby being able to provide a buffer for the gate drive, control the voltage drop slope, avoid the gate voltage of the upper tube M1 directly jumping between the first voltage and the third voltage, and reduce the occurrence of the gate oscillation phenomenon. At the same time, the adoption of the three-stage control also reduces the large amount of power charge consumption, makes the discharge stable, and reduces the risk of the upper tube M1 being broken down.

[0070] In one embodiment, as Figure 5As shown, the high-voltage level conversion unit 111 can include a low-voltage transmission unit 1113, a latch unit 1111, and a high-voltage control unit 1112. The low-voltage transmission unit 1113 is connected with the dead zone control module 140, and is configured to output a low-voltage pulse signal according to the upper bridge control signal; the latch unit 1111 is connected with the upper bridge power supply module 100; the high-voltage control unit 1112 is connected with the low-voltage transmission unit 1113, the latch unit 1111, and the upper bridge power supply module 100 respectively, and the high-voltage control unit 1112 outputs a first high-voltage domain signal provided by the upper bridge power supply module 100 in response to the low-voltage pulse signal, so as to drive the latch unit 1111 to continuously output the first high-voltage domain signal.

[0071] In the formula, the upper bridge power supply module 100 can be a floating power supply. It can be understood that the low-voltage pulse signal can be a narrow pulse signal with low voltage amplitude and short pulse duration, and can be used as a transient excitation for triggering the high-voltage control unit 1112 to output the first high-voltage domain signal. After the high-voltage control unit 1112 responds to the low-voltage pulse signal, the first high-voltage domain signal is output to the latch unit 1111. The latch unit 1111 receives the first high-voltage domain signal output by the high-voltage control unit 1112 on one hand, and receives the first high-voltage domain signal directly output by the upper bridge power supply module 100 on the other hand. The latch unit 1111 can respond to the first high-voltage domain signal output by the high-voltage control unit 1112, and then continuously output the first high-voltage domain signal directly output by the upper bridge power supply module 100, so as to realize the latching of the first high-voltage domain signal. Since the requirement for excitation is low, the low-voltage pulse signal with short pulse duration can be used to realize the continuous output of the first high-voltage domain signal, thereby reducing the overall requirement for the circuit.

[0072] In the formula, the duration of the first high-voltage domain signal output by the high-voltage control unit 1112 is the same as the pulse duration of the low-voltage pulse signal. When the low-voltage pulse signal disappears, the high-voltage control unit 1112 also stops outputting the first high-voltage domain signal. The first high-voltage domain signal output by the high-voltage control unit 1112 can be used as an excitation signal for triggering the latch unit 1111 to latch. When the excitation signal disappears, the latch unit 1111 can still realize the latching of the first high-voltage domain signal due to the latching function of the latch unit 1111.

[0073] In addition, compared with the conventional level conversion mode which needs to set a pull-up resistor between the high-voltage power supply and the switching circuit, and obtains a high-voltage domain output through the voltage division of the pull-up resistor, the pull-up resistor continuously generates power consumption, thereby increasing the overall power consumption of the circuit. In the embodiment, the high-voltage level conversion unit 111 does not set an additional energy-consuming element when realizing the high-voltage domain output, and the overall power consumption of the circuit is low.

[0074] In one embodiment, the low-voltage pulse signal comprises the first pulse signal or the second pulse signal; the first high-voltage domain signal comprises the first level signal and the second level signal; the latch unit 1111 comprises a first electrode terminal Q1 and a second electrode terminal Q2; the high-voltage control unit 1112 comprises a first switch unit 1112a and a second switch unit 1112b, as shown in Figure 6 the first end a1 of the first switch unit 1112a is connected with the upper bridge power module 100, the second end a2 of the first switch unit 1112a is connected with the low-voltage transmission unit 1113, the third end a3 of the first switch unit 1112a is connected with the first electrode terminal Q1, the fourth end a4 of the first switch unit 1112a is connected with the second electrode terminal Q2, the first switch unit 1112a outputs the first level signal to the first electrode terminal Q1 and outputs the second level signal to the second electrode terminal Q2 in response to the first pulse signal; the latch unit 1111 is further configured to continuously output the first level signal through the first electrode terminal Q1 and continuously output the second level signal through the second electrode terminal Q2; the first end b1 of the second switch unit 1112b is connected with the upper bridge power module 100, the second end b2 of the second switch unit 1112b is connected with the low-voltage transmission unit 1113, the third end b3 of the second switch unit 1112b is connected with the second electrode terminal Q2, the fourth end b4 of the second switch unit 1112b is connected with the first electrode terminal Q1, the second switch unit 1112b outputs the first level signal to the second electrode terminal Q2 and outputs the second level signal to the first electrode terminal Q1 in response to the second pulse signal; the latch unit 1111 is further configured to continuously output the second level signal through the first electrode terminal Q1 and continuously output the first level signal through the second electrode terminal Q2.

[0075] It can be understood that when the low-voltage pulse signal comprises the first pulse signal, after the first electrode terminal Q1 of the latch unit 1111 receives the first level signal output by the first switch unit 1112a and the second electrode terminal Q2 receives the second level signal output by the first switch unit 1112a, on the one hand, the latch unit 1111 can directly output the two level signals through the two electrode terminals, on the other hand, the latch unit 1111 is simultaneously excited by the two level signals, and the latch unit 1111 latches the first level signal and the second level signal provided by the upper bridge power module 100, when the first switch unit 1112a stops outputting the two level signals, then the latch unit 1111 continuously outputs the first level signal provided by the upper bridge power module 100 through the first electrode terminal Q1, and continuously outputs the second level signal provided by the upper bridge power module 100 through the second electrode terminal Q2, so that only a short pulse is needed to trigger the continuous output of the signal.

[0076] Similarly, when the low-voltage pulse signal includes the second pulse signal, after the first electrode end Q1 of the latch unit 1111 receives the second level signal output by the second switch unit 1112b and the second electrode end Q2 receives the first level signal output by the second switch unit 1112b, the latch unit 1111 can continuously output the second level signal provided by the upper bridge power supply module 100 through the first electrode end Q1, and continuously output the first level signal provided by the upper bridge power supply module 100 through the second electrode end Q2. In this way, the output of the two output ends of the latch unit 1111 can be reversed by the above-mentioned method, and finally the conduction state of the upper tube M1 is switched. The input end of the upper bridge negative voltage level conversion unit 112 can be connected with one of the first electrode end Q1 and the second electrode end Q2, so as to convert the negative voltage level according to the first level signal or the second level signal.

[0077] The first level signal and the second level signal can be one of a high level signal and a low level signal, respectively; the first electrode end Q1 and the second electrode end Q2 of the latch unit 1111 can be one of a positive end and a negative end. For example, when the first level signal is low and the second level signal is high, the first electrode end Q1 outputs the first level signal as a negative end, and the second electrode end Q2 outputs the second level signal as a positive end.

[0078] In one embodiment, the upper bridge negative voltage level conversion unit 112 includes a first conversion unit 1121 and a second conversion unit 1122. As shown in Figure 7 The first conversion unit 1121 is connected with the high-voltage level conversion unit 111 and the upper bridge power supply module 100 respectively, and is used to output the second high-voltage domain signal provided by the upper bridge power supply module 100 according to the first high-voltage domain signal output by the high-voltage level conversion unit 111; the second conversion unit 1122 is connected with the first conversion unit 1121, the power supply end and the first negative voltage end U31 of the upper bridge power supply module 100 respectively, and is used to convert the second high-voltage domain signal into the first negative voltage domain signal, wherein the first negative voltage domain signal includes the voltage signal of the power supply end and the voltage signal of the first negative voltage end of the upper bridge power supply module 100.

[0079] It can be understood that the first conversion unit 1121 is connected with the upper bridge power supply module 100, the first high-voltage domain signal is used as a trigger signal to drive the first conversion unit 1121 to output the second high-voltage domain signal provided by the upper bridge power supply module 100, and the second conversion unit 1122 is connected with the power supply end and the first negative voltage end of the upper bridge power supply module 100 respectively, and after receiving the second high-voltage domain signal, the voltage signal of the power supply end and the voltage signal of the first negative voltage end of the upper bridge power supply module 100 are output as the first negative voltage domain signal, so as to realize the conversion from the second high-voltage domain signal to the first negative voltage domain signal, which is simple.

[0080] In one embodiment, the first conversion unit 1121 and the second conversion unit 1122 each include two sets of switch pairs. In the same conversion unit, the drain of the master control transistor of one set of switch pairs is connected to the gate of the slave control transistor and is shared with the drain of the slave control transistor of the other set of switch pairs, serving as the output terminal of the conversion unit. The source of the slave control transistor of the first conversion unit 1121 and the source of the master control transistor of the second conversion unit 1122 are respectively connected to the power supply terminal of the upper bridge power module 100. The source of the master control transistor of the first conversion unit 1121 is connected to the ground terminal of the upper bridge power module 100, and the source of the slave control transistor of the second conversion unit 1122 is connected to the first negative voltage terminal. The gate of the master control transistor of the first conversion unit 1121 is respectively connected to the high voltage level conversion unit 111, and the gate of the master control transistor of the second conversion unit 1122 is respectively connected to the output terminal of the first conversion unit 1121. The upper bridge negative voltage level conversion unit 112 further includes an upper bridge signal generation unit 1123 and an upper bridge control unit 1124. The upper bridge signal generation unit 1123 is connected to the high voltage level conversion unit 111 and is used to receive the first high voltage domain signal and generate an upper bridge pulse drive signal when the level of the first high voltage domain signal changes. The upper bridge control unit 1124 is connected to the gate of the upper bridge target slave control transistor of the upper bridge signal generation unit 1123 and the upper bridge target conversion unit respectively, and is used to disconnect the upper bridge target slave control transistor according to the upper bridge pulse drive signal. The upper bridge target conversion unit includes at least one of the first conversion unit 1121 and the second conversion unit 1122, and the upper bridge target slave control transistor is the slave control transistor of the upper bridge target conversion unit that is turned on at the previous conversion time.

[0081] Specifically, such as Figure 8 As shown, for the first conversion unit 1121, one set of switches includes a master control transistor NW11 and a slave control transistor PW11, and another set of switches includes a master control transistor NW21 and a slave control transistor PW21; for the second conversion unit 1122, one set of switches includes a master control transistor PW31 and a slave control transistor NW31, and another set of switches includes a master control transistor PW41 and a slave control transistor NW41. The master control transistors NW11, NW21, NW31, and NW41 are N-type MOSFETs, while the slave control transistors PW11, PW21, PW31, and PW41 are P-type MOSFETs. Furthermore, the slave control transistors NW31 and NW41 of the second conversion unit 1122 can each be an isolated field-effect transistor.

[0082] In the same conversion unit, the drain of the master control tube of a switch pair is connected with the gate of the slave control tube, and is commonly connected with the drain of the slave control tube of another switch pair to serve as the output end of the conversion unit, for example, the first conversion unit 1121 includes output ends a1 and a2, and the second conversion unit 1122 includes output ends b1 and b2. The source of the slave control tube of the first conversion unit 1121 and the source of the master control tube of the second conversion unit 1122 are respectively connected with the power supply end U11 of the upper bridge power supply module 100, the source of the master control tube of the first conversion unit 1121 is connected with the ground end U21 of the upper bridge power supply module 100, and the source of the slave control tube of the second conversion unit 1122 is connected with the first negative voltage end U31.

[0083] It can be understood that the upper bridge negative voltage level conversion unit 112 can further include an inverter N1, and the first conversion unit 1121 receives a first high voltage domain signal, which can be a first level signal or a second level signal of the received first high voltage domain signal, as shown in the figure, denoted by symbol s1. The upper bridge signal generation unit 1123 receives the first high voltage domain signal, which is also the received signal s1,

[0084] It can be understood that the upper bridge signal generation unit 1123 can be commonly connected with the gate of the master control tube NW11 to commonly receive the signal s1, and then generate an upper bridge pulse driving signal according to the level change of the signal s1, wherein the upper bridge pulse driving signal can be a narrow pulse signal to provide short-time driving, so that the upper bridge control unit 1124 disconnects the upper bridge target slave control tube at the moment when the signal s1 changes. Wherein, the upper bridge control unit 1124 can disconnect the upper bridge target slave control tube by providing a low level to the upper bridge target slave control tube.

[0085] For example, if the upper bridge target conversion unit is the first conversion unit 1121, when the signal s1 is low at the last conversion time and jumps to high at the current time, the upper bridge target slave is the slave PW21, the upper bridge control unit 1124 can be connected with the gate of the slave PW21, so that the slave PW21 is temporarily disconnected at the signal s1 jump time according to the upper bridge pulse driving signal, so that the master NW11 is more likely to pull down the gate of the slave PW11, so that the slave PW11 is turned on. In this way, when the signal s1 jumps from low to high, the conversion speed of the first conversion unit 1121 is improved. After the slave PW11 is turned on, the output end a1 is connected to the ground end of the upper bridge power module 100, and the output end a2 is connected to the power supply end of the upper bridge power module 100, thereby driving the second conversion unit 1122 to perform secondary conversion. When the signal s1 is high at the last conversion time and jumps to low at the current time, the upper bridge target slave is the slave PW11, the upper bridge control unit 1124 can be connected with the gate of the slave PW11, so that the slave PW11 is temporarily disconnected at the signal s1 jump time according to the upper bridge pulse driving signal, so that the master NW21 is more likely to pull down the gate of the slave NW21, so that the slave NW21 is turned on. After the slave NW21 is turned on, the output end a1 is connected to the power supply end of the upper bridge power module 100, and the output end a2 is connected to the ground end of the upper bridge power module 100, thereby driving the second conversion unit 1122 to perform secondary conversion. In this way, when the signal s1 jumps from high to low, the conversion speed of the first conversion unit 1121 is improved. Therefore, the upper bridge target slave can be at least one of the slave PW11 and the slave PW21, wherein, Figure 8 The upper bridge target slave is simultaneously included in the slave PW11 and the slave PW21, in which case the conversion speed of the first conversion unit 1121 can be improved in any jump case.

[0086] Similarly, if the upper bridge target conversion unit is the second conversion unit 1122, when the signal s1 is low at the last conversion time and jumps to high at the current time, the upper bridge target slave is the slave NW41, the upper bridge control unit 1124 can be connected with the gate of the slave NW41, Figure 8the slave control tube NW41, so that the master control tube PW31 is more likely to pull up the gate of the slave control tube NW31, thereby turning on the slave control tube NW31. After the slave control tube NW41 is turned on, the output end bl is connected to the power supply end of the upper bridge power supply module 100, and the output end b2 is connected to the first negative voltage end, so as to realize the improvement of the conversion speed of the second conversion unit 1122 when the signal sl jumps from low level to high level. When the signal sl is high level at the previous conversion time and jumps to low level at the current time, the upper bridge target slave control tube is the slave control tube NW31, and the upper bridge control unit 1124 can be connected to the gate of the slave control tube NW31. Figure 8 the slave control tube NW41, so that the master control tube PW31 is more likely to pull up the gate of the slave control tube NW31, thereby turning on the slave control tube NW31. After the slave control tube NW41 is turned on, the output end bl is connected to the power supply end of the upper bridge power supply module 100, and the output end b2 is connected to the first negative voltage end, so as to realize the improvement of the conversion speed of the second conversion unit 1122 when the signal sl jumps from low level to high level. When the signal sl is high level at the previous conversion time and jumps to low level at the current time, the upper bridge target slave control tube is the slave control tube NW31, and the upper bridge control unit 1124 can be connected to the gate of the slave control tube NW31.

[0087] Since the drain of the master control tube of the switch pair to be turned on in the same conversion unit is connected to the gate of the slave control tube of the switch pair to be turned on and the drain of the slave control tube of another switch pair at the same time when the signal sl changes, the slave control tube is still in the on state when the signal sl changes, thereby affecting the driving of the master control tube on the slave control tube in the switch to be turned on. By using the upper bridge signal generation unit 1123 to generate a narrow pulse signal when the signal sl changes, and then using the upper bridge control unit 1124 to accelerate the disconnection of the slave control tube of the upper bridge target conversion unit turned on at the previous conversion time according to the narrow pulse signal, the driving ability of the master control tube on the slave control tube in the switch to be turned on can be improved, the turn-on speed of the switch to be turned on can be accelerated, and finally the conversion speed of the upper bridge negative voltage level conversion circuit can be improved.

[0088] In one embodiment, as Figure 9As shown, the upper bridge gate driving unit 113 includes a first control unit 1131, a second control unit 1132 and a third control unit 1133; the first control unit 1131 is configured to stop outputting the first voltage V1 according to the first level signal of the first negative voltage domain signal, and output a first feedback signal to the second control unit 1132; the second control unit 1132 is configured to output the second voltage V2 according to the first feedback signal; the second control unit 1132 is further configured to stop outputting the second voltage V2 after outputting the second voltage and before the first level signal of the first negative voltage domain signal jumps, and output a second feedback signal to the third control unit 1133; the third control unit 1133 is configured to output the third voltage V3 according to the second feedback signal.

[0089] It can be understood that the first control unit 1131 is connected with the upper bridge negative voltage level conversion unit 112 to receive the first negative voltage domain signal. The first feedback signal is used to represent the voltage output result of the first control unit 1131. The voltage output result is that the first control unit 1131 stops outputting the first level or the first control unit 1131 outputs the first level.

[0090] The second feedback signal is used to represent the voltage output result of the second control unit 1132. The voltage output result is that the second control unit 1132 stops outputting the first level or the second control unit 1132 outputs the second level.

[0091] Specifically, the first control unit 1131 is configured to stop outputting the first voltage according to the first level signal of the first negative voltage domain signal, and output a first feedback signal to the second control unit 1132. The second control unit 1132 is configured to output the second voltage according to the level representing the stop outputting the first voltage in the first feedback signal.

[0092] The second control unit 1132 is configured to stop outputting the second voltage after outputting the second voltage and before the first level signal of the first negative voltage domain signal jumps to the second level, and output a second feedback signal to the third control unit 1133. The second control unit 1132 can stop outputting the second voltage based on the input enable signal. The enable signal can be a delay signal output by the delay unit from the first level signal of the first negative voltage domain signal, or can be an enable signal directly input to the second control unit 1132, so as to stop outputting the second voltage after outputting the second voltage and before the first level signal of the first negative voltage domain signal jumps. The third control unit 1133 is configured to output the third voltage according to the level representing the stop outputting the second voltage in the second feedback signal.

[0093] For example, after the first control unit 1131 outputs a first voltage (e.g., VDD), Vc = VDD; after the second control unit 1132 outputs a second voltage (e.g., 0V), capacitor C discharges from VDD to 0V, at which point Vc = 0V; after the third control unit 1133 outputs a third voltage (e.g., VEE), capacitor C discharges from 0V to the negative voltage VEE, at which point Vc = VEE. This is illustrated using an example where VDD is 6V and VEE is -2V. Figure 4 In the technical solution described above, the amount of negative power consumed by capacitor C is C*(6-(-2))=8C. However, using the gate drive circuit in this embodiment, the amount of negative power consumed by capacitor C is only 2C, which is consumed when discharging from 0V to negative voltage VEE, reducing the negative power consumption by 6C.

[0094] Similarly, after the third control unit 1133 outputs the third voltage, Vc = VEE; the second control unit 1132 outputs the second voltage (e.g., 0V), and capacitor C discharges from VEE to 0V, at which point Vc = 0V; after the first control unit 1131 outputs the first voltage (e.g., VDD), capacitor C charges from 0V to VDD, at which point Vc = VDD. Again, this is illustrated using an example of VDD being 6V and VEE being -2V. Figure 4 In the technical solution described above, the positive power consumed by capacitor C is C*(6-(-2))=8C. However, using the gate drive circuit in this embodiment, the positive power consumed by capacitor C is only the 6C consumed during charging from 0V to VDD, reducing the positive power consumption by 2C.

[0095] Through the above three-stage control, the magnitude of the driving voltage of each stage is adjusted respectively, and the second control unit 1132 provides a buffer for the gate drive, controls the voltage jump slope, avoids jumping directly from the first voltage to the third voltage, and reduces the occurrence of gate oscillation.

[0096] In one embodiment, the third control unit 1133 is further configured to stop outputting the third voltage V3 according to the second level signal of the first negative voltage domain signal, and output a third feedback signal to the second control unit 1132; the second control unit 1132 is further configured to output the second voltage V2 according to the third feedback signal; the second control unit 1132 is further configured to stop outputting the second voltage V2 after outputting the second voltage and before the second level signal of the first negative voltage domain signal changes, and output a second feedback signal to the first control unit 1131; the first control unit 1131 is further configured to output the first voltage V1 according to the second feedback signal.

[0097] The third feedback signal can be used to characterize the cessation of outputting the third voltage.

[0098] Through the above three-stage control, the driving voltage of each stage is adjusted respectively, and the second control unit 1132 provides a buffer for the gate drive, controls the voltage jump slope, avoids direct jump from the third voltage to the first voltage, and reduces the occurrence of gate oscillation phenomenon.

[0099] In one embodiment, the dead-time control module 140 is further configured to generate a lower bridge control signal according to the instruction signal, and the lower bridge drive module 120 includes a lower bridge negative voltage level conversion unit 121 and a lower bridge gate drive unit 122. As shown in Figure 10 the lower bridge negative voltage level conversion unit 121 is connected with the dead-time control module 140 and configured to output a second negative voltage domain signal according to the lower bridge control signal; and the lower bridge gate drive unit 122 is connected with the lower bridge negative voltage level conversion unit 121 and configured to turn on or turn off the lower transistor M2 according to the second negative voltage domain signal.

[0100] wherein,

[0101] It can be understood that the source of the lower transistor M2 is connected with the negative power supply VEE, and the lower bridge control signal is usually several volts, and the voltage value is sufficient to control the driving of the lower transistor M2, so that the lower bridge control signal can be directly used to drive the lower bridge negative voltage level conversion unit 121 to obtain the second negative voltage domain signal, and then drive the lower bridge gate drive unit 122 to change the gate voltage of the lower transistor M2. The second negative voltage domain signal can include a high voltage level signal and a negative voltage level signal, and the lower bridge negative voltage level conversion unit 121 can include an input end and two output ends. The input end of the lower bridge negative voltage level conversion unit 121 is connected with the dead-time control module 140, and when the output of the dead-time control module 140 changes, the outputs of the two output ends of the lower bridge negative voltage level conversion unit 121 also change, thereby controlling the lower bridge gate drive unit 122 to switch the conduction state of the lower transistor M2.

[0102] Similarly, in one embodiment, the lower bridge gate drive unit 122 can be configured to control the gate of the lower transistor M2 to be connected with the third power supply to turn on the lower transistor M2, and control the gate of the lower transistor M2 to be connected with the fourth power supply to turn off the lower transistor M2.

[0103] In another embodiment, considering that the lower tube M2 includes a blocking capacitance, the lower bridge gate drive unit 122 can also be used to pull the gate voltage of the lower tube M2 from the fourth voltage to the fifth voltage, and then from the fifth voltage to the sixth voltage according to the second negative voltage domain signal in sequence, so as to turn on the lower tube M2; or pull the gate voltage of the lower tube M2 from the sixth voltage to the fifth voltage, and then from the fifth voltage to the fourth voltage according to the second negative voltage domain signal in sequence, so as to turn off the lower tube M2; wherein the fourth voltage is the gate voltage when the lower tube M2 is turned off, the sixth voltage is the gate voltage when the lower tube M2 is turned on, and the voltage value of the fifth voltage is within the voltage value range of the fourth voltage and the sixth voltage. In this way, when switching the on state of the lower tube M2, by adopting a three-stage gate drive, when discharging the gate control end (the gate of the lower tube M2) of the lower bridge, the gate control end is first discharged to the fifth voltage, and then the gate control end is pulled down using negative voltage, reducing the power consumption of the negative power supply; or the gate control end is first discharged from the negative voltage to the fifth voltage, and then the gate control end is pulled up to VDD, reducing the power consumption of the positive power supply. The fifth voltage can be a ground voltage.

[0104] Therefore, by adopting the upper bridge gate drive unit 113 to realize three-stage control of the gate voltage, the size of each stage driving voltage can be adjusted, so as to provide buffer for gate drive, control the voltage drop slope, avoid the gate voltage of the upper tube M1 directly jumping between the fourth voltage and the sixth voltage, and reduce the occurrence of gate oscillation phenomenon. At the same time, by adopting three-stage control, the power charge consumption is also reduced, the discharge is stable, and the risk of breakdown of the lower tube M2 is reduced. In addition, the traditional gate negative voltage drive scheme adopts a series gate capacitance mode, which uses the characteristic that the gate capacitance voltage cannot be suddenly changed to realize negative voltage off, but the voltage control precision of the traditional scheme is poor, and is related to the gate rise and fall time, which is seriously affected by the consistency of components. The lower bridge gate drive unit 122 in the embodiment can provide an accurate negative off voltage (fourth voltage) for the gate.

[0105] In one embodiment, the lower bridge negative voltage level conversion unit 121 includes a third conversion unit 1211 and a fourth conversion unit 1212. The third conversion unit 1211 is connected with the dead zone control module 140 and the lower bridge power supply module 200 respectively, and is used to output the positive voltage domain signal provided by the lower bridge power supply module 200 according to the lower bridge control signal; the fourth conversion unit 1212 is connected with the third conversion unit 1211, the power supply end of the lower bridge power supply module 200 and the second negative voltage end U32 respectively, and is used to convert the positive voltage domain signal into the second negative voltage domain signal, wherein the second negative voltage domain signal includes the voltage signal of the power supply end of the lower bridge power supply module 200 and the voltage signal of the second negative voltage end.

[0106] It can be understood that the third conversion unit 1211 is connected with the lower bridge power module 200, and the lower bridge control signal is used as a trigger signal to drive the third conversion unit 1211 to output the positive voltage domain signal provided by the lower bridge power module 200. The fifth conversion unit is connected with the power supply end and the second negative voltage end of the lower bridge power module 200 respectively. After receiving the positive voltage domain signal, the voltage signal of the power supply end and the voltage signal of the second negative voltage end of the lower bridge power module 200 are outputted as the second negative voltage domain signal, so as to realize the conversion of the lower bridge control signal to the second negative voltage domain signal, and the method is simple.

[0107] In one embodiment, the third conversion unit 1211 and the fourth conversion unit 1212 each include two groups of switch pairs. In the same conversion unit, the drain of the master control tube of one group of switch pairs is connected with the gate of the slave control tube, and the drain of the slave control tube of another group of switch pairs is commonly connected, so as to serve as the output end of the conversion unit. The source of the slave control tube of the third conversion unit 1211 and the source of the master control tube of the fourth conversion unit 1212 are connected with the power supply end of the lower bridge power module 200 respectively. The source of the master control tube of the third conversion unit 1211 is connected with the ground end of the lower bridge power module 200. The source of the slave control tube of the fourth conversion unit 1212 is connected with the second negative voltage end. The gate of the master control tube of the third conversion unit 1211 is connected with the dead zone control module 140 respectively. The gate of the master control tube of the fourth conversion unit 1212 is connected with the output end of the third conversion unit 1211 respectively. The lower bridge negative voltage level conversion unit 121 further includes a lower bridge signal generation unit 1213 and a lower bridge control unit 1214. The lower bridge signal generation unit 1213 is connected with the dead zone control module 140, used for receiving the lower bridge control signal and generating a lower bridge pulse driving signal when the level of the lower bridge control signal changes. The lower bridge control unit 1214 is connected with the lower bridge signal generation unit 1213 and the gate of the lower bridge target slave control tube of the lower bridge target conversion unit respectively, used for disconnecting the lower bridge target slave control tube according to the lower bridge pulse driving signal. The lower bridge target conversion unit includes at least one of the third conversion unit 1211 and the fourth conversion unit 1212, and the target slave control tube is the slave control tube of the lower bridge target conversion unit which is turned on at the last conversion time.

[0108] Specifically, as Figure 12As shown, for the third conversion unit 1211, one set of switches includes a master control transistor NW12 and a slave control transistor PW12, and another set of switches includes a master control transistor NW22 and a slave control transistor PW22; for the fourth conversion unit 1212, one set of switches includes a master control transistor PW32 and a slave control transistor NW32, and another set of switches includes a master control transistor PW42 and a slave control transistor NW42. The master control transistors NW12, NW22, NW32, and NW42 are N-type MOSFETs, while the slave control transistors PW12, PW22, PW32, and PW42 are P-type MOSFETs. Furthermore, the slave control transistors NW32 and NW42 of the second conversion unit 1122 can each be isolated field-effect transistors.

[0109] In each conversion unit, the drain of the master control transistor of one pair of switches is connected to the gate of the slave control transistor, and is also connected to the drain of the slave control transistor of another pair of switches, serving as the output terminal of the conversion unit. For example, the first conversion unit 1121 includes output terminals a3 and a4, and the fourth conversion unit 1212 includes output terminals b3 and b4. The source of the slave control transistor of the third conversion unit 1211 and the source of the master control transistor of the fourth conversion unit 1212 are respectively connected to the power supply terminal U11 of the lower bridge power module 200. The source of the master control transistor of the third conversion unit 1211 is connected to the ground terminal U22 of the lower bridge power module 200, and the source of the slave control transistor of the fourth conversion unit 1212 is connected to the second negative voltage terminal U32.

[0110] It is understood that the lower bridge negative voltage level conversion unit 121 may also include an inverter N2, and the third conversion unit 1211 receives the lower bridge control signal, denoted by the symbol s2. The lower bridge signal generation unit 1213 receives the lower bridge control signal, which is also the received signal s1.

[0111] It is understood that the lower-bridge signal generation unit 1213 can be connected to the gate of the main control transistor NW12 to jointly receive signal s2, and then generate a lower-bridge pulse drive signal according to the level change of signal s2. The lower-bridge pulse drive signal can be a narrow pulse signal to provide short-time drive, so that the lower-bridge control unit 1214 disconnects the lower-bridge target slave controller when signal s2 changes. The lower-bridge control unit 1214 can disconnect the lower-bridge target slave controller by providing a low level to the lower-bridge target slave controller.

[0112] For example, if the target conversion unit of the lower bridge is the third conversion unit 1211, when signal s2 is low at the previous conversion time and jumps to high at the current time, the target slave controller of the lower bridge is the slave controller PW22. The lower bridge control unit 1214 can be connected to the gate of the slave controller PW22, so that the slave controller PW22 can be briefly disconnected at the time of the signal s2 transition according to the lower bridge pulse drive signal, making it easier for the master controller NW12 to pull low the gate of the slave controller PW12, thereby turning on the slave controller PW12. In this way, when signal s2 jumps from low to high, the conversion speed of the third conversion unit 1211 is improved. After the slave controller PW12 is turned on, the output terminal a3 is connected to the ground terminal of the lower bridge power module 200, and the output terminal a4 is connected to the power terminal of the lower bridge power module 200, thereby driving the fourth conversion unit 1212 to perform secondary conversion. When signal s2 was high at the previous transition time and transitions to low at the current time, the target slave controller of the lower bridge is slave controller PW12. The lower bridge control unit 1214 can be connected to the gate of slave controller PW12, so that slave controller PW12 can be briefly disconnected at the transition time of signal s2 according to the lower bridge pulse drive signal, making it easier for master controller NW22 to pull low the gate of slave controller PW22, thereby turning on slave controller PW22. After slave controller PW22 is turned on, output terminal a3 is connected to the power supply terminal of lower bridge power module 200, and output terminal a4 is connected to the ground terminal of lower bridge power module 200, thereby driving the fourth conversion unit 1212 to perform secondary conversion. In this way, when signal s1 transitions from high level to low level, the conversion speed of the third conversion unit 1211 is improved. Therefore, the target slave controller of the lower bridge can be at least one of slave controller PW12 and slave controller PW22, wherein... Figure 12 An example is shown where the lower bridge target slave controller includes both slave controller PW12 and slave controller PW22. In this case, the conversion speed of the third conversion unit 1211 can be improved in any transition case of signal s2.

[0113] Similarly, if the lower bridge target conversion unit is the fourth conversion unit 1212, when signal s2 is low at the previous conversion time and jumps to high at the current time, the lower bridge target slave controller is slave controller NW42, and the lower bridge control unit 1214 can be connected to the gate of slave controller NW42. Figure 12(Not shown in the diagram), thus, according to the lower bridge pulse drive signal, the slave controller NW42 can be briefly disconnected at the transition moment of signal s2, making it easier for the master controller PW32 to pull high the gate of the slave controller NW32, thereby turning on the slave controller NW32. After the slave controller NW32 is turned on, the output terminal b3 is connected to the power supply terminal of the lower bridge power module 200, and the output terminal b4 is connected to the second negative voltage terminal U32. In this way, when the signal s2 transitions from low level to high level, the conversion speed of the fourth conversion unit 1212 is improved. When the signal s2 was high level at the previous transition moment and transitions to low level at the current moment, the target slave controller of the lower bridge is the slave controller NW32, and the lower bridge control unit 1214 can be connected to the gate of the slave controller NW32 ( Figure 12 (Not shown in the diagram), thus, according to the lower bridge pulse drive signal, the slave control transistor NW32 can be briefly disconnected at the moment of signal s2 transition, making it easier for the master control transistor PW42 to pull the gate of the slave control transistor NW42 high, thereby turning on the slave control transistor NW42. After the slave control transistor NW42 is turned on, the output terminal b3 is connected to the second negative voltage terminal, and the output terminal b4 is connected to the power supply terminal of the lower bridge power module 200. In this way, when the signal s2 transitions from a high level to a low level, the conversion speed of the fourth conversion unit 1212 is increased. Therefore, the target slave control transistor of the lower bridge can be at least one of the slave control transistors NW32 and NW42. When the target slave control transistor of the lower bridge includes both slave control transistors NW32 and NW42, in this case, the conversion speed of the fourth conversion unit 1212 can be increased in any transition case of signal s2.

[0114] Because when signal s2 changes, the drain of the master control transistor of the switch pair to be turned on in the same conversion unit is connected to the gate of its slave control transistor, and is also connected to the drain of the slave control transistor of another switch pair. The slave control transistor is still in the on state when signal s2 changes, which will affect the driving of the slave control transistor by the master control transistor in the switch to be turned on. By using the lower bridge signal generation unit 1213 to generate a narrow pulse signal when the level of signal s2 changes, the lower bridge control unit 1214 can accelerate the disconnection of the slave control transistor of the lower bridge target conversion unit that was turned on at the previous conversion time according to the narrow pulse signal, thereby improving the driving capability of the master control transistor in the switch to be turned on to the slave control transistor, speeding up the turn-on speed of the switch to be turned on, and ultimately improving the conversion speed of the lower bridge negative voltage level conversion circuit.

[0115] In one embodiment, the lower bridge gate drive unit 122 includes a fourth control unit 1221, a fifth control unit 1222, and a sixth control unit 1223, such as Figure 13As shown; the fourth control unit 1221 is used to stop outputting the fourth voltage V4 according to the first level signal of the second negative voltage domain signal, and output a fourth feedback signal to the fifth control unit 1222; the fifth control unit 1222 is used to output the fifth voltage V5 according to the fourth feedback signal; the fifth control unit 1222 is also used to stop outputting the fifth voltage V5 after outputting the fifth voltage V5 and before the first level signal of the second negative voltage domain signal changes, and output a fifth feedback signal to the sixth control unit 1223; the sixth control unit 1223 is used to output the sixth voltage V6 according to the fifth feedback signal.

[0116] It is understood that the fourth control unit 1221 is connected to the lower bridge negative voltage level conversion unit 121 to receive the second negative voltage domain signal. The fourth feedback signal is used to characterize the voltage output result of the fourth control unit 1221. The voltage output result is either the fourth control unit 1221 stops outputting the first level or the fourth control unit 1221 outputs the first level.

[0117] The fifth feedback signal is used to characterize the voltage output result of the fifth control unit 1222. The voltage output result is either the fifth control unit 1222 stopping the output of the first level or the fifth control unit 1222 outputting the second level.

[0118] Specifically, the fourth control unit 1221 is used to stop outputting the fourth voltage according to the first level signal of the second negative voltage domain signal, and output a fourth feedback signal to the fifth control unit 1222. The fifth control unit 1222 is used to output the fifth voltage according to the level in the fourth feedback signal that represents the stop of outputting the fourth voltage.

[0119] The fifth control unit 1222 is used to stop outputting the fifth voltage after outputting the fifth voltage and before the first level signal of the second negative voltage domain signal transitions to the second level, and to output a fifth feedback signal to the sixth control unit 1223. The fifth control unit 1222 can stop outputting the fifth voltage based on an input enable signal. This enable signal can be a delayed signal output by a delay unit from the first level signal of the second negative voltage domain signal, or it can be an enable signal directly input to the fifth control unit 1222, thereby stopping the output of the fifth voltage after outputting the fifth voltage and before the first level signal of the second negative voltage domain signal transitions. The sixth control unit 1223 is used to output a sixth voltage according to the level in the fifth feedback signal that indicates the cessation of outputting the fifth voltage.

[0120] Through the above three-stage control, the magnitude of the driving voltage of each stage is adjusted respectively, and the fifth control unit 1222 provides a buffer for the gate drive, controls the voltage jump slope, avoids jumping directly from the fourth voltage to the sixth voltage, and reduces the occurrence of gate oscillation.

[0121] In one embodiment, the sixth control unit 1223 is further configured to stop outputting the sixth voltage according to the second level signal of the second negative voltage domain signal, and output a sixth feedback signal to the fifth control unit 1222; the fifth control unit 1222 is further configured to output the fifth voltage according to the sixth feedback signal; the fifth control unit 1222 is further configured to stop outputting the fifth voltage after outputting the fifth voltage and before the second level signal of the second negative voltage domain signal changes, and output a fifth feedback signal to the fourth control unit 1221; the fourth control unit 1221 is further configured to output the fourth voltage according to the fifth feedback signal.

[0122] The sixth feedback signal can be used to characterize the cessation of outputting the sixth voltage.

[0123] Through the above three-stage control, the magnitude of the driving voltage of each stage is adjusted respectively, and the fifth control unit 1222 provides a buffer for the gate drive, controls the voltage jump slope, avoids jumping directly from the sixth voltage to the fourth voltage, and reduces the occurrence of gate oscillation.

[0124] In one embodiment, the gate driver integrated circuit further includes a gate protection module 160, such as... Figure 14 As shown, the gate protection module 160 is connected to the gate of the lower transistor M2 and the upper bridge drive module 110 respectively, and is used to control the upper bridge drive module 110 to disconnect the upper transistor M1 if the lower transistor M2 is in the on state.

[0125] Specifically, the gate protection module 160 may include an AND gate 161 and an inverter 162. The lower bridge drive module 120 and the gate of the lower transistor M2 are connected to the input of the inverter. The input of the inverter is connected to the first input of a logic gate such as the AND gate 161. The second input of the AND gate is connected to the dead-time control module 140. The output of the AND gate is connected to the upper bridge drive module 110.

[0126] In this embodiment, by setting the gate protection module 160, the driving status of the lower tube M2 can be fed back to the upper bridge drive module 110. Based on the reserved dead time, it further prevents the upper tube M1 and the lower tube M2 from being turned on at the same time, thereby improving the stability and safety of the drive device.

[0127] In one embodiment, the dead-time control module includes a dead-time resistor; the dead-time control module 140 is also used to control the upper bridge drive module 110 to delay the dead time to turn on the upper transistor M1, and to control the lower bridge drive module 120 to delay the dead time to turn on the lower transistor M2, wherein the dead time corresponds one-to-one with the resistance value of the dead-time resistor.

[0128] The value of the dead-time resistor affects the timing at which the dead-time control module 140 controls the upper bridge drive module 110 to turn on the upper transistor M1, and the timing at which the lower bridge drive module 120 controls the lower transistor M2 to turn on. By adjusting the value of the dead-time resistor, the dead-time control module 140 can adjust the duration for which the upper bridge drive module 110 delays the turn-on of the upper transistor M1, and the duration for which the lower bridge drive module 120 delays the turn-on of the lower transistor M2.

[0129] Specifically, the command signal is typically used to instruct one of the upper transistor M1 and the lower transistor M2 to be turned on while the other is turned off. When the dead-time control module 140 does not have a dead-time resistor, its dead-time setting function is invalid, but it can still execute actions according to the command signal to turn on one of the upper transistors M1 and M2. When the dead-time resistor is connected, the protection logic for the upper transistors M1 and M2 in the dead-time control module 140 becomes effective. At this time, after determining the transistor to be turned on according to the command signal, the dead-time control module 140 delays the dead-time period before turning on the transistor, thereby preventing the upper transistor M1 and the lower transistor M2 from being directly connected due to the transistor not being turned off in time.

[0130] In one embodiment, the dead-time control module 140 may include a dead-time resistor. The dead-time control module 140 is also configured to control the upper bridge drive module 110 to disconnect the upper MOSFET M1 and control the lower bridge drive module 120 to disconnect the lower MOSFET M2 if the instruction signal indicates that the upper MOSFET M1 and the lower MOSFET M2 are simultaneously turned on.

[0131] It is understandable that when the dead-time control module 140 is equipped with a dead-time resistor, the logic check function of the dead-time control module 140 is effective. If the command signal indicates that the upper transistor M1 and the lower transistor M2 are simultaneously turned on, the dead-time control module 140 can simultaneously turn off the upper transistor M1 and the lower transistor M2 by controlling the upper bridge drive module 110 and the lower bridge drive module 120 respectively. Therefore, by connecting the dead-time resistor, the dead-time control module 140 can avoid a situation where the upper transistor M1 and the lower transistor M2 are simultaneously turned on due to a logic error in the command signal, thus preventing a shoot-through of the upper transistor M1 and the lower transistor M2.

[0132] In one embodiment, the isolation transmission module 130 includes a modulation and transmission unit, a high-voltage isolation capacitor, and a signal demodulation unit. The modulation and transmission unit is used to receive a command signal and modulate it to obtain a high-frequency signal according to the command signal. The high-voltage isolation capacitor is connected to the modulation and transmission unit and is used to couple the high-frequency signal to the signal demodulation unit. The signal demodulation unit is connected to the high-voltage isolation capacitor and the dead-time control module 140 respectively and is used to demodulate the high-frequency signal to obtain the command signal and transmit it to the dead-time control module 140.

[0133] It is understood that the modulation and transmission unit modulates the command signal into a high-frequency signal. High-voltage isolation capacitors are used to achieve electrical isolation between the modulation and transmission unit and the demodulation unit, coupling and transmitting the modulated command signal. The demodulation unit demodulates the modulated command signal to restore the original command signal. The modulation and transmission unit (located on the TX chip) and the demodulation unit (located on the RX chip) are on two separate wafers. The modulation and transmission unit modulates the command signal into a high-frequency OOK modulated signal. The high-voltage capacitors can be integrated on the TX or RX chip, or they can be integrated off-chip. After coupling and transmission, the demodulation unit restores the modulated signal.

[0134] The modulation and transmission unit may specifically include a radio frequency oscillator and an amplitude modulator, which can modulate the desired high-frequency signal according to the command signal under the control of external input.

[0135] This invention also provides a gate driver integrated circuit applied to a half-bridge circuit. The gate driver integrated circuit includes an upper bridge driver module 110, a lower bridge driver module 120, an isolation transmission module 130, an over-temperature and over-current protection module 150, a dead-time control module 140, and a gate protection module 160. The upper bridge driver module 110 is connected to the gate of the upper transistor M1 of the half-bridge circuit, and the lower bridge driver module 120 is connected to the gate of the lower transistor M2 of the half-bridge circuit. The isolation transmission module 130 is used to receive and output command signals. The dead-time control module 140 is connected to the isolation transmission module 130, the upper bridge driver module 110, and the lower bridge driver module 120, and is used to control the upper bridge driver module to turn on or off the upper transistor M1, and to control the lower bridge driver module 120 to turn on or off the lower transistor M2, according to the command signals. The upper transistor M1 and the lower transistor M2 are not simultaneously turned on. The over-temperature and over-current protection module 150 is connected to the dead-time control module 140. If at least one of the following is detected: the temperature of the gate driver integrated circuit exceeds a temperature threshold, or the current flowing through the lower transistor M2 exceeds a current threshold, the dead-time control module 140 is instructed to control the upper bridge driver module 110 to disconnect the upper transistor M1, and the lower bridge driver module 120 is instructed to disconnect the lower transistor M2. The gate protection module 160 is connected to the gate of the lower transistor M2 and the upper bridge driver module 110, respectively. If the lower transistor M2 is in the on state, the upper bridge driver module 110 is instructed to disconnect the upper transistor M1.

[0136] Specifically, the dead-time control module 140 is also used to generate an upper bridge control signal according to the command signal. The upper bridge drive module 110 includes a high-voltage level conversion unit 111, an upper bridge negative voltage level conversion unit 112, and an upper bridge gate drive unit 113, such as... Figure 3As shown. The high-voltage level conversion unit 111 is connected to the dead-time control module 140 and is used to output a first high-voltage domain signal according to the upper bridge control signal; the upper bridge negative voltage level conversion unit 112 is connected to the high-voltage level conversion unit 111 and is used to output a first negative voltage domain signal according to the first high-voltage domain signal; the upper bridge gate drive unit 113 is connected to the upper bridge negative voltage level conversion unit 112 and is used to turn the upper tube M1 on or off according to the first negative voltage domain signal.

[0137] The upper bridge gate drive unit 113 can also be used to: sequentially pull the gate voltage of the upper transistor M1 from the first voltage to the second voltage and from the second voltage to the third voltage according to the first negative voltage domain signal, so as to turn on the upper transistor M1; or sequentially pull the gate of the upper transistor M1 from the third voltage to the second voltage and from the second voltage to the first voltage according to the first negative voltage domain signal, so as to turn off the upper transistor M1; wherein the first voltage is the gate voltage when the upper transistor M1 is turned off, the third voltage is the gate voltage when the upper transistor M1 is turned on, and the voltage value of the second voltage is within the voltage value range of the first voltage and the third voltage.

[0138] The high-voltage level conversion unit 111 includes a low-voltage transmission unit 1113, a latch unit 1111, and a high-voltage control unit 1112. The low-voltage transmission unit 1113 is connected to the dead-time control module 140 and is used to output a low-voltage pulse signal according to the upper bridge control signal. The latch unit 1111 is connected to the upper bridge power supply module 100. The high-voltage control unit 1112 is connected to the low-voltage transmission unit 1113, the latch unit 1111, and the upper bridge power supply module 100, respectively. The high-voltage control unit 1112 responds to the low-voltage pulse signal and outputs a first high-voltage domain signal provided by the upper bridge power supply module 100 to drive the latch unit 1111 to continuously output the first high-voltage domain signal.

[0139] Specifically, the low-voltage pulse signal includes a first pulse signal or a second pulse signal; the first high-voltage domain signal includes a first level signal and a second level signal; the latch unit 1111 includes a first terminal Q1 and a second terminal Q2; the high-voltage control unit 1112 includes a first switching unit 1112a and a second switching unit 1112b, such as... Figure 6As shown, the first terminal a1 of the first switching unit 1112a is connected to the upper bridge power module 100, the second terminal a2 of the first switching unit 1112a is connected to the low-voltage transmission unit 1113, the third terminal a3 of the first switching unit 1112a is connected to the first terminal Q1, and the fourth terminal a4 of the first switching unit 1112a is connected to the second terminal Q2. The first switching unit 1112a responds to a first pulse signal by outputting a first-level signal to the first terminal Q1 and a second-level signal to the second terminal Q2. The latching unit 1111 is also used to continuously output the first-level signal through the first terminal Q1 and continuously output the second-level signal through the second terminal Q2. The first terminal b1 of the second switching unit 1112b is connected to the upper bridge power module 100, the second terminal b2 of the second switching unit 1112b is connected to the low-voltage transmission unit 1113, the third terminal b3 of the second switching unit 1112b is connected to the second electrode Q2, and the fourth terminal b4 of the second switching unit 1112b is connected to the first electrode Q1. The second switching unit 1112b responds to the second pulse signal by outputting a first level signal to the second electrode Q2 and outputting a second level signal to the first electrode Q1. The latching unit 1111 is also used to continuously output a second level signal through the first electrode Q1 and continuously output a first level signal through the second electrode Q2.

[0140] The upper bridge negative voltage level conversion unit 112 includes a first conversion unit 1121 and a second conversion unit 1122. For example... Figure 7 As shown, the first conversion unit 1121 is connected to the high-voltage level conversion unit 111 and the upper bridge power module 100 respectively, and is used to output the second high-voltage domain signal provided by the upper bridge power module 100 according to the first high-voltage domain signal output by the high-voltage level conversion unit 111; the second conversion unit 1122 is connected to the first conversion unit 1121, the power supply terminal of the upper bridge power module 100 and the first negative voltage terminal U31 respectively, and is used to convert the second high-voltage domain signal into a first negative voltage domain signal, wherein the first negative voltage domain signal includes the voltage signal of the power supply terminal of the upper bridge power module 100 and the voltage signal of the first negative voltage terminal.

[0141] The first conversion unit 1121 and the second conversion unit 1122 each include two sets of switch pairs. In the same conversion unit, the drain of the master control transistor of one set of switch pairs is connected to the gate of the slave control transistor, and is shared with the drain of the slave control transistor of the other set of switch pairs, serving as the output terminal of the conversion unit. The source of the slave control transistor of the first conversion unit 1121 and the source of the master control transistor of the second conversion unit 1122 are respectively connected to the power supply terminal of the upper bridge power module 100. The source of the master control transistor of the first conversion unit 1121 is connected to the ground terminal of the upper bridge power module 100, and the source of the slave control transistor of the second conversion unit 1122 is connected to the first negative voltage terminal. The gate of the master control transistor of the first conversion unit 1121 is respectively connected to the high voltage level conversion unit 111, and the gate of the master control transistor of the second conversion unit 1122 is respectively connected to the output terminal of the first conversion unit 1121. The upper bridge negative voltage level conversion unit 112 also includes an upper bridge signal generation unit 1123 and an upper bridge control unit 1124. The upper bridge signal generation unit 1123 is connected to the high voltage level conversion unit 111 and is used to receive the first high voltage domain signal and generate an upper bridge pulse drive signal when the level of the first high voltage domain signal changes. The upper bridge control unit 1124 is connected to the gate of the upper bridge target slave control transistor of the upper bridge signal generation unit 1123 and the upper bridge target conversion unit respectively, and is used to disconnect the upper bridge target slave control transistor according to the upper bridge pulse drive signal. The upper bridge target conversion unit includes at least one of the first conversion unit 1121 and the second conversion unit 1122, and the upper bridge target slave control transistor is the slave control transistor of the upper bridge target conversion unit that is turned on at the previous conversion time.

[0142] The upper bridge gate drive unit 113 includes a first control unit 1131, a second control unit 1132, and a third control unit 1133. The first control unit 1131 is used to stop outputting the first voltage V1 according to the first level signal of the first negative voltage domain signal and output a first feedback signal to the second control unit 1132. The second control unit 1132 is used to output a second voltage V2 according to the first feedback signal. The second control unit 1132 is also used to stop outputting the second voltage V2 after outputting the second voltage and before the first level signal of the first negative voltage domain signal changes, and output a second feedback signal to the third control unit 1133. The third control unit 1133 is used to output a third voltage V3 according to the second feedback signal. Furthermore, the third control unit 1133 is also used to stop outputting the third voltage V3 according to the second level signal of the first negative voltage domain signal, and output a third feedback signal to the second control unit 1132; the second control unit 1132 is also used to output the second voltage V2 according to the third feedback signal; the second control unit 1132 is also used to stop outputting the second voltage V2 after outputting the second voltage and before the second level signal of the first negative voltage domain signal changes, and output a second feedback signal to the first control unit 1131; the first control unit 1131 is also used to output the first voltage V1 according to the second feedback signal.

[0143] The dead-time control module 140 is also used to generate a lower-bridge control signal based on the command signal. The lower-bridge drive module 120 includes a lower-bridge negative voltage level conversion unit 121 and a lower-bridge gate drive unit 122. Figure 10 As shown, the lower bridge negative voltage level conversion unit 121 is connected to the dead zone control module 140 and is used to output the second negative voltage domain signal according to the lower bridge control signal; the lower bridge gate drive unit 122 is connected to the lower bridge negative voltage level conversion unit 121 and is used to turn the lower tube M2 on or off according to the second negative voltage domain signal.

[0144] The lower gate drive unit 122 can also be used to sequentially pull the gate voltage of the lower transistor M2 from the fourth voltage to the fifth voltage and from the fifth voltage to the sixth voltage according to the second negative voltage domain signal, so as to turn on the lower transistor M2; or sequentially pull the gate voltage of the lower transistor M2 from the sixth voltage to the fifth voltage and from the fifth voltage to the fourth voltage according to the second negative voltage domain signal, so as to turn off the lower transistor M2; wherein the fourth voltage is the gate voltage when the lower transistor M2 is turned off, the sixth voltage is the gate voltage when the lower transistor M2 is turned on, and the voltage value of the fifth voltage is within the voltage value range of the fourth voltage and the sixth voltage.

[0145] The lower bridge negative voltage level conversion unit 121 includes a third conversion unit 1211 and a fourth conversion unit 1212. The third conversion unit 1211 is connected to the dead-time control module 140 and the lower bridge power module 200, respectively, and is used to output a positive voltage domain signal provided by the lower bridge power module 200 according to the lower bridge control signal. The fourth conversion unit 1212 is connected to the third conversion unit 1211, the power supply terminal and the second negative voltage terminal U4 of the lower bridge power module 200, respectively, and is used to convert the positive voltage domain signal into a second negative voltage domain signal, wherein the second negative voltage domain signal includes the voltage signal of the power supply terminal and the voltage signal of the second negative voltage terminal of the lower bridge power module 200.

[0146] The third conversion unit 1211 and the fourth conversion unit 1212 each include two sets of switch pairs. In the same conversion unit, the drain of the master control transistor of one set of switch pairs is connected to the gate of the slave control transistor, and is shared with the drain of the slave control transistor of the other set of switch pairs, serving as the output terminal of the conversion unit. The source of the slave control transistor of the third conversion unit 1211 and the source of the master control transistor of the fourth conversion unit 1212 are respectively connected to the power supply terminal of the lower bridge power module 200. The source of the master control transistor of the third conversion unit 1211 is connected to the ground terminal of the lower bridge power module 200, and the source of the slave control transistor of the fourth conversion unit 1212 is connected to the second negative voltage terminal. The gate of the master control transistor of the third conversion unit 1211 is respectively connected to the dead zone control module 140, and the gate of the master control transistor of the fourth conversion unit 1212 is respectively connected to the output terminal of the third conversion unit 1211. The lower bridge negative voltage level conversion unit 121 also includes a lower bridge signal generation unit 1213 and a lower bridge control unit 1214. The lower bridge signal generation unit 1213 is connected to the dead-time control module 140 and is used to receive the lower bridge control signal and generate a lower bridge pulse drive signal when the lower bridge control signal level changes. The lower bridge control unit 1214 is connected to the gate of the lower bridge target slave control transistor of the lower bridge signal generation unit 1213 and the lower bridge target conversion unit, respectively, and is used to disconnect the lower bridge target slave control transistor according to the lower bridge pulse drive signal. The lower bridge target conversion unit includes at least one of the third conversion unit 1211 and the fourth conversion unit 1212, and the target slave control transistor is the slave control transistor of the lower bridge target conversion unit that is turned on at the previous conversion time.

[0147] The lower bridge gate drive unit 122 includes a fourth control unit 1221, a fifth control unit 1222, and a sixth control unit 1223, such as Figure 13 As shown; the fourth control unit 1221 is used to stop outputting the fourth voltage V4 according to the first level signal of the second negative voltage domain signal, and output a fourth feedback signal to the fifth control unit 1222; the fifth control unit 1222 is used to output the fifth voltage V5 according to the fourth feedback signal; the fifth control unit 1222 is also used to stop outputting the fifth voltage V5 after outputting the fifth voltage V5 and before the first level signal of the second negative voltage domain signal changes, and output a fifth feedback signal to the sixth control unit 1223; the sixth control unit 1223 is used to output the sixth voltage V6 according to the fifth feedback signal. Furthermore, the sixth control unit 1223 is also used to stop outputting the sixth voltage according to the second level signal of the second negative voltage domain signal, and output a sixth feedback signal to the fifth control unit 1222; the fifth control unit 1222 is also used to output the fifth voltage according to the sixth feedback signal; the fifth control unit 1222 is also used to stop outputting the fifth voltage after outputting the fifth voltage and before the second level signal of the second negative voltage domain signal changes, and output a fifth feedback signal to the fourth control unit 1221; the fourth control unit 1221 is also used to output the fourth voltage according to the fifth feedback signal.

[0148] The gate driver integrated circuit may also include a gate protection module 160, such as Figure 14 As shown, the gate protection module 160 is connected to the gate of the lower transistor M2 and the upper bridge drive module 110, respectively, and is used to control the upper bridge drive module 110 to turn off the upper transistor M1 if the lower transistor M2 is in the on state. The dead time control module 140 may include a dead time resistor; the dead time control module 140 is also used to control the upper bridge drive module 110 to delay the dead time to turn on the upper transistor M1, and to control the lower bridge drive module to delay the dead time to turn on the lower transistor M2, wherein the dead time corresponds one-to-one with the resistance value of the dead time resistor.

[0149] When the dead-time control module 140 includes a dead-time resistor, the dead-time control module 140 is also used to control the upper bridge drive module 130 to disconnect the upper MOSFET M1 and control the lower bridge drive module 120 to disconnect the lower MOSFET M2 if the command signal indicates that the upper MOSFET M1 and the lower MOSFET M2 are simultaneously turned on.

[0150] The isolation transmission module 130 includes a modulation and transmission unit, a high-voltage isolation capacitor, and a signal demodulation unit. The modulation and transmission unit is used to receive a command signal and modulate it to obtain a high-frequency signal. The high-voltage isolation capacitor is connected to the modulation and transmission unit and is used to couple the high-frequency signal to the signal demodulation unit. The signal demodulation unit is connected to the high-voltage isolation capacitor and the dead-time control module 140 respectively and is used to demodulate the high-frequency signal to obtain the command signal and transmit it to the dead-time control module 140.

[0151] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A gate driver integrated circuit, characterized in that, The gate driver integrated circuit, applied to a half-bridge circuit, includes: The upper bridge drive module is connected to the gate of the upper transistor of the half-bridge circuit; The lower bridge drive module is connected to the gate of the lower transistor of the half-bridge circuit; An isolated transmission module is used to receive and output command signals; The dead-zone control module is connected to the isolation transmission module, the upper bridge drive module, and the lower bridge drive module, respectively. It is used to generate an upper bridge control signal according to the instruction signal, and to control the upper bridge drive module to turn on or off the upper transistor according to the instruction signal, and to control the lower bridge drive module to turn on or off the lower transistor; wherein the upper transistor and the lower transistor are not turned on at the same time. The upper bridge drive module includes: A high-voltage level conversion unit, connected to the dead-time control module, is used to output a first high-voltage domain signal according to the upper bridge control signal; The upper bridge negative voltage level conversion unit includes a first conversion unit and a second conversion unit. The first conversion unit is connected to the high voltage level conversion unit and the upper bridge power module, respectively, and is used to output a second high voltage domain signal provided by the upper bridge power module according to the first high voltage domain signal. The second conversion unit is connected to the first conversion unit, the power supply terminal of the upper bridge power module, and the first negative voltage terminal, respectively, and is used to convert the second high voltage domain signal into a first negative voltage domain signal. The first negative voltage domain signal includes the voltage signal of the power supply terminal of the upper bridge power module and the voltage signal of the first negative voltage terminal. The upper bridge gate drive unit is connected to the upper bridge negative voltage level conversion unit and is used to turn the upper tube on or off according to the first negative voltage domain signal.

2. The gate driver integrated circuit according to claim 1, characterized in that, The gate driver integrated circuit also includes: An over-temperature and over-current protection module, connected to the dead-time control module, is used to instruct the dead-time control module to control the upper bridge drive module to disconnect the upper MOSFET and the lower bridge drive module to disconnect the lower MOSFET if at least one of the following is detected: the temperature of the gate driver integrated circuit exceeds a temperature threshold or the current flowing through the lower MOSFET exceeds a current threshold.

3. The gate driver integrated circuit according to claim 1, characterized in that, The upper bridge gate drive unit is further configured to: sequentially pull the gate voltage of the upper transistor from a first voltage to a second voltage and from the second voltage to a third voltage according to the first negative voltage domain signal, so as to turn on the upper transistor; or According to the first negative voltage domain signal, the gate voltage of the upper transistor is sequentially pulled from the third voltage to the second voltage and then from the second voltage to the first voltage to disconnect the upper transistor; Wherein, the first voltage is the gate voltage when the upper transistor is turned off, the third voltage is the gate voltage when the upper transistor is turned on, and the voltage value of the second voltage is within the range of the first voltage and the third voltage.

4. The gate driver integrated circuit according to claim 1, characterized in that, The dead-time control module is further configured to generate a bridge down-bridge control signal based on the command signal, and the bridge down-bridge drive module includes: The lower-bridge negative voltage level conversion unit includes a third conversion unit and a fourth conversion unit. The third conversion unit is connected to the dead-time control module and the lower-bridge power supply module, respectively, and is used to output a positive voltage domain signal provided by the lower-bridge power supply module according to the lower-bridge control signal. The fourth conversion unit is connected to the third conversion unit, the power supply terminal and the second negative voltage terminal of the lower-bridge power supply module, respectively, and is used to convert the positive voltage domain signal into a second negative voltage domain signal. The second negative voltage domain signal includes the voltage signal at the power supply terminal of the lower-bridge power supply module and the voltage signal at the second negative voltage terminal. The lower bridge gate drive unit is connected to the lower bridge negative voltage level conversion unit and is used to turn the lower transistor on or off according to the second negative voltage domain signal.

5. The gate driver integrated circuit according to claim 4, characterized in that, The lower bridge gate drive unit is also used for: The gate voltage of the lower transistor is sequentially pulled from the fourth voltage to the fifth voltage, and then from the fifth voltage to the sixth voltage to turn on the lower transistor; or According to the second negative voltage domain signal, the gate voltage of the lower transistor is sequentially pulled from the sixth voltage to the fifth voltage, and then from the fifth voltage to the fourth voltage, so as to disconnect the lower transistor; Wherein, the fourth voltage is the gate voltage when the lower transistor is disconnected, the sixth voltage is the gate voltage when the lower transistor is turned on, and the voltage value of the fifth voltage is within the range of the fourth voltage and the sixth voltage.

6. The gate driver integrated circuit according to claim 1, characterized in that, The gate driver integrated circuit also includes: A gate protection module is connected to the gate of the lower transistor and the upper bridge drive module respectively, and is used to control the upper bridge drive module to disconnect the upper transistor if the lower transistor is in the on state.

7. The gate driver integrated circuit according to claim 1, characterized in that, The dead-time control module includes a dead-time resistor; the dead-time control module is also used to control the upper bridge drive module to delay the dead time to turn on the upper transistor, and to control the lower bridge drive module to delay the dead time to turn on the lower transistor, wherein the dead time corresponds one-to-one with the resistance value of the dead-time resistor.

8. The gate driver integrated circuit according to claim 7, characterized in that, The dead-time control module is further configured to control the upper bridge drive module to disconnect the upper MOSFET and control the lower bridge drive module to disconnect the lower MOSFET if the instruction signal indicates that the upper MOSFET and the lower MOSFET are simultaneously turned on.

9. The gate driver integrated circuit according to claim 1, characterized in that, The isolated transmission module includes a modulation and transmission unit, a high-voltage isolation capacitor, and a signal demodulation unit; The modulation and transmission unit is used to receive the instruction signal and modulate it into a high-frequency signal according to the instruction signal; The high-voltage isolation capacitor is connected to the modulation and transmission unit and is used to couple and transmit the high-frequency signal to the signal demodulation unit. The signal demodulation unit is connected to the high-voltage isolation capacitor and the dead-time control module respectively, and is used to obtain the command signal based on the high-frequency signal demodulation and transmit it to the dead-time control module.

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