Computing device and method of series powering

Abstract

This disclosure relates to a computing device and a series power supply method. The computing device includes: a computing board, including a series power supply circuit disposed thereon, the series power supply circuit including m layers of power-supply chips connected in series between the positive and negative power terminals of the computing board, where m is an integer greater than 2, the highest power-supply chip of the m layers is connected to the positive power terminal of the computing board and the lowest power-supply chip is connected to the negative power terminal of the computing board, the positive power terminal of the computing board is configured to receive a higher potential relative to the negative power terminal; a control board, configured to provide control signals and communication signals to the computing board, the control signals and communication signals being accessed through the communication interface of the highest power-supply chip to the series power supply circuit and communicating down through the series-connected m layers of power-supply chips, wherein, when the series power supply circuit on the computing board is configured to include m-n layers of power-supply chips, the lowest n layers of power-supply chips are replaced with conductive patches.

Description

Technical Field

[0001] This disclosure relates to the field of power supply technology, and particularly to the field of series power supply technology for computing chips. Specifically, it also relates to a method for sharing the same PCB when different chip levels are connected in series in a DC high voltage series power supply circuit. Background Technology

[0002] With the development of semiconductor technology, the operating power supply voltage of integrated circuit chips is getting lower and lower, while the operating current is getting higher and higher. In order to maximize power conversion efficiency, existing technologies have begun to adopt a series power supply method on printed circuit boards (PCBs) to form a series power supply circuit, that is, to form a multi-stage series voltage domain between the power supply terminal and the ground terminal. In this field, the PCB plus the chips on it is usually referred to as a computing board, which constitutes an important component of electrical equipment. However, existing series power supply circuits using this series power supply architecture still have some problems.

[0003] Therefore, it is necessary to design a new and optimized series power supply scheme. Summary of the Invention

[0004] According to a first aspect of this disclosure, a computing device is provided, the computing device comprising: a computing board including a series power supply circuit disposed on the computing board, the series power supply circuit including m layers of power supply chips connected in series between a positive power terminal and a negative power terminal of the computing board, where m is an integer greater than 2, wherein the highest power supply chip of the m layers of power supply chips is connected to the positive power terminal of the computing board and the lowest power supply chip of the m layers of power supply chips is connected to the negative power terminal of the computing board, wherein the positive power terminal of the computing board is configured to receive a higher potential relative to the negative power terminal of the computing board; a control board configured to provide control signals and communication signals to the computing board, the control signals and communication signals being accessed through the communication interface of the highest power supply chip in the series power supply circuit and communicating down through the series-connected m layers of power supply chips, wherein, when the series power supply circuit on the computing board is configured to include mn layers of power supply chips, the lowest n layers of power supply chips are replaced with conductive patches.

[0005] According to a second aspect of this disclosure, a series power supply method is provided for supplying power to a series power supply circuit including m layers of chips to be powered. The series power supply method includes: placing the m layers of chips to be powered on a computing board and connecting them in series between the positive and negative power terminals of the computing board, where m is an integer greater than 2; connecting the highest-level chip to be powered in the m layers to the positive power terminal of the computing board and connecting the lowest-level chip to the negative power terminal of the computing board, wherein the positive power terminal of the computing board is configured to receive a higher potential relative to the negative power terminal of the computing board; connecting a control board to the computing board to provide control signals and communication signals to the computing board, wherein the control signals and communication signals are accessed through the communication interface of the highest-level chip to be powered in the series power supply circuit and communicate down through the serially connected m layers of chips to the next layer, wherein when the series power supply circuit is configured to include mn layers of chips to be powered, the lowest n-layer chips to be powered are replaced with conductive patches.

[0006] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0008] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0009] Figure 1 A schematic diagram of a series power supply circuit in the prior art is shown.

[0010] Figure 2 A schematic block diagram of a computing device in the prior art is shown.

[0011] Figure 3 A schematic block diagram of a computing device according to an embodiment of the present disclosure is shown.

[0012] Figure 4 Another structural block diagram of a computing device according to an embodiment of the present disclosure is shown schematically;

[0013] Figure 5 A schematic flowchart of one embodiment of the series power supply method according to the present disclosure is shown.

[0014] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0015] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0016] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0017] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the circuits and methods herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in this disclosure and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways.

[0018] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0019] This disclosure can be applied to computer systems / servers that can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer systems / servers include, but are not limited to: personal computer systems, server computer systems, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems, etc.

[0020] Computer systems / servers can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are performed by remote processing devices linked through a communication network. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0021] Reference Figure 1 This diagram schematically illustrates a series power supply circuit in the prior art. In practice, the high-current core voltage (i.e., main operating voltage) of the chip to be powered is typically supplied via a series circuit. The negative power supply terminal of the higher-level chip to be powered serves as the power supply terminal of the lower-level chip, and vice versa, and so on, in series. Furthermore, for the power supply of special functional components such as input / output I / O interfaces and PLL circuits within each chip to be powered, this embodiment of the invention provides power through an auxiliary power supply unit corresponding to the chip on the same level. Specifically, for ease of explanation, in... Figure 1 The diagram uses m layers of chips to be powered, where each layer is designated as the first chip A1, the second chip A2, ..., the ninth chip A9, the tenth chip A10, the eleventh chip A11, ..., the mth chip Am. Depending on circuit configuration, each layer may include one chip or multiple chips connected in parallel within the same voltage domain. Each layer of chips is connected to an auxiliary power supply unit, which may be designated as the first auxiliary voltage unit B1, the second auxiliary power unit B2, ..., the ninth auxiliary power unit B9, the tenth auxiliary power unit B10, the eleventh auxiliary power unit B11, ..., the mth auxiliary power unit Bm. Depending on the configuration of the chips, each auxiliary power supply unit may include one or more auxiliary power supply units.

[0022] like Figure 1As shown, the series power supply circuit includes m layers of chips to be powered between the power supply terminal VCC and the ground terminal GND. These m layers of chips are connected in series, forming a voltage domain on each layer. Thus, the series power supply circuit, including the m layers of chips, forms m series-connected voltage domains, where m is an integer greater than 1. Each layer of chips has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a negative power supply terminal. The power supply terminal VCC is connected to the main operating voltage input terminal of the highest-level chip Am. The negative power supply terminal of each layer is connected to the main operating voltage input terminal of the next-level chip, thereby providing a main operating voltage to each layer of chips via the main operating voltage input terminal. The series power supply circuit also includes auxiliary power supply units corresponding to each layer of chips. The negative power supply terminal of each auxiliary power supply unit is connected to the negative power supply terminal of the chip in the same layer. The output terminal of each auxiliary power supply unit is connected to the auxiliary operating voltage input terminal of the chip in the same layer. At least one auxiliary power supply unit (e.g., ...) Figure 1 The input terminal of the auxiliary power supply unit (Bm) is connected to an external power supply terminal for power supply. The input terminals of the remaining auxiliary power supply units are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered, starting from the highest-level chip. Thus, the auxiliary power supply unit provides auxiliary operating voltage to the connected chips via the auxiliary operating voltage input terminals of the chips to be powered. The auxiliary power supply unit typically uses an LDO module to provide auxiliary operating voltage to special function modules such as I / O (input / output) modules and PLL (phase-locked loop) modules within the connected chips to be powered.

[0023] In some embodiments, the case of a series power supply circuit comprising 40 layers of chips to be powered, i.e., m = 40, is described as an example. In one example, the main operating voltage (i.e., core voltage) of each layer of chips to be powered can be 0.3V, and the following description is based on the example of a 12V DC power supply voltage provided by the power supply terminal VCC. However, those skilled in the art should understand that the operating voltages listed here are merely for the convenience of description. Of course, those skilled in the art should understand that, depending on the circuit hardware structure, circuit application, power supply configuration, etc., the main operating voltage of each layer of chips to be powered is not limited to 0.3V, and the power supply voltage received by the power supply terminal VCC is not limited to a 12V DC power supply voltage. In one example, assuming that the internal resistance of each layer of chips to be powered is the same, then the voltage value input to the main operating voltage input terminal of each layer of chips to be powered decreases sequentially, i.e., 12V, 11.7V, 11.4V, 11.1V...0.3V, so that a main operating voltage of approximately 0.3V can be provided on each layer of chips to be powered.

[0024] Secondly, for special functional components such as input / output I / O interfaces and PLL phase-locked loops in each layer of chips to be powered, Figure 1 In this circuit, power is supplied by an auxiliary power supply unit corresponding to the chip to be powered on in the same layer, and the auxiliary power supply unit's auxiliary operating voltage is generally greater than the main operating voltage of each chip to be powered on. In one example, the auxiliary operating voltage (i.e., I / O voltage and PLL phase-locked loop voltage) provided by the auxiliary power supply unit to the auxiliary voltage input terminal of the connected chip to be powered can be about 1.8V, which is 0.3V greater than the main operating voltage of each chip to be powered on. Of course, those skilled in the art should understand that, depending on circuit configuration and other factors, the auxiliary operating voltage provided by the auxiliary power supply unit can be any suitable value.

[0025] In this example, since the auxiliary operating voltage supplied to the connected chip by the auxiliary power supply unit is six times the main operating voltage of the chip, considering the voltage drop of the auxiliary power supply unit, the lower-level auxiliary power supply unit can use the main operating voltages of the eight or fewer layers of chips to perform voltage division, thereby maintaining an auxiliary operating voltage of approximately 1.8V for each layer of auxiliary power supply unit. For example, in one example, such as Figure 1 As shown, the bottom-level chip A1 receives a 0V ground voltage at its negative power supply terminal and a 0.3V operating voltage at its main operating voltage input terminal. Furthermore, the ninth-level chip A9 receives a 2.4V voltage at its negative power supply terminal and a 2.7V operating voltage at its main operating voltage input terminal. At this time, the bottom-level auxiliary power supply unit B1 can receive the 2.7V operating voltage from the main operating voltage input terminal of the ninth-level chip A9. Then, the bottom-level auxiliary power supply unit B1 adjusts the voltage, so that its output can provide an auxiliary operating voltage of approximately 1.8V to the connected chip via its auxiliary voltage input terminal. Therefore, in one example, as... Figure 1As shown, the bottom auxiliary power supply unit B1 can be provided with an auxiliary operating voltage by means of the main operating voltage of the 9th layer chip A9, the 2nd layer auxiliary power supply unit B2 can be provided with an auxiliary operating voltage by means of the main operating voltage of the 10th layer chip A10, the 9th layer auxiliary power supply unit B9 can be provided with an auxiliary operating voltage by means of the main operating voltage of the 17th layer chip A17 (not shown), the 10th layer auxiliary power supply unit B10 can be provided with an auxiliary operating voltage by means of the main operating voltage of the 18th layer chip A18 (not shown), the 11th layer auxiliary power supply unit B11 can be provided with an auxiliary operating voltage by means of the main operating voltage of the 19th layer chip B19 (not shown), and so on. The 32nd layer auxiliary power supply unit can be provided with an auxiliary operating voltage (not shown) by means of the main operating voltage (i.e., 12V) of the 40th layer chip. Therefore, the auxiliary power supply units of layers 1 to 32 can use the voltage drawn from the main operating voltage input terminal of the chip to be powered in a higher layer and output after being regulated by an LDO or BUCK as the auxiliary operating voltage of the connected chip to be powered.

[0026] However, for the current circuit structure, in this example, for the chips to be powered on, such as the 33rd layer and above, the auxiliary power supply units require higher voltages and cannot draw power from the main operating voltage of the higher-layer chips. Therefore, an additional power supply is needed to provide a higher voltage source. For example, in a commonly used VCC 12V series system, a boost circuit is often required to increase the voltage before supplying power to the auxiliary power supply units of the highest-layer chips via an LDO. Specifically, in one embodiment, the boost circuit is connected to the power supply terminal VCC to receive the power supply voltage and to provide the boosted voltage to the aforementioned external power supply terminal.

[0027] Specifically, in this example, for the 40th layer auxiliary power supply unit, since there is not enough voltage difference between the supply voltage VCC 12V and the negative terminal voltage 11.7V of the 40th layer auxiliary power supply unit, an additional boost circuit is needed to boost the 12V voltage to at least 14.7V to ensure that the auxiliary power supply unit can also provide an auxiliary operating voltage of 1.8V.

[0028] This invention describes an example where each auxiliary power supply unit draws its main operating voltage from the main operating voltage input terminals of eight layers of chips to be powered upwards to provide the input voltage for that auxiliary power supply unit. However, those skilled in the art should understand that the invention is not limited thereto. For example, in one embodiment, it may be necessary for the auxiliary power supply unit to input a larger or smaller voltage for adjustment; in this case, each auxiliary power supply unit may draw its main operating voltage from five, six, seven, or more layers of chips to be powered upwards to provide the input voltage for that auxiliary power supply unit.

[0029] In addition, for example, in a series power supply circuit including a structure of 35 chips to be powered, the 12V DC voltage is first converted to 10.5V by a DC-DC power supply module as the main operating voltage of the 35th (top) chip Am to be powered.

[0030] Reference Figure 2 The diagram schematically illustrates the structure of a computing device 200 in the prior art. Specifically, the computing device 200 may include a computing board 201 and a control board 202.

[0031] The computing board 201 includes a series power supply circuit 203 disposed thereon. The series power supply circuit 203 includes m layers of chips to be powered, connected in series between the positive and negative power terminals of the computing board 201, where m is an integer greater than 2. The highest-level chip in the m-layer power supply is connected to the positive power terminal of the computing board 201, and the lowest-level chip in the m-layer power supply is connected to the negative power terminal of the computing board 201. The positive power terminal of the computing board 201 is configured to receive the power supply voltage VCC, and the negative power terminal of the computing board 201 is configured to ground (GND). The power supply voltage input, i.e., approximately 12V (some use approximately 15V-18V, or higher), provides the main operating voltage from the highest-level chip to the lowest-level chip. For this current circuit structure, such as... Figure 1 As shown, the input voltage of the auxiliary power supply unit for each layer of the chip to be powered is drawn from the main operating voltage of the chip in the higher layer or from the boost circuit. After being regulated by an LDO or BUCK, it provides the auxiliary operating voltage to the chip via the auxiliary voltage input terminal of the connected chip. Therefore, it can be seen that in... Figure 2 In the example, the auxiliary operating voltage of the lower-level chip to be powered is provided downwards by the higher-level chip to be powered or an additional boost circuit (not shown) via an auxiliary power supply unit, such as... Figure 2 The solid arrow in the diagram is shown. For the sake of brevity, the diagram is... Figure 2 The auxiliary power supply unit, boost circuit, and other related components in the series power supply circuit 203 are omitted.

[0032] Generally, the negative power supply terminal of the control board 202 can be grounded to GND together with the negative power supply terminal of the computing board 201. Therefore, in the prior art, both the computing board 201 and the control board 202 use the ground voltage of the negative power supply terminal as a reference voltage. Thus, the control board 202 is configured to provide control signals and communication signals to the computing board using the ground voltage as a reference voltage. The control signals and communication signals enter the series power supply circuit 203 from the control board 202 through the communication interface of the lowest-level chip to be powered in the series power supply circuit 203, pass through the inside of the chip to be powered, and are transmitted level by level to the upper layers, such as... Figure 2As shown by the dashed arrow in the image.

[0033] However, as chip manufacturing processes become increasingly advanced, the number of chip grades produced is also increasing. To reduce the number of machine models, different grades of chips are sometimes used, connected in series with different numbers of layers to achieve the same overall machine parameters. Because there are many chip grades, a single machine model can have multiple different circuit configurations (with different numbers of connected layers), resulting in a wide variety of PCB types and difficulties in material control.

[0034] For example, when designing circuits, using Class A chips requires 35 layers connected in series, with 3 chips per layer; using Class B chips requires 33 layers connected in series, with 3 chips per layer; and using Class C chips requires 31 layers connected in series, with 3 chips per layer. This allows machines built using all three classes of chips to achieve the same or similar parameters. Figure 2 To fabricate a PCB for a given circuit structure, three different sizes of circuits and PCBs are required.

[0035] In view of the above, this disclosure aims to provide a method for sharing the same PCB when different chip levels are connected in series in a DC high voltage series power supply circuit, as well as the corresponding computing device and compatible layout structure.

[0036] Reference Figure 3 The diagram illustrates a structural block diagram of a computing device 300 according to an embodiment of the present disclosure. In this example, the computing device 300 may specifically include a computing board 301 and a control board 302.

[0037] The computing board 301 includes a series power supply circuit 303 disposed thereon. The series power supply circuit 303 includes m layers of chips to be powered, connected in series between the positive and negative power terminals of the computing board 301, where m is an integer greater than 2. The highest-level chip in the m layers is connected to the positive power terminal of the computing board 301, and the lowest-level chip is connected to the negative power terminal of the computing board 301. The positive power terminal of the computing board 301 is configured to receive a higher potential relative to the negative power terminal. In one embodiment, such as... Figure 3As shown, the positive power terminal of the computing board 301 is configured to receive the power supply voltage VCC, and the negative power terminal of the computing board 301 is configured to be grounded (GND). However, the invention is not limited to this. In another embodiment, the positive power terminal of the computing board 301 can be configured to be grounded, and the negative power terminal of the computing board 301 can be configured to receive a negative power supply voltage; and in yet another embodiment, the positive power terminal of the computing board 301 can be configured to receive a positive voltage, and the negative power terminal of the computing board 201 can be configured to receive a negative voltage, and the negative power terminal of the highest-level chip to be powered in the series power supply circuit 303 can be grounded, as long as the higher-level chip to be powered can provide the auxiliary operating voltage to the lower-level chip to be powered via the auxiliary power supply unit. In one embodiment, as... Figure 3 As shown, the power supply voltage input, i.e., approximately VCC 12V (some use approximately 15V~18V, or higher), provides the main operating voltage from the highest-level chip to the lowest-level chip. For this current circuit structure, as... Figure 1 As shown, the input voltage of the auxiliary power supply unit for each layer of the chip to be powered is drawn from the main operating voltage of the chip in the higher layer or from the boost circuit. After being regulated by an LDO or BUCK, it provides the auxiliary operating voltage to the chip via the auxiliary voltage input terminal of the connected chip. Therefore, it can be seen that in... Figure 3 In the example, the auxiliary operating voltage of the lower-level chip to be powered is provided downwards by the higher-level chip to be powered or an additional boost circuit (not shown) via an auxiliary power supply unit, such as... Figure 3 The solid arrow in the diagram is shown. For the sake of brevity, the diagram is... Figure 3 The auxiliary power supply unit, boost circuit, and other related components in the series power supply circuit 303 are omitted.

[0038] Furthermore, when the positive power terminal of the computing board 301 is configured to be grounded and the negative power terminal of the computing board 301 is configured to receive a negative power supply voltage, the main operating voltage is provided from the highest-level chip to the lowest-level chip. In this current circuit structure, the input voltage of the auxiliary power supply unit for each layer of chips is derived from the main operating voltage of the higher-level chip or from the control board, regulated by an LDO or BUCK, and then provides auxiliary operating voltage to the connected chip via its auxiliary voltage input terminal. Therefore, the auxiliary operating voltage for the lower-level chips is provided downwards from the higher-level chip or the control board (not shown in the figures) via the auxiliary power supply unit.

[0039] In addition, in order to achieve matching of control signals and communication signals, such as Figure 3As shown, the negative power supply terminal -Vsys of the control board 302 is not grounded, but can be connected to the negative power supply terminal of the highest-level chip to be powered in the series power supply circuit. In another case, when the positive power supply terminal of the computing board 301 is grounded and the negative power supply terminal of the computing board 301 receives a negative power supply voltage, the negative power supply terminal -Vsys of the control board 302 can be connected to the positive power supply terminal of the computing board 301, or the negative power supply terminal -Vsys of the control board 302 can be connected to the ground terminal of the highest-level chip to be powered in the series power supply circuit 303. Furthermore, in one embodiment, when the positive power supply terminal of the computing board 301 is configured to receive a positive voltage and the negative power supply terminal of the computing board 301 is configured to receive a negative voltage, the negative power supply terminal -Vsys of the control board 302 can be connected to the negative power supply terminal of the highest-level chip to be powered in the series power supply circuit 303 and grounded. Thus, in this technical solution, control signals and communication signals from the control board 302 can be accessed via the communication interface of the highest-level chip to be powered, and can communicate with lower layers through the series-connected chips to be powered, such as... Figure 3 As shown by the dashed arrow in the diagram. Furthermore, the control signals and communication signals of the control board 302 can be connected to the communication and control signals of the highest-level chip to be powered through common level conversion or isolation methods, thereby achieving signal level matching. Level conversion or isolation methods can include, for example, optocouplers, transformers, capacitive coupling, network interfaces, etc. For simplicity in the accompanying drawings, ... Figure 3 Level conversion or isolation is not shown. Therefore, it can be concluded that... Figure 3 In the example, the control signals and communication signals of the communication line are from top to bottom.

[0040] In another example, the negative power supply terminal -Vsys of control board 302 can be connected to the negative power supply terminal of the chip to be powered on in other layers except the top layer, and signal level matching can be achieved through appropriate level shifting or isolation chips.

[0041] Therefore, in this embodiment, both the power lines and communication lines are arranged from top to bottom. Thus, this invention provides a method for achieving the same overall system parameters with a single PCB design compatible with different levels of chips. The main method is to design the PCB according to the most frequently used series layers. During surface mount manufacturing, when fewer series layers are needed, the unused layers are directly mounted as conductor patches (e.g., copper sheets), preserving the current path.

[0042] However, in the existing solution, because the higher-level chips need to provide auxiliary operating voltage to the lower-level chips, they cannot be replaced with copper sheets. Also, because the communication channel is connected from the lower-level chips to the higher-level chips in series, the lower-level chips cannot be replaced with copper sheets either.

[0043] In the chip-series circuit of this invention, the control signals and communication signals of the control board are accessed by higher-level chips and transmitted to lower-level chips through the series chips. The control signals and communication signals of the control board are connected to the communication signals and control signals of the highest-level chip through level conversion or isolation chips. In this way, the auxiliary power supply is provided downwards from the higher-level chips, and the communication signals are also transmitted downwards from the higher-level chips. For the lowest-level chips, when it is necessary to reduce the number of layers, copper sheets can be used for replacement without affecting the normal operation of the entire circuit.

[0044] For example, when designing circuits, using Class A chips requires 35 layers connected in series, with 3 chips per layer; using Class B chips requires 33 layers connected in series, with 3 chips per layer; and using Class C chips requires 31 layers connected in series, with 3 chips per layer. This allows machines built using all three classes of chips to achieve the same or similar parameters. Figure 2 The circuit structure requires PCB fabrication in three different sizes, but using... Figure 3 For a circuit with this structure, you can make just one standard circuit and PCB, with only 35 layers in series. When using a 33-layer structure, you only need to replace the main chips on the bottom two layers with copper plates, and you don't need to attach the surrounding resistors, capacitors, LDOs, etc. For a 31-layer series circuit, the same operation method can be used, just replace the bottom four layers of chips with copper plates.

[0045] Figure 4 Another structural block diagram of a computing device 400 according to an embodiment of the present disclosure is shown schematically. Figure 4 The computing device 400 and Figure 3 The computing device 300 in the middle has a similar structure and includes components similar to those in the middle. Figure 3 The computing board 401 and control board 402 are computing board 301 and control board 302, respectively, wherein the computing board 401 includes a series power supply circuit 403. Figure 4 In the example shown, the bottom two layers of chips (e.g., Figure 1 The chips A1 to A2 to be powered in the middle are replaced with copper sheets, and the corresponding auxiliary power supply units (e.g., Figure 1 (Auxiliary power supply units B1-B2 in the middle). In another embodiment, the bottom layer of more or fewer chips can be replaced with copper sheets, and the corresponding auxiliary power supply units are not attached.

[0046] Therefore, the present invention can provide a method that can achieve the same overall system parameters with a single PCB design compatible with different levels of chips.

[0047] Figure 5 A schematic flowchart illustrating one embodiment of the series power supply method according to this disclosure is shown. Figure 5As shown in the figure, the series power supply method of this invention is used to supply power to a series power supply circuit including m layers of chips to be powered. The method includes:

[0048] Step S11: Place the m-layer chips to be powered on the computing board and connect them in series between the positive and negative power terminals of the computing board, where m is an integer greater than 2.

[0049] Step S12: Connect the highest-level chip in the m-layer power supply to the positive terminal of the power supply of the computing board and connect the lowest-level chip in the m-layer power supply to the negative terminal of the power supply of the computing board, wherein the positive terminal of the power supply of the computing board is configured to receive a higher potential relative to the negative terminal of the power supply of the computing board.

[0050] In some implementations, each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a power supply negative terminal. The method includes: connecting the positive power supply terminal of the computing board to the main operating voltage input terminal of the highest layer of chips to be powered, and connecting the negative power supply terminal of each layer of chips to be powered to the main operating voltage input terminal of the next layer of chips to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal; connecting the negative power supply terminal of each auxiliary power supply unit corresponding to each layer of chips to be powered to the negative power supply terminal of the chips to be powered in the same layer, and connecting the output terminal of each auxiliary power supply unit to the auxiliary operating voltage input terminal of the chips to be powered in the same layer, wherein the input terminal of at least one auxiliary power supply unit is connected to an external power supply terminal for power supply, and the input terminals of the remaining auxiliary power supply units are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered from the highest layer of chips to be powered, thereby providing an auxiliary operating voltage to the connected chips to be powered via the auxiliary operating voltage input terminal.

[0051] Step S13: Connect the control board to the computing board to provide control signals and communication signals to the computing board. The control signals and communication signals are accessed through the communication interface of the highest-level chip to be powered in the series power supply circuit, and communicate down to the next layer through the serially connected m-layer chips to be powered. In one embodiment, when the positive power terminal of the computing board is configured to receive power supply voltage and the negative power terminal of the computing board is configured to be grounded, the series power supply method further includes connecting the input terminal of the boost circuit to the positive power terminal of the computing board and connecting the output terminal to an external power supply terminal. In another embodiment, when the positive power terminal of the computing board is configured to be grounded and the negative power terminal of the computing board is configured to receive a negative power supply voltage, the series power supply method further includes configuring the voltage regulator circuit included in the control board to provide a regulated voltage to the external power supply terminal.

[0052] In some implementations, the series power supply method further includes connecting the negative power supply terminal of the control board to the negative power supply terminal of the highest-level chip to be powered in the series power supply circuit.

[0053] Step S14: When the series power supply circuit is configured to include mn layers of chips to be powered, the bottom n layer of chips to be powered is replaced with a conductor patch.

[0054] In some implementations, when the series power supply circuit is configured to include mn layers of chips to be powered, the series power supply method further includes removing the bottom n-layer auxiliary power supply unit corresponding to the bottom n-layer chips to be powered.

[0055] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0056] According to one aspect of this disclosure, a computing device is provided, the computing device comprising: a computing board including a series power supply circuit disposed on the computing board, the series power supply circuit including m layers of power supply chips connected in series between a positive power terminal and a negative power terminal of the computing board, where m is an integer greater than 2, wherein the highest power supply chip of the m layers of power supply chips is connected to the positive power terminal of the computing board and the lowest power supply chip of the m layers of power supply chips is connected to the negative power terminal of the computing board, wherein the positive power terminal of the computing board is configured to receive a higher potential relative to the negative power terminal of the computing board; a control board configured to provide control signals and communication signals to the computing board, the control signals and communication signals being accessed through the communication interface of the highest power supply chip in the series power supply circuit and communicating down through the series-connected m layers of power supply chips, wherein, when the series power supply circuit on the computing board is configured to include mn layers of power supply chips, the lowest n layers of power supply chips are replaced with conductive patches.

[0057] In one embodiment, each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a power supply negative terminal. The positive terminal of the computing board is connected to the main operating voltage input terminal of the highest-layer chip to be powered, and the negative terminal of each layer of chips to be powered is connected to the main operating voltage input terminal of the next layer of chips to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal. Each auxiliary power supply unit is provided corresponding to each layer of chips to be powered. The negative terminal of each auxiliary power supply unit is connected to the negative terminal of the chip to be powered in the same layer, and the output terminal of each auxiliary power supply unit is connected to the auxiliary operating voltage input terminal of the chip to be powered in the same layer. At least one auxiliary power supply unit has its input terminal connected to an external power supply terminal for power supply, and the input terminals of the remaining auxiliary power supply units are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered from the highest-layer chip to the next layer, thereby providing an auxiliary operating voltage to the connected chips to be powered via the auxiliary operating voltage input terminal.

[0058] In one embodiment, the negative power terminal of the control board is connected to the negative power terminal of the highest-level chip to be powered in the series power supply circuit.

[0059] In one embodiment, when the series power supply circuit is configured to include mn layers of chips to be powered, the bottom n-layer auxiliary power supply unit corresponding to the bottom n-layer chips to be powered is removed.

[0060] In one embodiment, the positive terminal of the computing board is configured to receive a power supply voltage and the negative terminal of the computing board is configured to be grounded.

[0061] In one embodiment, the positive terminal of the power supply of the computing board is configured to be grounded, and the negative terminal of the power supply of the computing board is configured to receive a negative power supply voltage.

[0062] In one embodiment, the series power supply circuit further includes a boost circuit, the input of which is connected to the positive power supply terminal of the computing board, and the output of which is connected to the external power supply terminal.

[0063] In one embodiment, the control board includes a voltage regulator circuit configured to provide a regulated voltage to the external power supply.

[0064] According to another aspect of this disclosure, a series power supply method is provided for supplying power to a series power supply circuit including m layers of chips to be powered. The series power supply method includes: placing the m layers of chips to be powered on a computing board and connecting them in series between the positive power terminal and the negative power terminal of the computing board, where m is an integer greater than 2; connecting the highest layer of the m layers of chips to be powered to the positive power terminal of the computing board and connecting the lowest layer of the m layers of chips to the negative power terminal of the computing board, wherein the positive power terminal of the computing board is configured to receive a higher potential relative to the negative power terminal of the computing board; connecting a control board to the computing board to provide control signals and communication signals to the computing board, wherein the control signals and communication signals are accessed through the communication interface of the highest layer of chips to be powered in the series power supply circuit and communicate down through the serially connected m layers of chips to the next layer, wherein when the series power supply circuit is configured to include mn layers of chips to be powered, the lowest n layers of chips to be powered are replaced with conductive patches.

[0065] In one embodiment, each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a negative power supply terminal. The series power supply method includes: connecting the positive power supply terminal of the computing board to the main operating voltage input terminal of the highest layer of chips to be powered; connecting the negative power supply terminal of each layer of chips to be powered to the main operating voltage input terminal of the next layer of chips to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal; connecting the negative power supply terminal of each auxiliary power supply unit corresponding to each layer of chips to be powered to the negative power supply terminal of the chips to be powered in the same layer; connecting the output terminal of each auxiliary power supply unit to the auxiliary operating voltage input terminal of the chips to be powered in the same layer; wherein at least one auxiliary power supply unit has its input terminal connected to an external power supply terminal for power supply; and the input terminals of the remaining auxiliary power supply units are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered from the highest layer of chips to be powered, thereby providing an auxiliary operating voltage to the connected chips to be powered via the auxiliary operating voltage input terminal.

[0066] In one embodiment, the series power supply method further includes connecting the negative power supply terminal of the control board to the negative power supply terminal of the highest-level chip to be powered in the series power supply circuit.

[0067] In one embodiment, when the series power supply circuit is configured to include mn layers of chips to be powered, the series power supply method further includes removing the bottom n-layer auxiliary power supply unit corresponding to the bottom n-layer chips to be powered.

[0068] In one embodiment, the series power supply method further includes configuring the positive terminal of the computing board to receive the power supply voltage and configuring the negative terminal of the computing board to ground.

[0069] In one embodiment, the series power supply method further includes configuring the positive terminal of the computing board to ground and configuring the negative terminal of the computing board to receive a negative power supply voltage.

[0070] In one embodiment, the series power supply method further includes connecting the input terminal of the boost circuit to the positive power supply terminal of the computing board and connecting the output terminal to the external power supply terminal.

[0071] In one embodiment, the series power supply method further includes configuring a voltage regulator circuit included in the control board to provide a regulated voltage to the external power supply terminal.

[0072] The terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc., used in the specification and claims, if present, are for descriptive purposes and are not necessarily used to describe unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can, for example, operate on other orientations different from those shown or otherwise described herein.

[0073] As used herein, the term "exemplary" means "used as an example, instance, or illustration" and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied in the foregoing description of the technical field, background, invention, or detailed description.

[0074] As used herein, the word "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0075] The above description may refer to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, “coupled” means that one element / node / feature can be directly or indirectly connected to another element / node / feature mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, “coupled” is intended to include both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0076] It should also be understood that when the term "includes / contains" is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0077] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0078] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A computing device, comprising: The computing device comprises: a computing power board comprising a PCB and a series power supply circuit arranged on the PCB, the series power supply circuit comprising m layers of to-be-powered chips connected in series between a power supply positive pole of the computing power board and a power supply negative pole of the computing power board, wherein m is an integer greater than 2, wherein the uppermost layer of to-be-powered chips in the m layers of to-be-powered chips is connected to the power supply positive pole of the computing power board and the lowermost layer of to-be-powered chips in the m layers of to-be-powered chips is connected to the power supply negative pole of the computing power board, wherein the power supply positive pole of the computing power board is configured to receive a higher potential relative to the power supply negative pole of the computing power board, wherein each layer of to-be-powered chips has a main working voltage input end, an auxiliary working voltage input end and a power supply negative pole end, the power supply positive pole of the computing power board is connected to the main working voltage input end of the uppermost layer of to-be-powered chips, the power supply negative pole end of each layer of to-be-powered chips is connected to the main working voltage input end of the next layer of to-be-powered chips, and the main working voltage input end of each layer of to-be-powered chips is configured to receive a higher potential relative to the main working voltage input end of the next layer of to-be-powered chips; each layer of auxiliary power supply units corresponding to each layer of to-be-powered chips, the power supply negative pole end of each layer of auxiliary power supply units being connected to the power supply negative pole end of the to-be-powered chips of the same layer, and the output end of each layer of auxiliary power supply units being connected to the auxiliary working voltage input end of the to-be-powered chips of the same layer, wherein the input end of at least one layer of auxiliary power supply units is connected to an external power supply end for power supply, and the input end of each of the remaining layers of auxiliary power supply units is sequentially connected to the main working voltage input end of the to-be-powered chips of the corresponding number of layers from the uppermost layer of to-be-powered chips downwards, so as to provide auxiliary working voltage for the connected to-be-powered chips via the auxiliary working voltage input end; a control board configured to provide control signals and communication signals to the computing power board, the control signals and communication signals being accessed into the series power supply circuit via the communication interface of the uppermost layer of to-be-powered chips in the series power supply circuit and communicated downwards through the m layers of to-be-powered chips connected in series, wherein in the series power supply circuit, the transmission direction of the control signals and communication signals is consistent with the power supply direction from the uppermost layer of to-be-powered chips receiving a higher potential to the lowermost layer of to-be-powered chips receiving a lower potential; wherein the PCB can be configured to connect different chip layers in series, and in the case that the series power supply circuit on the PCB is configured to comprise m-n layers of to-be-powered chips, the lowermost n layers of to-be-powered chips are directly replaced by conductor patches, so as to reserve current channels and communication channels.

2. The computing device of claim 1, wherein, The power supply negative pole of the control board is connected to the power supply negative pole end of the uppermost layer of to-be-powered chips in the series power supply circuit.

3. The computing device of claim 1, wherein, In the case that the series power supply circuit is configured to comprise m-n layers of to-be-powered chips, the lowermost n layers of auxiliary power supply units corresponding to the lowermost n layers of to-be-powered chips are removed.

4. The computing device of claim 1, wherein, The power supply positive pole of the computing power board is configured to receive a power supply voltage and the power supply negative pole of the computing power board is configured to be grounded.

5. The computing device of claim 1, wherein, The power supply positive pole of the computing power board is configured to be grounded and the power supply negative pole of the computing power board is configured to receive a negative power supply voltage.

6. The computing device of claim 4, wherein, The series power supply circuit further comprises a boost circuit, an input end of the boost circuit being connected to a power supply positive pole of the computing power board, and an output end of the boost circuit being connected to the external power supply end.

7. The computing device of claim 5, wherein, The control board comprises a voltage stabilizing circuit configured to provide a stabilized voltage to the external power supply end.

8. A series power supply method for supplying power to a series power supply circuit comprising m layers of chips to be powered, each layer of chips to be powered having a main operating voltage input, an auxiliary operating voltage input and a power supply negative terminal, characterized in that, The series power supply method comprises: arranging the m layers of chips to be powered on a computing power board and connecting the m layers of chips to be powered in series between a power supply positive pole of the computing power board and a power supply negative pole of the computing power board, wherein m is an integer greater than 2, the computing power board comprises a PCB, connecting a topmost layer of chips to be powered among the m layers of chips to be powered to the power supply positive pole of the computing power board and connecting a bottommost layer of chips to be powered among the m layers of chips to be powered to the power supply negative pole of the computing power board, wherein the power supply positive pole of the computing power board is configured to receive a higher potential relative to the power supply negative pole of the computing power board, wherein the power supply positive pole of the computing power board is connected to a main working voltage input end of the topmost layer of chips to be powered, a power supply negative pole end of each layer of chips to be powered is connected to a main working voltage input end of a next layer of chips to be powered, and the main working voltage input end of each layer of chips to be powered is configured to receive a higher potential relative to the main working voltage input end of the next layer of chips to be powered; connecting a power supply negative pole end of each layer of auxiliary power supply units corresponding to each layer of chips to be powered to a power supply negative pole end of a chip to be powered in the same layer, connecting an output end of each layer of auxiliary power supply units to an auxiliary working voltage input end of a chip to be powered in the same layer, wherein an input end of at least one layer of auxiliary power supply units is connected to an external power supply end for power supply, and input ends of the remaining layers of auxiliary power supply units are sequentially connected to main working voltage input ends of corresponding layers of chips to be powered from the topmost layer of chips to be powered downwards, so as to provide auxiliary working voltage to the connected chips to be powered via the auxiliary working voltage input end; connecting a control board to the computing power board to provide control signals and communication signals to the computing power board, the control signals and communication signals being accessed into the series power supply circuit via a communication interface of a topmost layer of chips to be powered in the series power supply circuit and being communicated downwards through the m layers of chips to be powered connected in series, wherein in the series power supply circuit, a transmission direction of the control signals and communication signals is consistent with a power supply direction from the topmost layer of chips to be powered receiving a higher potential to the bottommost layer of chips to be powered receiving a lower potential; wherein the PCB can be configured to connect different chip layers in series, and in a case where the series power supply circuit on the PCB is configured to comprise m-n layers of chips to be powered, the bottommost n layers of chips to be powered are directly replaced by conductor patches, so as to reserve current channels and communication channels.

9. The method of claim 8, wherein, The series power supply method further comprises connecting a power supply negative pole of the control board to a power supply negative pole end of a topmost layer of chips to be powered in the series power supply circuit.

10. The method of claim 8, wherein, In a case where the series power supply circuit is configured to comprise m-n layers of chips to be powered, the series power supply method further comprises removing a bottommost n layer of auxiliary power supply units corresponding to a bottommost n layer of chips to be powered.

11. The method of claim 8, wherein, The series power supply method further includes configuring a power supply positive pole of the computing power board to receive a power supply voltage and configuring a power supply negative pole of the computing power board to be grounded.

12. The method of claim 8, wherein, The series power supply method further includes configuring a power supply positive pole of the computing power board to be grounded and configuring a power supply negative pole of the computing power board to receive a negative power supply voltage.

13. The method of claim 11, wherein, The series power supply method further includes connecting an input end of a boost circuit to the power supply positive pole of the computing power board and connecting an output end to the external power supply end.

14. The method of claim 12, wherein, The series power supply method further includes configuring a voltage stabilizing circuit included in the control board to provide a voltage stabilized by the voltage stabilizing circuit to the external power supply end.

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