Power semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a method for manufacturing a power semiconductor structure, comprising: providing a semiconductor substrate with a first conductivity type; sequentially forming a groove in the semiconductor substrate, a gate oxide layer located at the edge of the groove and the bottom of the groove, and a dielectric layer filling the groove; sequentially forming a base region, a source region and an insulating layer on the semiconductor substrate; forming a contact hole passing through the insulating layer and the source region and reaching the base region, a hole groove being formed at the bottom of the contact hole, one side of the contact hole being self-aligned with the boundary of a gate oxide layer, and the other side of the contact hole maintaining a set spacing with an adjacent gate oxide layer; forming a heavily doped region with a second conductivity type below the hole groove, and the method can improve the manufacturability and consistency of such devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a power semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the upgrading of power semiconductor technology, the current density per unit area in the core cell region is getting higher and higher, and the internal cell structure is also undergoing significant changes. The gate has evolved from the early planar gate to the trench gate, and the trench cell pitch has been reduced to the micron level. As the trench cell pitch continues to shrink to below 2.0um, the design and process of the contact holes on the active area between the trenches face challenges.

[0003] In order to ensure strong anti-latch or reverse bias safe operating area (SOA) capabilities, power semiconductors need to minimize base resistance, which is usually achieved through high-dose implantation behind the contact hole. When the trench cell pitch is small, the distance between the contact hole and the trench and the channel is small. A slight left-right alignment deviation of the contact hole and the subsequent high-dose implantation process steps will affect the doping of the channel area and the overall device characteristics, posing challenges to the consistency, repeatability and manufacturability of the device.

[0004] Therefore, there is an urgent need to provide a novel design scheme and manufacturing method for a power semiconductor contact hole structure to improve the manufacturability and consistency of such devices. Summary of the invention

[0005] The object of the present invention is to provide a power semiconductor structure and a manufacturing method thereof, so as to improve the manufacturability and consistency of such devices.

[0006] To achieve the above-mentioned purpose, the present invention provides a method for manufacturing a power semiconductor structure, comprising: providing a semiconductor substrate with a first conductivity type; sequentially forming a groove in the semiconductor substrate, a gate oxide layer located at the edge of the groove and the bottom of the groove, and a dielectric layer filling the groove; sequentially forming a base region, a source region and an insulating layer on the semiconductor substrate; forming a contact hole passing through the insulating layer and the source region and reaching the base region, a hole groove being formed at the bottom of the contact hole, one side of the contact hole being self-aligned with the boundary of a gate oxide layer, and the other side of the contact hole maintaining a set distance with the adjacent gate oxide layer; and forming a heavily doped region with a second conductivity type below the hole groove.

[0007] The beneficial effect of the manufacturing method of the power semiconductor structure provided by the present invention is that: through the above-mentioned manufacturing method, for non-full channel devices, the gate oxide layer on the non-channel side can be used as a boundary to form self-alignment of contact holes, thereby reducing process complexity and reducing the demand for high-end high-precision lithography machines, thereby reducing production costs and improving the manufacturability and consistency of such devices.

[0008] Optionally, a trench, a gate oxide layer located at an edge of the trench and a bottom of the trench, and a dielectric layer filling the trench are sequentially formed in the semiconductor substrate, including:

[0009] The semiconductor substrate is etched to form a trench in the semiconductor substrate; a gate oxide layer is formed at the edge and bottom of the trench; and a dielectric is filled in the trench to form a dielectric layer.

[0010] Optionally, forming a base region, a source region and an insulating layer on the semiconductor substrate in sequence includes:

[0011] A base region is formed on the semiconductor substrate by ion implantation, wherein the base region is located between the adjacent trenches on the semiconductor substrate and has the second conductivity type; a source region is formed between the adjacent trenches by ion implantation, wherein the source region is located between the adjacent trenches on the semiconductor substrate and has the first conductivity type with a high doping concentration; and an insulating layer covering the base region and the source region is formed on the base region and the source region.

[0012] Optionally, forming a contact hole that passes through the insulating layer and the source region and reaches the base region, wherein a hole groove is formed at the bottom of the contact hole, one side of the contact hole is self-aligned with a boundary of a gate oxide layer, and the other side of the contact hole maintains a set distance with an adjacent gate oxide layer, comprising:

[0013] A photoresist is applied, and a window of a set size is etched with a gate oxide layer as a boundary, and the other side of the contact hole maintains a set distance with the adjacent gate oxide layer; an inverted trapezoidal groove is formed based on the window; and further etching is performed to form a hole groove at the bottom of the groove that slightly passes through the insulating layer and the source region and reaches the body region.

[0014] Optionally, the groove is a U-shaped groove.

[0015] Optionally, the contact hole is in an inverted trapezoidal shape.

[0016] Optionally, the set spacing can be adjusted according to actual needs.

[0017] Optionally, the material of the insulating layer includes silicon dioxide.

[0018] Optionally, the contact hole is filled with a conductive material.

[0019] In a second aspect, an embodiment of the present invention further provides a power semiconductor structure, characterized in that it includes:

[0020] Semiconductor substrate;

[0021] A trench in the semiconductor substrate, wherein the edges of the trench and the bottom of the trench are provided with a gate oxide layer, and the trench is filled with a dielectric layer;

[0022] A base region, a source region and an insulating layer sequentially located on the semiconductor substrate;

[0023] A contact hole penetrating the insulating layer and the source region and reaching the base region, wherein a hole groove is formed at the bottom of the contact hole, one side of the contact hole is self-aligned with a boundary of a gate oxide layer, and the other side of the contact hole maintains a set distance with an adjacent gate oxide layer;

[0024] A heavily doped region of the second conductivity type is located below the hole.

[0025] The power semiconductor structure provided by the present invention has the beneficial effects of good device consistency, good repeatability and manufacturability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a power semiconductor structure provided by the present invention;

[0027] Figure 2 is a schematic diagram of a method for manufacturing a power semiconductor structure according to some embodiments of the present invention;

[0028] FIG. 3A to FIG. 3I Schematic cross-sectional views of intermediate structures of some further embodiments of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0030] At present, in the manufacturing process of power semiconductor devices, there are two common improvement methods to improve the contact hole alignment accuracy. The first solution is to use a more advanced lithography machine to ensure the alignment accuracy and smaller contact hole size to increase the distance from the contact hole to the channel. Due to the relatively high cost of using high-end equipment and processes, the contact hole size is small, and the high-dose doping after the contact hole is formed is relatively small, and the reduction of the base resistance is limited. The second solution is to use self-aligned contact holes to eliminate alignment deviations, and form a "bird's beak" structure of the oxide layer on the top of the trench through high-temperature thermal oxidation. With the help of the high selectivity of the oxide layer and silicon, contact holes and hole grooves are formed along the oxide layer boundary during the etching process of forming the contact hole. However, due to the relatively complex process and the limited size of the "bird's beak", the increase in the distance from the contact hole to the channel is not significant.

[0031] To this end, an embodiment of the present invention proposes a novel power semiconductor structure and a manufacturing method thereof, which realizes self-alignment of contact holes formed by using the gate oxide layer on the non-full channel side as a boundary for power semiconductors with non-full channels, so that the contact holes can be laterally translated, and the contact holes can be enlarged while also increasing the distance from the contact holes to the gate oxide layer and the channel on the other side, thereby reducing the complexity of the power semiconductor structure manufacturing process, reducing the demand for high-end high-precision lithography machines, and thus reducing production costs.

[0032] The implementation of the power semiconductor structure of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0033] In a specific embodiment of the power semiconductor structure of the present invention, reference Figure 1 The power semiconductor structure may include: a semiconductor substrate 100 of a first conductivity type; a trench 201 located in the semiconductor substrate 100, a gate oxide layer 202 is provided at the edge of the trench 201 and the bottom of the trench 201, and a dielectric layer 203 is filled in the trench. A base region 300 of a second conductivity type is located on the semiconductor substrate 100 and between the adjacent trenches 201; a source region 400 of a first conductivity type with a high doping concentration is located on the base region 300 and between the adjacent trenches 201; and an insulating layer 500 covering the base region 300 and the source region 400. A contact hole 600 passes through the insulating layer 500 and the source region 400 and reaches the base region 300, and a hole groove 700 is provided at the bottom of the contact hole 600, one side of the contact hole 600 is self-aligned with the boundary of the gate oxide layer 202, and the other side of the contact hole 600 maintains a set distance with the adjacent gate oxide layer, and the set distance can be adjusted according to actual needs. A heavily doped region 800 of the second conductivity type is located below the hole 700 .

[0034] Specifically, the semiconductor substrate 100 may include a base and a lightly doped region, wherein the lightly doped region is also called an epitaxial layer. The epitaxial layer may be lightly doped with n-type. For example, arsenic, antimony, or phosphorus ions may be implanted, with a doping concentration of 10 14 / cm 3 -10 15 / cm 3 The substrate and source region 400 may be heavily doped with n-type. For example, arsenic, antimony, or phosphorus ions may be implanted to form a doping concentration of 10 16 / cm 3 -10 19 / cm 3 n-type heavily doped region within the range.

[0035] The base region 300 may be lightly doped with a p-type. For example, the base region 300 may be doped with boron ions to make the base region 300 have a doping concentration of 10 14 / cm 3 -10 15 / cm 3 A p-type lightly doped region within the range.

[0036] The contact hole 600 may be inverted trapezoidal to prevent carriers from gathering along the sidewalls; and the heavily doped region 800 is distributed at the bottom of the hole groove 700. The heavily doped region 800 may be p-type heavily doped, and its doping ions may be boron ions, and the doping concentration may be 10 16 / cm 3 -10 19 / cm 3 scope.

[0037] In this embodiment, one side of the contact hole 600 is self-aligned with the boundary of a gate oxide layer, and the other side of the contact hole 600 maintains a set distance with the adjacent gate oxide layer, and the distance can be adjusted as needed. Since the heavily doped region 800 is distributed on the outer surface of the bottom of the hole groove 700, the heavily doped region 800 is separated from the PN junction formed by the source region 400 and the base region 300.

[0038] On the one hand, the above power semiconductor structure reduces or even avoids the influence of carriers generated by the expansion of the PN junction space charge region on the heavily doped region 800 by separating the heavily doped region 800 from the PN junction and ensuring a set spacing, thereby avoiding the following defects: carriers gather under a concentrated electric field, causing a surge in reverse current, thereby causing avalanche breakdown. On the other hand, for non-full channel devices, the gate oxide layer on the non-channel side is used as a boundary to form a self-alignment of the contact hole 600, thereby reducing the process complexity and the requirements for the photolithography accuracy of the photolithography machine, thereby reducing the production cost.

[0039] See also Figure 2The method for manufacturing a power semiconductor structure provided by an embodiment of the present invention comprises the following steps:

[0040] S201 , providing a semiconductor substrate 100 having a first conductivity type.

[0041] In this step, refer to Figure 3A The semiconductor substrate 100 of the first conductivity type may be an N-type or P-type silicon substrate. The following description takes the semiconductor substrate 100 as an N-type substrate as an example. For example, a high-concentration n-type ion implantation may be performed into the polysilicon layer to form an n-type heavily doped substrate, wherein the doping ions may be arsenic, antimony, or phosphorus, etc., wherein the doping concentration of arsenic ions may be 10 16 / cm 3 The injection energy can be 10KEV (1KeV = 1.60217646 × 10 -16 Joule). Then, an epitaxial layer is formed on the substrate. The epitaxial layer has a first conductivity type and a concentration lower than that of the substrate. The epitaxial layer is lightly doped with n-type. For example, the epitaxial layer can be implanted with arsenic, antimony, or phosphorus ions with a doping concentration of 10 14 / cm 3 ~10 15 / cm 3 scope.

[0042] S202 , sequentially forming a trench 201 , a gate oxide layer 202 located at the edge of the trench 201 and the bottom of the trench 201 , and a dielectric layer 203 filling the trench in the semiconductor substrate 100 .

[0043] In this step, in detail, the semiconductor substrate 100 may be etched first to form a trench 201 in the semiconductor substrate 100. Figure 3B As shown, by coating photoresist on the semiconductor substrate 100 and then performing pattern etching, a photolithography window can be formed first, and then the semiconductor substrate corresponding to the window area is further patterned and etched to form a Figure 3B The trench 201 shown in FIG. 1 may be a U-shaped opening. A gate oxide layer 202 is then formed at the edge of the trench 201 and at the bottom of the trench 201. Figure 3C As shown, a gate oxide layer 202 is formed at the edge of the U-shaped trench and the bottom of the U-shaped trench. Further, a dielectric is filled in the trench 201 to form a dielectric layer 203. For example, Figure 3D As shown, the trench corresponding to the window area is filled, and the medium used to fill the trench in this step may be polysilicon.

[0044] S203 , forming a base region 300 , a source region 400 and an insulating layer 500 on the semiconductor substrate 100 in sequence.

[0045] For example, Figure 3E As shown, by ion implantation, for example, boron ions, the implantation dose may be 10 14 cm -2 ; Then, by high temperature diffusion, a P-type base region 300 is formed. Further, as Figure 3F As shown, a source region 400 is formed between the adjacent trenches 201 by ion implantation. The source region 400 is located between the adjacent trenches 201 on the semiconductor substrate 100 and has a first conductivity type with a high doping concentration.

[0046] For example, Figure 3F As shown, the photoresist is first etched to form a source region injection window, and then, referring to Figure 3F , by implanting ions into the source region, the implanted ions can be arsenic, antimony, or phosphorus, etc., and the implantation dose can be 10 16 cm -2 , forming a source region 400 with heavy n-type doping.

[0047] Afterwards, an insulating layer 500 is formed on the base region 300 and the source region 400 to cover the base region 300 and the source region 400. Figure 3G As shown, silicon dioxide or silicon nitride is formed on the surface of the source region 400 and the base region 300 by thermal oxidation or chemical vapor deposition to form an insulating layer 500 .

[0048] Optionally, the material of the insulating layer includes silicon dioxide.

[0049] S204, forming a contact hole 600 that passes through the insulating layer 500 and the source region 400 and reaches the base region 300, a hole groove 700 is formed at the bottom of the contact hole 600, one side of the contact hole 600 is self-aligned with the boundary of a gate oxide layer 202, and the other side of the contact hole 600 maintains a set distance with the adjacent gate oxide layer.

[0050] Specifically, for example, Figure 3H As shown, a photoresist is coated, and a window of a set size is etched with the gate oxide layer as the boundary. An inverted trapezoidal groove is first etched based on the window, and then further etched, as shown in FIG. Fig. 3IAs shown, the bottom of the trench slightly passes through the insulating layer and the source region and reaches the body region. The etching can be dry etching, and the etching gas can use an etching gas containing carbon tetrafluoride (CF4) to achieve almost no side etching but only vertical etching, thereby obtaining a vertical sidewall of the trench. Afterwards, the bottom of the inverted trapezoidal trench and the trench are filled with conductive materials, such as metal tungsten, and then the excess conductive material outside the trench is removed by chemical mechanical polishing, etc., to form a contact hole structure. In a specific embodiment, the etching gas can be carbon tetrafluoride.

[0051] S205 , forming a heavily doped region 800 of the second conductivity type below the hole 700 .

[0052] Specifically, ion implantation is performed at the bottom of the trench to form a p-type heavily doped region 800, forming a reference Figure 1 The semiconductor structure shown. For example, the doping ions may be boron ions, and the doping concentration may be 3×10 15 / cm 3 , the implantation energy is 25KeV.

[0053] In the embodiment of the present invention, the above manufacturing method can be used for non-full channel devices, using the gate oxide layer on the non-channel side as the boundary to form self-alignment of contact holes, thereby reducing process complexity, reducing the requirements for photolithography accuracy of the photolithography machine, and thus reducing production costs. The present invention is suitable for cell structures with dense grooves, and the groove cell pitch is less than 2um; the present invention is mainly aimed at but not limited to non-full channel devices, and non-full channel refers to a single-sided channel next to the groove; the present invention can be used for but not limited to micro-groove IGBTs (virtual grooves) and MOSFETs (especially single-sided channel SiC MOSFETs).

[0054] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A method for manufacturing a power semiconductor structure, characterized in that: include: providing a semiconductor substrate having a first conductivity type; Forming a trench, a gate oxide layer located at the edge of the trench and the bottom of the trench, and a dielectric layer filling the trench in the semiconductor substrate in sequence; forming a base region, a source region and an insulating layer on the semiconductor substrate in sequence; A contact hole is formed through the insulating layer and the source region and reaches the base region, wherein a hole groove is formed at the bottom of the contact hole, one side of the contact hole is self-aligned with the boundary of a gate oxide layer, and the other side of the contact hole maintains a set distance with the adjacent gate oxide layer. The forming of the contact hole through the insulating layer and the source region and reaches the base region comprises: coating a photoresist, etching a window of a set size with a gate oxide layer as a boundary, and the other side of the contact hole maintains a set distance with the adjacent gate oxide layer; Based on the window etching, an inverted trapezoidal groove is formed; Further etching is performed so that a hole is formed at the bottom of the trench, slightly passing through the insulating layer and the source region and reaching the body region; A heavily doped region of the second conductivity type is formed below the hole.

2. The method according to claim 1, characterized in that A trench, a gate oxide layer located at the edge of the trench and the bottom of the trench, and a dielectric layer filling the trench are sequentially formed in the semiconductor substrate, including: Etching the semiconductor substrate to form a groove in the semiconductor substrate; forming a gate oxide layer at the edge of the trench and at the bottom of the trench; A dielectric is filled in the trench to form a dielectric layer.

3. The method according to claim 2, characterized in that Sequentially forming a base region, a source region and an insulating layer on the semiconductor substrate, including: By ion implantation, a base region is formed on the semiconductor substrate, wherein the base region is located between the adjacent trenches on the semiconductor substrate and has a second conductivity type; By ion implantation, a source region is formed between the adjacent trenches, wherein the source region is located between the adjacent trenches on the semiconductor substrate and has a first conductivity type with a high doping concentration; An insulating layer covering the base region and the source region is formed on the base region and the source region.

4. The method according to claim 1, characterized in that The groove is a U-shaped groove.

5. The method according to claim 1, characterized in that The contact hole is in an inverted trapezoidal shape.

6. The method according to any one of claims 1 to 3, characterized in that: The size of the set spacing can be adjusted according to actual needs.

7. The method according to claim 6, characterized in that The material of the insulating layer includes silicon dioxide.

8. The method according to any one of claims 1 to 3, characterized in that: The contact hole is filled with a conductive material.

9. A power semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 8, the power semiconductor structure comprises: Semiconductor substrate; A trench in the semiconductor substrate, wherein the edges of the trench and the bottom of the trench are provided with a gate oxide layer, and the trench is filled with a dielectric layer; A base region, a source region and an insulating layer sequentially located on the semiconductor substrate; A contact hole penetrating the insulating layer and the source region and reaching the base region, wherein a hole groove is formed at the bottom of the contact hole, one side of the contact hole is self-aligned with a boundary of a gate oxide layer, and the other side of the contact hole maintains a set distance with an adjacent gate oxide layer; A heavily doped region of the second conductivity type is located below the hole.

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