Chip stacking structure

Abstract

The application discloses a chip stacking structure, which comprises a first lead frame, a first switch chip, a second switch chip, a conductive clamp and an input capacitor. The drain electrode of the first switch chip is electrically connected to a first chip base of the first lead frame. The drain electrode of the second switch chip is electrically connected to a second chip base of the first lead frame and the source electrode of the first switch chip. The conductive clamp is electrically connected to the source electrode of the second switch chip and a ground pin of the first lead frame. The input capacitor is coupled to a ground potential and an input power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to a chip stack structure, in particular, a chip stack structure with shorter conductive path. BACKGROUND

[0002] The prior art modular DC-DC converter has integrated driver MOSFET (DrMOS) proposed by Intel and Renesas or NexFET power block proposed by Texas Instruments (Ti). The DrMOS is designed by placing two or more field effect transistor switching chips in a plane and using a copper clip as a ground electrode package. The NexFET power block of Ti considers the parallel setting of the pulse width modulation integrated circuit (PWMIC) to avoid electromagnetic radiation generated when the field effect transistor is powered on, and uses two or more special specification NexFET field effect transistors.

[0003] However, in response to the continuous development of electronic products, the modular DC-DC converter with the planar arrangement has a longer conductive path, which not only has greater inductance effect and switching response time, but also has poor heat dissipation effect, which does not meet the needs of miniaturization and high frequency application. Moreover, the architecture of parallel setting PWM IC and special specification field effect transistor used in the conventional technology also increases the difficulty and cost of production.

[0004] Therefore, how to propose a chip stack structure is an important subject studied by the present inventors. SUMMARY

[0005] One of the purposes of the present application is to provide a chip stack structure with shorter conductive path than the prior art, which can eliminate inductance effect, reduce switching response time, and improve heat dissipation effect, thereby meeting the needs of miniaturization and high frequency application.

[0006] To achieve the aforementioned object, the chip stack structure includes a first lead frame, a first switch chip, a second switch chip, a conductive clip and an input capacitor. The first lead frame includes a first chip base, a second chip base and a ground pin. The first chip base is coupled to an input power supply, the second chip base is coupled to an output node, and the ground pin is coupled to a ground potential. The first switch chip includes a first drain, a first source and a first gate. The first drain is electrically connected to the first chip base. The second switch chip includes a second drain, a second source and a second gate. The first region of the second drain is electrically connected to the second chip base, and the second region of the second drain is electrically connected to the first source. The conductive clip includes a chip end and a lead frame end. The chip end is electrically connected to the second source, and the lead frame end is electrically connected to the ground pin. The input capacitor has two ends coupled to the ground potential and the input power supply. In the first direction, the second chip base extends beyond the periphery of the first chip base. In the second direction, the ground pin and the first chip base both extend beyond the periphery of the second chip base. The first direction and the second direction have a non-zero included angle. The portion of the ground pin not covered by the conductive clip includes a pin exposed region. The portion of the first chip base not covered by the second switch chip and the conductive clip includes a base exposed region. The two ends of the input capacitor are coupled to the pin exposed region and the base exposed region.

[0007] In some embodiments, in the second direction, the portion of the first switch chip not covered by the second chip base, the second switch chip and the conductive clip includes a first chip exposed region, and the first gate is located in the first chip exposed region.

[0008] In some embodiments, in the first direction, the portion of the second switch chip not covered by the conductive clip includes a second chip exposed region, and the second gate is located in the second chip exposed region.

[0009] In some embodiments, the upper surface of the first chip base is at least a gap height lower than the upper surface of the second chip base. The gap height is greater than the thickness of the first switch chip. When the first switch chip is arranged on the first chip base, the upper surface of the first switch chip is not higher than the upper surface of the second chip base.

[0010] In some embodiments, the chip stack structure further includes a first conductive layer and a second conductive layer. The first conductive layer is coated on the upper surface of the first switch chip. The second conductive layer is coated on the upper surface of the second chip base. The upper surface of the first conductive layer is substantially aligned with the upper surface of the second conductive layer, and has substantially the same height, so that the lower surface of the second switch chip is substantially horizontally arranged on the upper surface of the first conductive layer and the upper surface of the second conductive layer.

[0011] In some embodiments, the second die base has a two-branch structure in an L shape, and the two branches extend along the first direction and the second direction, respectively, and the two branches are adjacent to the two edges of the first die base, respectively.

[0012] In some embodiments, the conductive clip has a two-branch structure in an L shape, and the two branches extend along the first direction and the third direction, respectively, and the first direction, the second direction and the third direction have a non-zero included angle with each other, the lead frame end of the conductive clip extends along the third direction by at least a receiving interval, the die end of the conductive clip extends along the first direction, and the receiving interval is greater than the thickness of the second switch chip, so that the second switch chip is received between the die end of the conductive clip and the first die base.

[0013] In some embodiments, the chip stack structure further includes a control chip, the control chip includes a first surface and a second surface opposite to each other, the first surface is coupled to the die end of the conductive clip and is arranged opposite to the second switch chip, the second surface includes a plurality of contacts and is selectively electrically connected to at least one of the conductive clip, the first gate and the second gate, the conductive clip is electrically connected to the ground pin, when the first switch chip and the second switch chip generate electromagnetic radiation due to the change of the on-off state, the conductive clip shields the electromagnetic radiation and reduces the intensity of the electromagnetic radiation reaching the control chip.

[0014] One of the purposes of the present application is to provide a chip stack structure, which has a shorter conductive path compared to the prior art, can eliminate inductance effect, reduce switching response time, and improve heat dissipation effect, so as to meet the purpose of miniaturization and high frequency application.

[0015] To achieve the aforementioned object, the chip stacking structure includes a first lead frame, a first switch chip, a second lead frame, a second switch chip, a conductive clip, and an input capacitor. The first lead frame includes a first chip base, a second chip base, and a ground pin. The first chip base is coupled to an input power supply, the second chip base is coupled to an output node, and the ground pin is coupled to a ground potential. The first switch chip includes a first drain, a first source, and a first gate. The first drain is electrically connected to the first chip base. The second lead frame includes a first conductive surface and a second conductive surface opposite to each other. A first region of the first conductive surface corresponds to the second chip base, and a second region of the first conductive surface corresponds to the first source of the first switch chip. The second lead frame, the second chip base, and the first source are electrically connected to each other. The second switch chip includes a second drain, a second source, and a second gate. The second drain is electrically connected to the second conductive surface of the second lead frame. The conductive clip includes a chip end and a lead frame end. The chip end is electrically connected to the second source, and the lead frame end is electrically connected to the ground pin. The input capacitor has two ends coupled to the ground potential and the input power supply, respectively. In a first direction, the second chip base extends beyond a periphery of the first chip base. In a second direction, the ground pin and the first chip base both extend beyond a periphery of the second chip base. The first direction and the second direction have a non-zero included angle. A portion of the ground pin not covered by the conductive clip includes a pin exposed region. A portion of the first chip base not covered by the second lead frame, the second switch chip, and the conductive clip includes a base exposed region. The two ends of the input capacitor are coupled to the pin exposed region and the base exposed region, respectively.

[0016] In some embodiments, in the second direction, a portion of the first switch chip not covered by the second lead frame, the second switch chip, and the conductive clip includes a first chip exposed region, and the first gate is located in the first chip exposed region.

[0017] In some embodiments, in the first direction, a portion of the second switch chip not covered by the conductive clip includes a second chip exposed region, and the second gate is located in the second chip exposed region.

[0018] In some embodiments, an upper surface of the first chip base is lower than an upper surface of the second chip base by at least a gap height. The gap height is greater than a thickness of the first switch chip. When the first switch chip is arranged on the first chip base, an upper surface of the first switch chip is not higher than the upper surface of the second chip base.

[0019] In some embodiments, the chip stack structure further comprises a first conductive layer and a second conductive layer; wherein the first conductive layer is coated on the upper surface of the first switch chip; the second conductive layer is coated on the upper surface of the second chip base; the upper surface of the first conductive layer is substantially aligned with the upper surface of the second conductive layer and has substantially the same height, so that the lower surface of the second lead frame is substantially horizontally disposed on the upper surface of the first conductive layer and the upper surface of the second conductive layer.

[0020] In some embodiments, the second chip base has an L-shaped two-branch structure, and the two-branch structure respectively extends along the first direction and the second direction, and the two-branch structure respectively is adjacent to the two peripheries of the first chip base.

[0021] In some embodiments, the conductive clip has an L-shaped two-branch structure, and the two-branch structure respectively extends along the first direction and the third direction, and the first direction, the second direction and the third direction have a non-zero included angle with each other; the lead frame end of the conductive clip extends along the third direction by at least a receiving interval; the chip end of the conductive clip extends along the first direction; the receiving interval is greater than the thickness of the second switch chip, so that the second switch chip is accommodated between the chip end of the conductive clip and the first chip base.

[0022] In some embodiments, the chip stack structure further comprises a control chip, the control chip comprises a first surface and a second surface opposite to each other; wherein the first surface is coupled to the chip end of the conductive clip and is disposed opposite to the second switch chip; the second surface comprises a plurality of contacts and is selectively electrically connected to at least one of the conductive clip, the first gate and the second gate; the conductive clip is electrically connected to the ground pin; when the first switch chip and the second switch chip generate electromagnetic radiation due to the change of the on-off state, the conductive clip shields the electromagnetic radiation and reduces the intensity of the electromagnetic radiation reaching the control chip.

[0023] In summary, the chip stack structure of the present application can use two field effect transistors with a general architecture (e.g., the gate and source are located on the same side, and the drain is located on the opposite side) as the first switch chip and the second switch chip. The first switch chip can form a conductive path by the first chip base and the bottom of the second switch chip (e.g., conductive glue or tin paste, etc.). The second switch chip can form a conductive path by electrically connecting the first switch chip and the conductive clamping piece of the first chip base. Since the first switch chip and the second switch chip are arranged in a top-down stacked manner, compared with the prior art of placing two or more field effect transistors in a plane, the size of the area occupied by the modular elements on the circuit board can be saved, and the first switch chip and the second switch chip are arranged in a top-down stacked manner, which eliminates the additional circuit for electrically connecting between the two or more field effect transistors, reduces the impedance between the first switch chip and the second switch chip, and thereby eliminates the inductive effect of the first switch chip and the second switch chip, improves the efficiency of conduction and heat conduction.

[0024] In some embodiments, compared with the technical problem that the prior art integrated circuit is easily disturbed by the electromagnetic radiation generated by the field effect transistor due to the proximity to the voltage source, the chip stack structure of the present application can further consider arranging the control chip on the topmost conductive clamping piece, which can further reduce the area of the chip stack structure, and can avoid the electromagnetic radiation generated by the field effect transistor when energized from interfering with the operation of the control chip, but it is not limited.

[0025] Therefore, compared with the prior art, the chip stack structure of the present application has a shorter conductive path, can eliminate the inductive effect, reduce the switching response time, and improve the heat dissipation effect, and achieves the purpose of miniaturization and high frequency application.

[0026] In order to further understand the technology, means and effects adopted by the present application to achieve the predetermined purpose, please refer to the following detailed description and drawings of the present application. It is believed that the features and characteristics of the present application can be understood in depth and specifically from the drawings, which are provided for reference and illustration only, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a side view schematic diagram of the first embodiment of the chip stack structure of the present application;

[0028] Figure 2 It is a top view schematic diagram of the first embodiment of the chip stack structure of the present application;

[0029] Figure 3 It is an equivalent circuit diagram of the first embodiment of the chip stack structure of the present application;

[0030] Figure 4A side view schematic diagram of a second embodiment of the chip stack structure of the present application;

[0031] Figure 5 A top view schematic diagram of a second embodiment of the chip stack structure of the present application;

[0032] Figure 6 A structure schematic diagram of the first conductive frame of the chip stack structure of the present application; and

[0033] Figure 7 An equivalent circuit diagram of a second embodiment of the chip stack structure of the present application.

[0034] Wherein, the reference signs:

[0035] 1: chip stack structure

[0036] 2: first switch chip

[0037] 2a: first chip exposed area

[0038] 3: second switch chip

[0039] 3a: second chip exposed area

[0040] 4: conductive clip

[0041] 8: first lead frame

[0042] 9: signal pin

[0043] 10: chip pin

[0044] 11: first chip pedestal

[0045] 11a: pedestal exposed area

[0046] 12: second chip pedestal

[0047] 12a, 12b: arm structure

[0048] 13: ground pin

[0049] 13a: pin exposed area

[0050] 20: second lead frame

[0051] 20a, 31a: first area

[0052] 20b, 31b: second area

[0053] 21: first drain

[0054] 22: first source

[0055] 23: first gate

[0056] 31: second drain

[0057] 32: second source

[0058] 33: second gate

[0059] 41: chip end

[0060] 42: lead frame end

[0061] 61: first conductive layer

[0062] 62: second conductive layer

[0063] 64: third conductive layer

[0064] 100: control chip

[0065] 100a: contact

[0066] 400: metal line

[0067] CAP: input capacitor

[0068] Vin: input voltage

[0069] SW: output node

[0070] GND: ground potential

[0071] Lo: output inductor

[0072] Vo: step-down converter output port

[0073] Co: output capacitor

[0074] X: first direction

[0075] Y: second direction

[0076] Z: third direction

[0077] LD1, LS1, LD2, LS2: parasitic inductance

[0078] L1: first path

[0079] L2: second path

[0080] L3: third path

[0081] L4: fourth path DETAILED DESCRIPTION

[0082] The present application is herein described, by way of example only, with the assistance of the accompanying drawings detailed description giving specific embodiments thereof. Other advantages and benefits of the present application will become apparent to those skilled in the art from this disclosure, many variations and modifications of which can be made without departing from the spirit and scope of the application. It is to be understood that the specific order or hierarchy of steps in the methods disclosed is an example of an appropriate way to implement the methods. Based upon the disclosure and depending on the exact combination of hardware and software chosen, the claims should not be construed as limited to the order or hierarchy presented.

[0083] It is to be understood that the structures, proportions, elements, materials, and / or relative positioning reflected in the drawings are illustrative only and that variations in structure, proportions, elements, materials, and / or relative positioning are possible without departing from the spirit and scope of the application. Accordingly, other examples are within the scope of the following claims.

[0084] The technical content and detailed description of the present application are described as follows in conjunction with the drawings.

[0085] Figure 1 A side view schematic diagram of a first embodiment of the chip stack structure of the present application; Figure 2 A top view schematic diagram of a first embodiment of the chip stack structure of the present application; Figure 3 An equivalent circuit diagram of a first embodiment of the chip stack structure of the present application; Figure 6 A structure schematic diagram of a first conductive frame of the chip stack structure of the present application.

[0086] As shown in FIG. 1, Figure 1 the chip stack structure 1 of the present application includes a first lead frame 8, a first switch chip 2, a second switch chip 3, a conductive clamping sheet 4, and an input capacitor CAP (the specific structure position cannot be shown in this side view schematic diagram, so the electrical connection relationship between the two ends of the input capacitor CAP is described by a circuit symbol). Further, Figure 1 as shown in FIG. 2, Figure 2 a schematic diagram is shown in a side view cut by a section line A.

[0087] As shown in FIG. 3, Figure 1 , Figure 6 the first lead frame 8 includes a chip pin 10, a first chip base 11, a second chip base 12, and a ground pin 13. Among them, the first chip base 11 is coupled to an input power Vin, the second chip base 12 is coupled to an output node SW, and the ground pin 13 is coupled to a ground potential GND.

[0088] As shown in FIG. 4, Figure 1As shown, in some embodiments, the first die submount 11 can be made of an etched conductive material and is used to support the first switch chip 2. Furthermore, the top surface of the first die submount 11 is lower than the top surface of the second die submount 12 by at least a gap height, which is greater than the thickness of the first switch chip 2. Thus, when the first switch chip 2 is mounted on the first die submount 11, the top surface of the first switch chip 2 does not exceed the top surface of the second die submount 12. However, this is not intended to be limiting.

[0089] like Figure 6 As shown, in some embodiments, the second chip base 12 is L-shaped and has two arm structures 12a and 12b, and the two arm structures 12a and 12b extend along the first direction X and the second direction Y respectively. The two arm structures are respectively adjacent to the X-direction periphery and the Y-direction periphery of the first chip base 11, but this is not restrictive.

[0090] like Figure 1 As shown, the first switch chip 2 includes a first drain 21, a first source 22, and a first gate 23. The first drain 21 is electrically connected to the first chip base 11 to indirectly couple to the input power supply Vin. The first switch chip 2 includes a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be used as the high-side FET of a buck converter, also referred to as the HS die, i.e., the FET connected to the higher voltage side, such as the input power supply Vin, but this is not limiting.

[0091] The second switch chip 3 includes a second drain 31, a second source 32, and a second gate 33. The first region 31a of the second drain 31 is electrically connected to the second chip base 12, and the second region 31b of the second drain is electrically connected to the first source 22. The second switch chip 3 includes a metal oxide semiconductor field effect transistor (MOSFET), which can function as a low-side FET of a buck converter. This term, also referred to as the LS die (i.e., the FET connected to the lower voltage side), is not intended to be limiting.

[0092] like Figure 2As shown, the spatial relationship between the various components of the chip stack structure 1 is described based on a three-dimensional coordinate system. The three-dimensional coordinate system includes a first direction X, a second direction Y, and a third direction Z, and these three directions form a non-zero angle with each other. Along the second direction Y, the portion of the first switch chip 2 not shielded by the second switch chip 3 and the conductive clip 4 includes the first chip exposed area 2a, and the first gate 23 is located in the first chip exposed area 2a, although this is not limiting. Along the first direction X, the portion of the second switch chip 3 not shielded by the conductive clip 4 includes the second chip exposed area 3a, and the second gate 33 is located in the second chip exposed area 3a, although this is not limiting. In the plane formed by the first direction X and the second direction Y, the base exposed area 11a of the first chip base 11 is adjacent to the pin exposed area 13a of the ground pin 13.

[0093] like Figure 1 、 Figure 2 As shown, the conductive clip 4 includes a chip terminal 41 and a lead frame terminal 42 . The chip terminal 41 is electrically connected to the second source 32 , and the lead frame terminal 42 is electrically connected to the ground pin 13 .

[0094] In certain embodiments, the conductive clip 4 is L-shaped and has two arm structures. The two arm structures extend along the first direction X and the third direction Z, respectively. The arm structure corresponding to the lead frame end 42 extends along the third direction Z by at least an accommodation distance, while the arm structure corresponding to the chip end 41 extends along the first direction X. The accommodation distance is greater than the thickness of the second switch chip 3, so that the second switch chip 3 can be accommodated between the chip end 41 of the conductive clip 4 and the first chip base 11. However, this is not limiting.

[0095] like Figures 1 to 3 As shown, the two ends of the input capacitor CAP are respectively coupled to the ground potential GND and the input power supply Vin. The input capacitor CAP can be selected from one of different material capacitors such as ceramic capacitors, film capacitors, electrolytic capacitors, tantalum capacitors, polymer capacitors, etc., but it is not limited.

[0096] like Figure 1 As shown, the chip stacking structure 1 further includes a first conductive layer 61 and a second conductive layer 62. The first conductive layer 61 is coated on the upper surface of the first switch chip 2. The second conductive layer 62 is coated on the upper surface of the second chip base 12. The upper surface of the first conductive layer 61 is substantially aligned with the upper surface of the second conductive layer 62 and has substantially the same height, so that the lower surface of the second switch chip 3 is substantially horizontally disposed on the upper surfaces of the first conductive layer 61 and the second conductive layer 62.

[0097] In some embodiments, a third conductive layer 64 is further included and can be disposed at one of the following locations: between the first die base 11 and the first drain 21, between the second source 32 and the die end 41, or between the ground pin 13 and the lead frame end 42, without limitation.

[0098] In some embodiments, the first conductive layer 61, the second conductive layer 62, and the third conductive layer 64 can be selected from one of the following conductive materials: conductive glue (e.g., anisotropic conductive film (ACF) containing at least one of silver chloride (AgCl), graphite, carbon nanotube, graphene, copper, silver, gold, or alloys thereof, or a high polymer material combined with metal particles), silver glue, or tin paste, without limitation.

[0099] As shown in FIG. 1, the first conductive layer 61 is disposed between the first die base 11 and the first drain 21, the second conductive layer 62 is disposed between the second source 32 and the die end 41, and the third conductive layer 64 is disposed between the ground pin 13 and the lead frame end 42. Figure 1 Figure 3 As shown in FIG. 1, the output inductor Lo is coupled between the buck converter output port Vo and the output node SW, and the input capacitor CAP is coupled between the buck converter input power Vin and the ground GND. The first path LI from the input power Vin, through the first switching chip 2, to the output node SW affects the operation efficiency of the buck converter circuit, and the current conduction passes through the first die base 11 and the second die base 12. In addition, the second path L2 from the input power Vin, through the first switching chip 2, the second switching chip 3, the ground potential GND, the input capacitor CAP, and back to the input power Vin affects the operation efficiency of the buck converter circuit, and the current conduction passes through the first die base 11, the conductive clip 4, and the ground pin 13.

[0100] Further, the first drain 21 of the first switching chip 2 usually includes a parasitic inductance LD1, and the first source 22 of the first switching chip 2 usually includes a parasitic inductance LS1. The second drain 31 of the second switching chip 3 usually includes a parasitic inductance LD2, and the second source 32 of the second switching chip 3 usually includes a parasitic inductance LS2. When the buck converter module uses longer wiring, the above-mentioned parasitic inductance values will increase accordingly, thereby seriously reducing the operation efficiency of the buck converter circuit.

[0101] ​It is worth mentioning that, compared with the prior art, the chip stacking structure 1 of the present application directly adheres the second region 31b of the second drain 31 of the second switch chip 3 to the first source 22 of the first switch chip 2, and directly adheres the first region 31a of the second drain 31 of the second switch chip 3 to the second chip base 12, thereby shortening the conduction path between the first source 22 and the second drain 31 as much as possible, and shortening the conduction path length between the input power Vin and the output node SW. In this way, the parasitic inductance LS1 and the parasitic inductance LD2 can be greatly reduced, the inductance effect between the first switch chip 2 and the second switch chip 3 on the first path L1 and the second path L2 is reduced, and the switching response time is shortened, but this is not limited.

[0102] To this end, the chip stacking structure 1 of the present application can use two field effect transistors with a general electrode contact arrangement (for example, the gate and the source are located on the same side of the die, and the drain needs a larger area and is located on the opposite side of the die) as the first switch chip 2 and the second switch chip 3. The two opposite surfaces of the first switch chip 2 can be electrically connected to the first chip base 11 and the bottom of the second switch chip 3 (for example, conductive glue or tin paste) respectively to form a conduction path. The two opposite surfaces of the second switch chip 3 can be electrically connected to the first switch chip 2 and the conductive clamp 4 respectively to form a conduction path. Compared with the prior art, the first switch chip 2 and the second switch chip 3 are arranged in a top-down stacking manner along the third direction Z in the manner of placing two or more field effect transistors in the first direction X-second direction Y plane, which improves the benefits as follows: (1) the size of the area occupied by the modular element on the circuit board can be saved; and (2) the first switch chip 2 and the second switch chip 3 are arranged in a top-down stacking manner, the conduction path length between the first source 22 and the second drain 31 is only the thickness of the first conductive layer 61 in the third direction Z; the critical dimension (CD) of the parallel design is avoided, the additional circuit for electrically connecting between the two or more field effect transistors is eliminated, the impedance between the first switch chip 2 and the second switch chip 3 is reduced, and the inductance effect (for example, reducing the parasitic inductance LS1 and the parasitic inductance LD2) of the first switch chip 2 and the second switch chip 3 is eliminated, thereby improving the conduction and heat conduction efficiency.

[0103] As Figures 1 to 2As shown, for the part of the second path L2 related to the input power Vin, the first switch chip 2 and the second switch chip 3, the current first rises from the lower first chip base 11 to the higher conductive clip 4 chip end 41 along the third direction Z, then falls from the conductive clip 4 ground end 42 to the lower ground pin 13 along the third direction Z, and then flows on the X-Y plane to the pin exposed area 13a of the ground pin 13, and then flows through the input capacitor CAP, and then returns to the base exposed area 11a of the first chip base 11. Thus, the second path L2 part makes the charge flow upward along the third direction Z, part makes the charge flow downward along the third direction Z, part makes the charge flow right along the X-Y plane, and part makes the charge flow left along the X-Y plane, so that each part of the second path L2 extends in three coordinate directions, thus avoiding the limitation of the size and electrode position of each element of the first switch chip 2, the second switch chip 3 and the input capacitor CAP on the X-Y plane, and effectively shortening the total length of the second path L2.

[0104] Figure 4 A side view schematic diagram of a second embodiment of the chip stacking structure of the present application; Figure 5 A top view schematic diagram of a second embodiment of the chip stacking structure of the present application; Figure 7 An equivalent circuit diagram of a second embodiment of the chip stacking structure of the present application.

[0105] As Figure 4 shown, the second embodiment of the present application is substantially the same as the chip stacking structure 1 described in the foregoing first embodiment, but further includes a second lead frame 20 and a control chip 100. Further, Figure 4 is Figure 5 a schematic diagram viewed from the side by cutting with the section line A.

[0106] The second lead frame 20 includes a first conductive surface and a second conductive surface opposite to each other. Among them, the first area 20a of the first conductive surface corresponds to the second chip base 12, and the second area 20b of the first conductive surface corresponds to the first source 22 of the first switch chip 2, and the second lead frame 20, the second chip base 12 and the first source 22 are electrically connected to each other. The second drain 31 of the second switch chip 3 is electrically connected to the second conductive surface of the second lead frame 20. Further, the lower surface of the second lead frame 20 is substantially horizontally arranged on the upper surface of the first conductive layer 61 and the upper surface of the second conductive layer 62, but it is not limited.

[0107] Please refer to Figure 4The control chip 100 includes a first face (e.g., a bottom face) and a second face (e.g., a top face) opposite to each other. The first face is coupled to the chip end 41 of the conductive clip 4 and is arranged opposite to the second switch chip 3. The second face includes a plurality of contacts 100a, and each of the contacts 100a is selectively electrically connected to one of the signal pins 9, the conductive clip 4, the first gate 23, and the second gate 33. The conductive clip 4 is electrically connected to the ground pin 13. When the first switch chip 2 and the second switch chip 3 generate electromagnetic radiation due to the change of the on-off state, the conductive clip 4 shields the electromagnetic radiation and reduces the intensity of the electromagnetic radiation reaching the control chip 100, but this is not limited.

[0108] In some embodiments, the control chip 100 includes a pulse width modulation integrated circuit (PWM IC) for outputting a control signal including pulse width modulation (PWM) to the first gate 23 of the first switch chip 2 and the second gate 33 of the second switch chip 3, and controlling the on-off of the current channel of the first switch chip 2 and the second switch chip 3, but this is not limited. Further, the wire bonding process can be applied to the control chip 100, so that the control chip 100 is electrically connected to the conductive clip 4 by the metal wire 400, and the control signal including pulse width modulation (PWM) is output to the first gate 23 of the first switch chip 2 and the second gate 33 of the second switch chip 3 by the metal wire 400, but this is not limited.

[0109] As shown in Figure 4 , Figure 7 , the third path L3 affecting the operation efficiency of the buck converter circuit is from the input power Vin, through the first switch chip 2 to the output node SW; the specific structure of the current conduction further includes the first chip base 11, the second lead frame 20, and the second chip base 12. In addition, the fourth path L4 affecting the operation efficiency of the buck converter circuit is from the input power Vin, through the first switch chip 2, the second switch chip 3, the ground potential GND, the input capacitor CAP, and back to the input power Vin; the specific structure of the current conduction further includes the first chip base 11, the second lead frame 20, the conductive clip 4, and the ground pin 13. In some embodiments, the control chip 100, the first switch chip 2, and the second switch chip 3 together constitute a buck converter circuit.

[0110] As shown in Figure 5As shown, in some embodiments, the portion of the first chip base 11 that is not covered by the second lead frame 20, the second switch chip 3, and the conductive clip 4 includes a base exposed region 11a. Further, along the second direction Y, the portion of the first switch chip 2 that is not covered by the second lead frame 20, the second switch chip 3, and the conductive clip 4 includes a first chip exposed region 2a.

[0111] In summary, the chip stack structure of the present application can use two field effect transistors with a general architecture (e.g., the gate and source are on the same side, and the drain is on the opposite side) as the first switch chip and the second switch chip. The first switch chip can form a conductive path by the first chip base and the bottom of the second switch chip (e.g., conductive glue or tin paste, etc.). The second switch chip can form a conductive path by electrically connecting the first switch chip and the conductive clip of the first chip base. Since the first switch chip and the second switch chip are arranged in a stacked manner, compared with the prior art of placing two or more field effect transistors in a plane, the size of the area occupied by the modular elements on the circuit board can be saved, and the first switch chip and the second switch chip are arranged in a stacked manner, which eliminates the additional circuit for electrically connecting between the two or more field effect transistors, reduces the impedance between the first switch chip and the second switch chip, and thereby eliminates the inductive effect of the first switch chip and the second switch chip, improves the efficiency of conduction and heat conduction.

[0112] In some embodiments, compared with the technical problem of the prior art integrated circuit susceptible to electromagnetic radiation interference generated by the field effect transistor due to proximity to the voltage source, the chip stack structure of the present application can further consider arranging the control chip on the topmost conductive clip, which can further reduce the area of the chip stack structure, and can avoid the electromagnetic radiation interference generated by the field effect transistor when energized from affecting the operation of the control chip, but it is not limited thereto.

[0113] Therefore, compared with the prior art, the chip stack structure of the present application has a shorter conductive path, can eliminate the inductive effect, reduce the switching response time, and improve the heat dissipation effect, and achieves the purpose of meeting the miniaturization and high frequency application.

[0114] The above is only a detailed description of the preferred embodiments of the present application and the drawings, but the features of the present application are not limited thereto, and the scope of the present application should be subject to the claims below. Any person skilled in the art can easily think of changes or modifications within the scope of the present application, which are all included in the scope of the present application. Any changes or modifications within the scope of the present application are covered by the patent scope of the present application.

[0115] Of course, the present application can have other various embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present application without departing from the spirit and essence of the present application, and these corresponding changes and modifications shall all belong to the protection scope of the claims of the present application.

Claims

1. A chip stack structure, characterized by, The application relates to a semiconductor package, comprising: a first lead frame, comprising a first die pad, a second die pad and a ground pin, wherein the first die pad is coupled to an input power source, the second die pad is coupled to an output node, and the ground pin is coupled to a ground potential; a first switch die, comprising a first drain, a first source and a first gate, wherein the first drain is electrically connected to the first die pad; a second switch die, comprising a second drain, a second source and a second gate, wherein a first region of the second drain is electrically connected to the second die pad, and a second region of the second drain is electrically connected to the first source; a conductive clip, comprising a die end and a lead frame end, wherein the die end is electrically connected to the second source, and the lead frame end is electrically connected to the ground pin; and an input capacitor, having two ends coupled to the ground potential and the input power source, respectively. In a first direction, the second die pad extends beyond the periphery of the first die pad; in a second direction, the ground pin and the first die pad both extend beyond the periphery of the second die pad; the first direction and the second direction have a non-zero included angle. The portion of the ground pin not covered by the conductive clip comprises a pin exposed region; the portion of the first die pad not covered by the second switch die and the conductive clip comprises a die pad exposed region, and the two ends of the input capacitor are coupled to the pin exposed region and the die pad exposed region, respectively.

2. The chip stack structure of claim 1, wherein, In the second direction, the portion of the first switch die not covered by the second die pad, the second switch die and the conductive clip comprises a first switch die exposed region, and the first gate is located in the first switch die exposed region.

3. The chip stack structure of claim 1, wherein, In the first direction, the portion of the second switch die not covered by the conductive clip comprises a second switch die exposed region, and the second gate is located in the second switch die exposed region.

4. The chip stack structure of claim 1, wherein, The upper surface of the first die pad is lower than the upper surface of the second die pad by at least a gap height, and the gap height is greater than the thickness of the first switch die; when the first switch die is arranged on the first die pad, the upper surface of the first switch die is not higher than the upper surface of the second die pad.

5. The chip stack structure of claim 1, wherein, The application further comprises a first conductive layer and a second conductive layer; the first conductive layer is coated on the upper surface of the first switch die; the second conductive layer is coated on the upper surface of the second die pad; the upper surface of the first conductive layer is substantially aligned with the upper surface of the second conductive layer, and has substantially the same height, so that the lower surface of the second switch die is arranged substantially horizontally on the upper surface of the first conductive layer and the upper surface of the second conductive layer.

6. The chip stack structure of claim 1, wherein, The second die pad has an L-shaped two-branch structure, and the two-branch structure extends along the first direction and the second direction, respectively; the two-branch structure is adjacent to two peripheries of the first die pad, respectively.

7. The chip stack structure of claim 1, wherein, The conductive clip has an L-shaped two-branch structure, the two branches extend along a first direction and a third direction, the first direction, the second direction and the third direction have a non-zero included angle with each other, the lead frame end of the conductive clip extends along the third direction by at least a receiving interval, the chip end of the conductive clip extends along the first direction, and the receiving interval is greater than the thickness of the second switch chip, so that the second switch chip is received between the chip end of the conductive clip and the first chip base.

8. The chip stack structure of claim 1, wherein, Further comprising a control chip, the control chip comprises a first surface and a second surface opposite to each other; wherein the first surface is coupled to the chip end of the conductive clip and is arranged opposite to the second switch chip; the second surface comprises a plurality of contacts and can selectively electrically connect at least one of the conductive clip, the first gate and the second gate; the conductive clip is electrically connected to the ground pin, when the first switch chip and the second switch chip generate an electromagnetic radiation due to the change of on-off state, the conductive clip shields the electromagnetic radiation and reduces the intensity of the electromagnetic radiation reaching the control chip.

9. A chip stack structure, characterized by Comprise: a first lead frame comprising a first chip base, a second chip base and a ground pin; wherein the first chip base is coupled to an input power supply, the second chip base is coupled to an output node, and the ground pin is coupled to a ground potential; a first switch chip comprising a first drain, a first source and a first gate, the first drain is electrically connected to the first chip base; a second lead frame comprising a first conductive surface and a second conductive surface opposite to each other; wherein a first region of the first conductive surface corresponds to the second chip base, and a second region of the first conductive surface corresponds to the first source of the first switch chip, the second lead frame, the second chip base and the first source are electrically connected to each other; a second switch chip comprising a second drain, a second source and a second gate, the second drain is electrically connected to the second conductive surface of the second lead frame; a conductive clip comprising a chip end and a lead frame end, the chip end is electrically connected to the second source, and the lead frame end is electrically connected to the ground pin; and an input capacitor, two ends of the input capacitor are coupled to the ground potential and the input power supply respectively; wherein along a first direction, the second chip base extends beyond the periphery of the first chip base; along a second direction, the ground pin and the first chip base both extend beyond the periphery of the second chip base; the first direction and the second direction have a non-zero included angle; wherein the part of the ground pin not covered by the conductive clip comprises a pin exposed area; the part of the first chip base not covered by the second lead frame, the second switch chip and the conductive clip comprises a base exposed area, and two ends of the input capacitor are coupled to the pin exposed area and the base exposed area respectively.

10. The chip stack structure of claim 9, wherein, Along the second direction, the portion of the first switch chip not shielded by the second lead frame, the second switch chip and the conductive clip includes a first chip exposed area, and the first gate is located in the first chip exposed area.

11. The chip stack structure of claim 9, wherein, Along the first direction, the portion of the second switch chip not shielded by the conductive clip includes a second chip exposed area, and the second gate is located in the second chip exposed area.

12. The chip stack structure of claim 9, wherein, The upper surface of the first chip base is lower than the upper surface of the second chip base by at least a gap height, the gap height is greater than the thickness of the first switch chip, and when the first switch chip is disposed in the first chip base, the upper surface of the first switch chip is not higher than the upper surface of the second chip base.

13. The chip stack structure of claim 9, wherein, Further comprising a first conductive layer and a second conductive layer; wherein the first conductive layer is coated on the upper surface of the first switch chip; the second conductive layer is coated on the upper surface of the second chip base; the upper surface of the first conductive layer is substantially aligned with the upper surface of the second conductive layer, and has substantially the same height, so that the lower surface of the second lead frame is substantially horizontally disposed on the upper surface of the first conductive layer and the upper surface of the second conductive layer.

14. The chip stack structure of claim 9, wherein, The second chip base has a two-branch structure of L shape, and the two-branch structures extend along the first direction and the second direction respectively, and the two-branch structures are adjacent to the two peripheries of the first chip base respectively.

15. The chip stack structure of claim 9, wherein, The conductive clip has a two-branch structure of L shape, and the two-branch structures extend along the first direction and a third direction respectively, the first direction, the second direction and the third direction have a non-zero included angle with each other, the lead frame end of the conductive clip extends along the third direction by at least a containing interval, the chip end of the conductive clip extends along the first direction, the containing interval is greater than the thickness of the second switch chip, so that the second switch chip is contained between the chip end of the conductive clip and the first chip base.

16. The chip stack structure of claim 9, wherein, Further comprising a control chip, the control chip includes a first surface and a second surface opposite to each other; wherein the first surface is coupled to the chip end of the conductive clip and is disposed opposite to the second switch chip; the second surface includes a plurality of contacts and can selectively electrically connect at least one of the conductive clip, the first gate and the second gate; the conductive clip is electrically connected to the ground pin, when the first switch chip and the second switch chip generate an electromagnetic radiation due to the change of on-off state, the conductive clip shields the electromagnetic radiation and reduces the intensity of the electromagnetic radiation reaching the control chip.

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