A low-loss mosfet device and method of manufacturing the same

Abstract

The present application relates to a kind of low-loss power MOSFET device and its manufacturing method.The present application is provided with first conductive type epitaxial layer on the first conductive type substrate, longitudinal trench is provided in the first conductive type epitaxial layer, first gate and second gate are provided in longitudinal trench, second conductive type body region is provided on the surface of first conductive type epitaxial layer, second conductive type buried layer is provided below second conductive type body region, first conductive type source and second conductive type source are provided in second conductive type body region, first conductive type source and longitudinal trench are connected, in the direction of longitudinal extension of longitudinal trench, second conductive type body region is also provided with first conductive type drain adjacent to longitudinal trench.The low-loss power MOSFET device provided by the present application reduces the longitudinal leakage current of device, reduces the static power consumption of device, and improves the reliability of device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a low-loss power MOSFET device and a manufacturing method thereof. Background Art

[0002] Power MOSFET devices are generally divided into two types: lateral and vertical. Lateral power MOSFETs are easy to integrate and are generally used in BCD processes. They are suitable for implementing various functions in analog integrated circuits. Vertical power MOSFETs are generally used as standalone switching devices, with their voltage-resistant components located internally. Compared to lateral power MOSFETs of the same current level, their chip area can be significantly reduced. However, vertical power MOSFETs cannot be integrated with other devices, and therefore cannot implement various functions within the circuit.

[0003] With the demand for power devices with various complex functions, major manufacturers such as Infineon, Onsemi and TI have launched processes that integrate lateral power MOSFET devices and vertical power MOSFET devices. This process is particularly suitable for chips such as power MOSFET devices or smart load switches with protection and drive functions. The above chips realize the monolithic integration of analog circuits and vertical power devices, integrating various protection functions and drive functions with vertical power devices. When used in the system, there is no need for additional protection or drive chips, which greatly reduces the complexity of system design and improves system reliability.

[0004] For the above process, when the lateral power device is turned on, it will face the problem of current leakage from the surface of the device to the inside of the device, which will reduce the drain current of the lateral power device and the current will flow out from the substrate metal on the back (that is, the drain metal of the vertical power device), reducing the current capacity of the lateral power device, increasing the leakage of the vertical power device, and increasing the overall power consumption of the system. Summary of the Invention

[0005] The purpose of the present invention is to provide a low-loss power MOSFET device and a process method thereof, which can reduce the longitudinal leakage of the device, lower the static loss of the device, and improve the reliability of the device.

[0006] In order to achieve the above technical objectives, the technical solution of the present invention is: a low-loss power MOSFET device, including a substrate metal, a first conductive type substrate is provided on the substrate metal, a first conductive type epitaxial layer is provided on the first conductive type substrate, a longitudinal groove is provided in the first conductive type epitaxial layer, and a first gate and a second gate composed of polysilicon material are also provided in the longitudinal groove, the first gate is located at the upper part of the longitudinal groove, and the second gate is located at the lower part of the longitudinal groove, a second conductive type body region is also provided on the surface of the first conductive type epitaxial layer, a second conductive type buried layer is also provided below the second conductive type body region, and a heavily doped first conductive type source electrode is also provided on the surface of the second conductive type body region. and a second conductive type source, one side of the heavily doped first conductive type source is connected to the longitudinal groove, and the other side of the heavily doped first conductive type source is connected to the heavily doped second conductive type source, in the horizontal extension direction of the longitudinal groove, a first conductive type drain is also provided on the surface of the first conductive type epitaxial layer, the first conductive type drain is connected to the longitudinal groove, an insulating medium is also provided on the surface of the first conductive type epitaxial layer and the longitudinal groove, a source metal and a drain metal are also provided on the surface of the insulating medium, the source metal passes through the insulating medium and is connected to the heavily doped first conductive type source and the second conductive type source, and the drain metal passes through the insulating medium and is connected to the heavily doped first conductive type drain.

[0007] In one embodiment of the present invention, there is silicon dioxide isolation between the first gate and the second gate.

[0008] In one embodiment of the present invention, the longitudinal groove is made of silicon dioxide insulating material.

[0009] In one embodiment of the present invention, the concentration of the second conductive type buried layer is higher than the concentration of the second conductive type body region.

[0010] In one embodiment of the present invention, for an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0011] The present invention also provides a method for manufacturing a low-loss power MOSFET device, comprising the following steps:

[0012] Step 1: Select a first conductive type substrate material and epitaxially grow a first conductive type epitaxial layer on its surface;

[0013] Step 2: Using a mask window and high-energy implantation, second conductive type ions are implanted on the surface of the first conductive type epitaxial layer to form a second conductive type buried layer, and a longitudinal groove is selectively etched on the upper surface of the first conductive type epitaxial layer;

[0014] Step 3: growing an oxide layer composed of silicon dioxide in the longitudinal trench, and then filling the longitudinal trench with polysilicon to the surface of the first conductivity type epitaxial layer;

[0015] Step 4: removing the polysilicon on the surface of the first conductive type epitaxial layer, further etching the polysilicon in the longitudinal trench to form a second gate, and then depositing an oxide layer in the longitudinal trench to the surface of the first conductive type epitaxial layer;

[0016] Step 5: etching the oxide layer in the longitudinal trench, and then growing a gate oxide layer in the longitudinal trench to form a gate oxide layer of the first gate;

[0017] Step 6: Filling the longitudinal trench with polysilicon again to the surface of the first conductivity type epitaxial layer to form a first gate, and removing excess polysilicon;

[0018] Step seven: injecting second conductive type ions into the surface of the first conductive type epitaxial layer, forming a second conductive type body region through high temperature annealing, and using a mask window, respectively injecting high concentrations of first conductive type ions and second conductive type ions into the surface of the second conductive type body region, and forming a heavily doped first conductive type source, a first conductive type drain, and a second conductive type source after high temperature annealing.

[0019] Step 8: Deposit an insulating dielectric on the surface of the first conductive type epitaxial layer and the surface of the longitudinal groove, then selectively etch a through hole on the insulating dielectric, then deposit metal and selectively etch the metal to form source metal, gate metal and drain metal, and deposit metal under the first conductive type substrate to form substrate metal.

[0020] In one embodiment of the present invention, the second conductive type buried layer is formed by high energy ion implantation before forming the second conductive type body region; or is formed by high energy ion implantation after forming the second conductive type body region.

[0021] Compared with the prior art, the main advantage of the present invention is that when the device of the present invention is turned on and the substrate metal is connected to high voltage, the high-concentration second conductive type buried layer and the first conductive type epitaxial layer will not be completely depleted when they are depleted, thereby avoiding the current from flowing directly into the substrate metal through the depletion region, reducing device leakage and lowering the static loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings, wherein

[0023] Figure 1 This is a three-dimensional structural diagram of the device structure of the present invention after removing the insulating medium and surface metal.

[0024] Figure 2 This is a three-dimensional structural diagram of the device structure of the present invention.

[0025] Figure 3 A three-dimensional structure diagram that integrates traditional lateral power MOSFET devices and vertical power MOSFET devices and removes the insulating dielectric and surface metal.

[0026] Figure 4 A three-dimensional structure diagram that integrates the device structure of the present invention and a longitudinal power MOSFET device and removes the insulating medium and surface metal. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0030] The present invention will be further described below with reference to specific drawings and embodiments.

[0031] Example 1

[0032] A low-loss power MOSFET device, when the device is an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; when the device is a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type. This embodiment takes an N-type power semiconductor device as an example. Figure 1 and Figure 2 As shown, it includes a substrate metal 101, an N-type substrate 102 is provided on the substrate metal 101, an N-type epitaxial layer 103 is provided on the N-type substrate 102, a longitudinal groove 105 composed of a silicon dioxide insulating material is provided in the N-type epitaxial layer 103, a first gate 108 and a second gate 106 composed of a polysilicon material are further provided in the longitudinal groove 105, the first gate 108 is located at the upper part of the longitudinal groove 105, the second gate 106 is located at the lower part of the longitudinal groove 105, and the first gate 108 and the second gate 106 are isolated by silicon dioxide, a P-type body region 104 is further provided on the surface of the N-type epitaxial layer 103, a P-type buried layer 115 is further provided below the P-type body region 104, and a heavily doped N-type source 106 is further provided on the surface of the P-type body region 104. 9 and the P-type source 107, one side of the heavily doped N-type source 109 is connected to the longitudinal groove 105, and the other side of the heavily doped N-type source 109 is connected to the heavily doped P-type source 107, in the direction in which the longitudinal groove 105 extends horizontally, an N-type drain 110 is further provided on the surface of the N-type epitaxial layer 103, the N-type drain 110 is connected to the longitudinal groove 105, an insulating medium 113 is further provided on the surface of the N-type epitaxial layer 103 and the longitudinal groove 105, a source metal 111 and a drain metal 112 are further provided on the surface of the insulating medium 113, the source metal 111 passes through the insulating medium 113 and is connected to the heavily doped N-type source 109 and the P-type source 107, the drain metal 112 passes through the insulating medium 113 and is connected to the heavily doped N-type drain 110.

[0033] like Figure 3The figure shows a three-dimensional structure that integrates a lateral power MOSFET device and a vertical power MOSFET device, with the surface insulating dielectric and metal removed. 001 is a lateral power MOSFET device, namely the low-loss power MOSFET device provided by the present invention, and 002 is a vertical power MOSFET device. Several other devices may be interposed between lateral power MOSFET device 001 and vertical power MOSFET device 002. Reference numeral 101 represents the substrate metal for lateral power MOSFET device 001 and the drain metal for vertical power MOSFET device 002. When the vertical power MOSFET device is in the off state, its drain metal 101 is exposed to a high voltage. In this case, if lateral power MOSFET device 001 is turned on (i.e., the voltage on the first gate 108 exceeds the device threshold voltage), the source metal of the lateral power MOSFET device is connected to a low potential (typically ground), while the drain metal of the lateral power MOSFET device is connected to a positive voltage. The P-type body regions on both sides of the first gate are inverted to form N-type channels. Ideally, electron current flows from the N-type source 109 through the N-type channel to the N-type drain 110. However, since the substrate metal 101 (i.e., the drain metal of the vertical power MOSFET device) is connected to a high voltage, the P-type body region 104 will deplete the N-type epitaxial layer 103, and coupled with the influence of the positive voltage on the first gate 108, for a lower concentration (10 15 ~10 16 cm -3 For a P-type body region with a shallow depth (0.3um~0.5um) (on the order of magnitude), it is very easy to be completely depleted, causing the electron current to flow through the depletion region into the N-type substrate 102 and eventually out of the device through the substrate metal 101. This increases the leakage of the vertical power MOSFET device 002 when it is turned off, thereby increasing the overall power consumption of the chip. If this leakage continues to increase, the vertical power MOSFET device 002 will lose its shutdown function, thereby affecting the reliability of the entire system.

[0034] like Figure 4 As shown, for the low-loss power MOSFET device 001 provided by the present invention, a P-type buried layer 115 is further provided under the P-type body region. When the low-loss power MOSFET device 001 is turned on, the vertical power MOSFET device 002 is turned off, that is, the drain metal 101 (the substrate metal for the low-loss power MOSFET device 001) is connected to a high voltage. At this time, the P-type buried layer 115 will be depleted together with the N-type epitaxial layer 103. Since the concentration of the P-type buried layer is relatively high (10 17~ 10 18 cm -3The N-type epitaxial layer 103 is unable to completely deplete the P-type buried layer 115, so the current in the channel of the low-loss power MOSFET device 001 will not flow into the substrate metal 101 through the depletion region, thereby avoiding an increase in the leakage current of the substrate metal 101 and reducing the loss of the device of the present invention.

[0035] The P-type buried layer is located below the P-type body region. Its main purpose is to reduce its impact on the device's threshold voltage. If only the P-type body concentration is increased, even if the device can avoid leakage from the surface to the back substrate metal, it will greatly increase the device's threshold voltage.

[0036] The concentration of the P-type buried layer is higher than that of the P-type body region, which aims to prevent the P-type buried layer from being completely depleted by the N-type epitaxial layer and the first gate, so that the current directly passes through the depletion region to reach the substrate metal of the device.

[0037] The manufacturing method according to this embodiment includes the following steps:

[0038] Step 1: Select an N-type substrate 102 material and epitaxially grow an N-type epitaxial layer 103 on its surface;

[0039] Step 2: Using a mask window and high-energy implantation, P-type ions are implanted on the surface of the N-type epitaxial layer 103 to form a P-type buried layer, and a longitudinal trench 105 is selectively etched on the upper surface of the N-type epitaxial layer 103;

[0040] Step 3: growing an oxide layer made of silicon dioxide in the longitudinal trench 105 , and then filling the longitudinal trench 105 with polysilicon to the surface of the N-type epitaxial layer 103 ;

[0041] Step 4: removing the polysilicon on the surface of the N-type epitaxial layer 103, further etching the polysilicon in the longitudinal groove 105 to form a second gate 108, and then depositing an oxide layer in the longitudinal groove 105 to the surface of the N-type epitaxial layer 103;

[0042] Step 5: etching the oxide layer in the longitudinal trench 105 , and then growing a gate oxide layer in the longitudinal trench 105 to form a gate oxide layer of the first gate 108 ;

[0043] Step 6: Filling the longitudinal trench 105 with polysilicon again to the surface of the N-type epitaxial layer 103 to form a first gate 108 , and removing excess polysilicon;

[0044] Step 7: P-type ions are implanted on the surface of the N-type epitaxial layer 103, and a P-type body region 104 is formed by high-temperature annealing. High-concentration N-type ions and P-type ions are implanted on the surface of the P-type body region 104 using a mask window, and a heavily doped N-type source 109, an N-type drain 110, and a P-type source 107 are formed after high-temperature annealing.

[0045] Step 8: Deposit an insulating dielectric 113 on the surface of the N-type epitaxial layer 103 and the surface of the longitudinal groove 105, then selectively etch a through hole on the insulating dielectric 113, then deposit metal and selectively etch the metal to form a source metal 111, a gate metal and a drain metal 112, and deposit metal under the N-type substrate to form a substrate metal 101.

[0046] The manufacturing method proposed in this embodiment is fully compatible with the manufacturing process of the vertical power MOSFET device. In other words, the manufacturing process proposed in this embodiment can simultaneously realize the manufacturing of the low-loss power MOSFET device and the vertical power MOSFET device provided by the present invention.

[0047] Example 2

[0048] This embodiment provides another method for manufacturing a low-loss power MOSFET device, comprising the following steps:

[0049] Step 1: Select an N-type substrate 102 material and epitaxially grow an N-type epitaxial layer 103 on its surface;

[0050] Step 2: selectively etching a longitudinal groove 105 on the upper surface of the N-type epitaxial layer 103 using a mask window;

[0051] Step 3: growing an oxide layer made of silicon dioxide in the longitudinal trench 105 , and then filling the longitudinal trench 105 with polysilicon to the surface of the N-type epitaxial layer 103 ;

[0052] Step 4: removing the polysilicon on the surface of the N-type epitaxial layer 103, further etching the polysilicon in the longitudinal groove 105 to form a second gate 108, and then depositing an oxide layer in the longitudinal groove 105 to the surface of the N-type epitaxial layer 103;

[0053] Step 5: etching the oxide layer in the longitudinal trench 105 , and then growing a gate oxide layer in the longitudinal trench 105 to form a gate oxide layer of the first gate 108 ;

[0054] Step 6: Filling the longitudinal trench 105 with polysilicon again to the surface of the N-type epitaxial layer 103 to form a first gate 108 , and removing excess polysilicon;

[0055] Step seven: Using a mask window, with the aid of high-energy implantation, P-type ions are implanted into the surface of the N-type epitaxial layer 103. After removing the mask window, P-type ions are implanted into the surface of the N-type epitaxial layer 103 again. After high-temperature annealing, a P-type body region 104 and a P-type buried layer are formed simultaneously. Using the mask window again, high-concentration N-type ions and P-type ions are implanted into the surface of the P-type body region 104 respectively. After high-temperature annealing, heavily doped N-type source 109, N-type drain 110 and P-type source 107 are formed.

[0056] Step 8: Deposit an insulating dielectric 113 on the surface of the N-type epitaxial layer 103 and the surface of the longitudinal groove 105, then selectively etch a through hole on the insulating dielectric 113, then deposit metal and selectively etch the metal to form a source metal 111, a gate metal and a drain metal 112, and deposit metal under the N-type substrate to form a substrate metal 101.

[0057] In this embodiment, the P-type buried layer is formed by high-energy implantation before the P-type body region is formed, and undergoes the same long-term high-temperature annealing as the P-type body region. After annealing, the P-type buried layer diffuses deeper, which is beneficial for avoiding leakage. However, it may also increase the concentration on the surface of the P-type body region, thereby affecting the device threshold. If you want to further reduce the device threshold on this basis, you can also reduce the thickness of the gate oxide layer on both sides of the first gate, shorten the device channel length, and implant N-type ions on the device surface. In this embodiment, you can also form the P-type body region by first implanting, then forming the P-type buried layer by high-energy implantation, and finally undergoing annealing together.

[0058] Example 3

[0059] The P-type buried layer of this embodiment can be directly formed without undergoing a long-term annealing of the P-type body region. The difference from Embodiment 2 is that:

[0060] Step seven: P-type ions are implanted into the surface of the N-type epitaxial layer 103. After high-temperature annealing, a P-type body region 104 is formed. P-type ions are implanted into the surface of the N-type epitaxial layer 103 through a mask window with the aid of high-energy implantation. Then, high-concentration N-type ions and P-type ions are implanted into the surface of the P-type body region 104 through a new mask window. After high-temperature annealing, a P-type buried layer, a heavily doped N-type source 109, an N-type drain 110, and a P-type source 107 are formed.

[0061] The P-type buried layer of this embodiment does not undergo long-term high-temperature annealing to form a P-type body region, but only undergoes short-term low-temperature annealing to form a source, so that the P-type buried layer has basically no diffusion and its impact on the threshold voltage is minimal.

[0062] The above description of the present invention and its embodiments is non-limiting, and the actual structure is not limited thereto. In short, if a person skilled in the art is inspired by the above, and does not deviate from the purpose of the invention, without creatively designing a structure and embodiment similar to the technical solution, they shall fall within the scope of protection of the present invention.

Claims

1. A low-loss power MOSFET device, comprising a metal substrate, a first conductivity type substrate disposed on the metal substrate, a first conductivity type epitaxial layer disposed on the first conductivity type substrate, a longitudinal trench disposed in the first conductivity type epitaxial layer, a first gate and a second gate composed of polysilicon disposed in the longitudinal trench, the first gate being located above the longitudinal trench, the second gate being located below the longitudinal trench, and a second conductivity type body region disposed on a surface of the first conductivity type epitaxial layer; It is characterized by: A second conductive type buried layer is further provided below the second conductive type body region, and a heavily doped first conductive type source and a second conductive type source are further provided on the surface of the second conductive type body region, one side of the heavily doped first conductive type source is in contact with the longitudinal trench, and the other side of the heavily doped first conductive type source is in contact with the heavily doped second conductive type source, and a first conductive type drain is further provided on the surface of the first conductive type epitaxial layer in the direction in which the longitudinal trench extends horizontally, and the first conductive type drain is in contact with the longitudinal trench; The concentration of the second conductive type buried layer is higher than the concentration of the second conductive type body region.

2. A low-loss power MOSFET device according to claim 1, characterized in that: An insulating medium is further provided on the surface of the first conductive type epitaxial layer and the longitudinal groove, and a source metal and a drain metal are further provided on the surface of the insulating medium.

3. A low-loss power MOSFET device according to claim 2, characterized in that: The source metal passes through the insulating medium and is connected to the heavily doped first conductivity type source and the second conductivity type source. The drain metal passes through the insulating medium and is connected to the heavily doped first conductivity type drain.

4. A low-loss power MOSFET device according to claim 1, characterized in that: There is silicon dioxide isolation between the first gate and the second gate.

5. A low-loss power MOSFET device according to claim 1, characterized in that: The longitudinal groove is made of silicon dioxide insulating material.

6. A low-loss power MOSFET device according to any one of claims 1 to 5, characterized in that: For an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

7. A method for manufacturing a low-loss power MOSFET device, based on the low-loss power MOSFET device according to any one of claims 1 to 6, characterized in that: The steps include: Step 1: Select a first conductive type substrate material and epitaxially grow a first conductive type epitaxial layer on its surface; Step 2: Using a mask window and high-energy implantation, second conductive type ions are implanted on the surface of the first conductive type epitaxial layer to form a second conductive type buried layer, and a longitudinal groove is selectively etched on the upper surface of the first conductive type epitaxial layer; Step 3: growing an oxide layer composed of silicon dioxide in the longitudinal trench, and then filling the longitudinal trench with polysilicon to the surface of the first conductivity type epitaxial layer; Step 4: removing the polysilicon on the surface of the first conductive type epitaxial layer, further etching the polysilicon in the longitudinal trench to form a second gate, and then depositing an oxide layer in the longitudinal trench to the surface of the first conductive type epitaxial layer; Step 5: etching the oxide layer in the longitudinal trench, and then growing a gate oxide layer in the longitudinal trench to form a gate oxide layer of the first gate; Step 6: Filling the longitudinal trench with polysilicon again to the surface of the first conductivity type epitaxial layer to form a first gate, and removing excess polysilicon; Step 7: Implanting second conductivity type ions into the surface of the first conductivity type epitaxial layer, forming a second conductivity type body region through high temperature annealing, and using a mask window, respectively implanting high concentrations of first conductivity type ions and second conductivity type ions into the surface of the second conductivity type body region, forming a heavily doped first conductivity type source, a first conductivity type drain, and a second conductivity type source through high temperature annealing; Step 8: Deposit an insulating dielectric on the surface of the first conductive type epitaxial layer and the surface of the longitudinal groove, then selectively etch a through hole on the insulating dielectric, then deposit metal and selectively etch the metal to form source metal, gate metal and drain metal, and deposit metal under the first conductive type substrate to form substrate metal.

8. The method for manufacturing a low-loss power MOSFET device according to claim 7, wherein: The second conductive type buried layer is formed by high energy ion implantation before forming the second conductive type body region; or is formed by high energy ion implantation after forming the second conductive type body region.

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