Schottky barrier transistor and method of making the same

Abstract

The present disclosure provides a Schottky barrier transistor and a preparation method thereof. The Schottky barrier transistor comprises an SOI substrate, the SOI substrate comprising a silicon substrate, a buried oxygen layer and a silicon layer which are sequentially stacked; a channel region on the SOI substrate, the channel region comprising a SiGe layer on the silicon layer; a gate structure on the channel region; source-drain regions on both sides of the gate structure, the source-drain regions comprising a second metal silicide layer on both sides of the channel region and a third metal silicide layer on the second metal silicide layer, the second metal silicide layer being in the silicon layer, and the third metal silicide layer being on the second metal silicide layer and on both sides of the SiGe layer. The Schottky barrier transistor has a high mobility channel, thereby being capable of improving the on-state current of the device, and also being capable of reducing the off-state current of the transistor, thereby improving the current on-off ratio of the device.

Description

[0001] This application is a divisional application of the invention patent application with application number 201811436193.X and application date of November 28, 2018. The invention title of the original invention patent application is Schottky barrier transistor and its fabrication method. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more specifically, to a Schottky barrier transistor and a method for fabricating the same. Background Technology

[0003] As device gate lengths shrink to the nanoscale, Schottky source-drain transistors have become the most promising alternatives to doped source-drain transistors due to their numerous advantages, such as atomically abrupt junctions, low source-drain series resistance and contact resistance, and suitability for integrating high-k metal gates.

[0004] However, traditional Schottky barrier devices suffer from a low current on / off ratio because the source / channel Schottky barrier height is high in the on-state and the drain / channel Schottky barrier height is low in the off-state. Summary of the Invention

[0005] The main objective of this invention is to provide a Schottky barrier transistor and its fabrication method to solve the problem of low current on / off ratio in existing Schottky barrier devices.

[0006] To achieve the above objectives, according to one aspect of the present invention, a Schottky barrier transistor is provided, comprising a substrate and a gate structure located on the substrate. The Schottky barrier transistor further comprises: a channel region located on the substrate surface corresponding to the gate structure, the channel region comprising a first metal silicide layer; and source / drain regions comprising a second metal silicide layer and a third metal silicide layer located on both sides of the channel region, the second metal silicide layer being located in the substrate, the third metal silicide layer being located on the substrate surface corresponding to the second metal silicide layer, and the work function of the second metal silicide layer being less than the work function of the third metal silicide layer.

[0007] Furthermore, the Schottky barrier transistor is a PMOS transistor, and the raw material for forming the first metal silicide layer includes a first metal, preferably SiGe; the raw material for forming the second metal silicide layer includes a second metal with a work function of 2.0–4.3 eV, preferably HfSi. x ZrSi x LaSi x TiSi x EuSi x and GdSi xThe materials for forming the third metal silicide layer include the first metal and the third metal, wherein 1 ≤ x ≤ 2; the work function of the third metal is 4.3 to 5.65 eV, and preferably the third metal silicide layer is selected from Al2Si. x Ge y Co2Si x Ge y Ir2Si x Ge y Ni2Si x Ge y Pd2Si x Ge y Pt2Si x Ge y and Ti2Si x Ge y Any of the following, where 1≤x≤2 and 1≤y≤2.

[0008] Furthermore, the potential barrier between the first metal silicide layer and the third metal silicide layer is 0.5–1 eV.

[0009] Furthermore, the channel region also includes a cap layer disposed between the first metal silicide layer and the gate structure, preferably made of Si, and preferably having a thickness of 2 to 5 nm.

[0010] Furthermore, the substrate is an SOI substrate, which includes a silicon substrate, a buried oxide layer and a silicon layer stacked in sequence, a first metal silicide layer disposed on the surface of the silicon layer and a second metal silicide layer disposed in the silicon layer.

[0011] According to another aspect of the present invention, a method for fabricating a Schottky barrier transistor is provided, comprising the following steps: S1, providing a substrate, and sequentially forming a first metal silicide on the surface of the substrate and a gate structure on a portion of the surface of the first metal silicide, wherein the first metal silicide is formed using a material comprising a first metal, a second metal silicide layer is formed in the substrate on both sides of the corresponding gate structure, and a third metal silicide layer is formed in the first metal silicide on both sides of the corresponding gate structure, wherein the work function of the second metal silicide layer is less than the work function of the third metal silicide layer, the second metal silicide layer and the third metal silicide layer constitute the structure in the source-drain region of the Schottky barrier transistor, and the remaining first metal silicide constitutes the first metal silicide layer in the channel region of the Schottky barrier transistor.

[0012] Furthermore, the substrate is an SOI substrate, which includes a buried oxide layer and a silicon layer located on the surface of the buried oxide layer. The step of providing the substrate includes: oxidizing the silicon layer and removing the oxidation products to thin the silicon layer. Preferably, BOE etching is used to remove the oxidation products, and the thickness of the silicon layer is preferably 1 to 20 nm.

[0013] Further, after providing the substrate, step S1 includes the following steps: epitaxially forming a first metal silicide on the surface of the substrate, preferably epitaxially forming SiGe to form the first metal silicide; forming a gate on the first metal silicide and forming a sidewall covering the surface of the gate, wherein the gate and the sidewall constitute a gate structure, preferably the gate is a stacked structure composed of a high-k dielectric layer and a metal gate.

[0014] Furthermore, between the steps of forming the first metal silicide and forming the gate structure, step S1 further includes the following step: forming a cap layer on the surface of the first metal silicide, with the gate structure located on the surface of the cap layer. Preferably, the material for forming the cap layer is Si, and preferably, the thickness of the cap layer is 2 to 5 nm.

[0015] Further, the step of forming the second metal silicide layer includes: depositing a second metal material on the gate structure and the first metal silicide, preferably the work function of the second metal material is 2.0 to 4.3 eV, more preferably the second metal material is selected from any one of Hf, Zr, La, Ti, Eu and Gd; performing a first heat treatment on the second metal material to react with the second metal material on a portion of the substrate located on both sides of the gate structure, and removing the unreacted second metal material to obtain the second metal silicide layer, preferably the temperature of the first heat treatment is 250 to 400°C.

[0016] Furthermore, through a first heat treatment, a portion of the first metal silicide located on both sides of the gate structure reacts with the second metal material, and after removing the unreacted second metal material, a third metal silicide layer is obtained.

[0017] Further, the step of forming the third metal silicide layer includes: depositing a third metal material on the gate structure and the fourth metal silicide layer, preferably with a work function of 4.3 to 5.65 eV, more preferably selected from Al, Co, Ir, Ni, Pd, Pt and Tiy; performing a second heat treatment on the third metal material, so that a portion of the fourth metal silicide layer on both sides of the gate structure reacts with the third metal material, and obtaining the third metal silicide layer after removing the unreacted third metal material, preferably at a temperature of 400 to 700°C.

[0018] The present invention provides a Schottky barrier transistor with a high mobility channel, which can improve the on-state current of the device. The low Schottky barrier in the upper layer of the source-drain region can improve the on-state current of the transistor, while the high Schottky barrier in the lower layer can improve the immunity of the device to short-channel effects and reduce the off-state current of the transistor, thereby improving the current switching ratio of the device. Furthermore, the structure of the stacked silicide in the source-drain region is fully compatible with current CMOS processes. Attached Figure Description

[0019] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0020] Figure 1 A schematic cross-sectional view of a Schottky barrier transistor provided in an embodiment of this application is shown.

[0021] Figure 2 This paper shows a schematic diagram of the substrate cross-sectional structure after providing a substrate in the fabrication method of the Schottky barrier transistor provided in the embodiments of this application.

[0022] Figure 3 It shows that Figure 2 The diagram shows a cross-sectional structure of the substrate after the silicon layer has been thinned.

[0023] Figure 4 It shows in Figure 3 The diagram shows a cross-sectional structure of the substrate after the first metal silicide is epitaxially formed on the surface of the substrate.

[0024] Figure 5 It shows in Figure 4 A schematic diagram of the substrate cross-section structure after a gate structure is formed on the first metal silicide and a sidewall covering the surface of the gate structure is formed.

[0025] Figure 6 It shows in Figure 5 The diagram shows the gate structure and the cross-sectional structure of the substrate after the second metal material is deposited on the first metal silicide.

[0026] Figure 7 A schematic diagram of the cross-sectional structure of the substrate after obtaining the second metal silicide layer and the fourth metal silicide layer is shown.

[0027] Figure 8 It shows in Figure 7 The diagram shows the gate structure and the substrate cross-sectional structure after the third metal material is deposited on the fourth metal silicide layer.

[0028] Figure 9A schematic diagram of the substrate cross-sectional structure after obtaining the third metal silicide layer is shown.

[0029] The above figures include the following reference numerals:

[0030] 10. Substrate; 110. Buried oxide layer; 120. Silicon layer; 20′. First metal silicide; 20. First metal silicide layer; 30. Gate; 40. Sidewall; 50. Second metal material; 60. Second metal silicide layer; 70. Fourth metal silicide layer; 80. Third metal material; 90. Third metal silicide layer. Detailed Implementation

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] As described in the background section, traditional Schottky barrier devices suffer from a low current-to-once ratio due to the high Schottky barrier height of the source / channel in the on-state and the low Schottky barrier height of the drain / channel in the off-state. To address this problem, the inventors of this invention have proposed a Schottky barrier transistor, such as... Figure 1As shown, the Schottky barrier transistor includes a substrate 10 and a gate structure located on the substrate 10. The Schottky barrier transistor further includes: a channel region located on the surface of the substrate 10 corresponding to the gate structure, the channel region including a first metal silicide layer 20; and source / drain regions including a second metal silicide layer 60 and a third metal silicide layer 90 located on both sides of the channel region. The second metal silicide layer 60 is located in the substrate 10, and the third metal silicide layer 90 is located on the surface of the substrate 10 corresponding to the second metal silicide layer 60. The work function of the second metal silicide layer 60 is less than the work function of the third metal silicide layer 90.

[0035] The aforementioned Schottky barrier transistor has a high mobility channel, which can improve the on-state current of the device; the low Schottky barrier in the upper layer of the source-drain region can improve the on-state current of the transistor, while the high Schottky barrier in the lower layer can improve the device's immunity to short-channel effects and reduce the off-state current of the transistor, thereby improving the device's current switching ratio; furthermore, the structure of the stacked silicide in the source-drain region is fully compatible with current CMOS processes.

[0036] The Schottky barrier transistor described above can be a PMOS transistor or an NMOS transistor, and both PMOS and NMOS transistors can be applied in CMOS. The Schottky barrier transistor provided by this invention will be described in more detail below using a PMOS transistor as an example.

[0037] In the Schottky barrier transistor of the present invention, the raw material for forming the first metal silicide layer 20 may include a first metal with high mobility; and in order to ensure the high mobility of the channel, the first metal silicide layer 20 formed is preferably SiGe.

[0038] To ensure a low Schottky barrier is formed in the upper layer of the source / drain region, preferably, the raw material for forming the second metal silicide layer 60 includes a second metal with a work function of 2.0–4.3 eV; and to ensure a high Schottky barrier is formed in the lower layer of the source / drain region, preferably, the raw material for forming the third metal silicide layer 90 includes a first metal and a third metal with a work function of 4.3–5.65 eV. More preferably, the barrier between the first metal silicide layer 20 and the third metal silicide layer 90 is 0.5–1 eV.

[0039] Preferably, the second metal silicide layer 60HfSi x ZrSi x LaSi x TiSi x EuSi x and GdSi x Any of the following, where 1 ≤ x ≤ 2; the third metal silicide layer 90 is selected from Al2Si. x Gey Co2Si x Ge y Ir2Si x Ge y Ni2Si x Ge y Pd2Si x Ge y Pt2Si x Ge y and Ti2Si x Ge y Any one of the above-mentioned preferred types, wherein 1≤x≤2 and 1≤y≤2. However, it is not limited to the above-mentioned preferred types, and those skilled in the art can reasonably select the second metal and the third metal that satisfy the above-mentioned work function based on the existing technology.

[0040] In the Schottky barrier transistor of the present invention, as shown above... Figure 1 As shown, the gate structure may include a gate 30 and a sidewall 40 surrounding the gate 30. The gate 30 may be a stacked structure composed of a high-k dielectric layer and a metal gate. To avoid interface degradation between the high-k dielectric layer and the first metal silicide layer 20, preferably, the channel region further includes a cap layer (not shown in the figure) disposed between the first metal silicide layer 20 and the gate structure. More preferably, the material forming the cap layer is Si; more preferably, the thickness of the cap layer is 2-5 nm.

[0041] In the Schottky barrier transistor of the present invention, the substrate 10 can be one of a silicon substrate, a germanium substrate, a gallium nitride substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator substrate. Preferably, the substrate 10 is an SOI substrate, which includes a silicon substrate, a buried oxide layer 110, and a silicon layer 120 stacked sequentially, such as... Figure 1 As shown, the first metal silicide layer 20 is disposed on the surface of the silicon layer 120, and the second metal silicide layer 60 is disposed in the silicon layer 120.

[0042] According to another aspect of the present invention, a method for fabricating a Schottky barrier transistor is also provided, such as... Figures 2 to 9As shown, the method includes the following steps: S1, providing a substrate 10, and sequentially forming a first metal silicide 20′ on the surface of the substrate 10 and a gate structure on a portion of the surface of the first metal silicide 20′, wherein the first metal silicide 20′ is formed using a material including a first metal; S2, forming a second metal silicide layer 60 in the substrate 10 on both sides of the corresponding gate structure, and forming a third metal silicide layer 90 in the first metal silicide 20′ on both sides of the corresponding gate structure, wherein the work function of the second metal silicide layer 60 is less than the work function of the third metal silicide layer 90, the second metal silicide layer 60 and the third metal silicide layer 90 constitute the structure in the source / drain region, and the remaining first metal silicide 20′ constitutes the first metal silicide layer 20 in the channel region.

[0043] The Schottky barrier transistors fabricated using the above method have high mobility channels, which can improve the on-state current of the device. The low Schottky barrier in the upper layer of the source-drain region can improve the on-state current of the transistor, while the high Schottky barrier in the lower layer can improve the device's immunity to short-channel effects and reduce the off-state current of the transistor, thereby improving the device's current on / off ratio. Furthermore, the structure of the stacked silicides in the source-drain region is fully compatible with current CMOS processes.

[0044] Exemplary embodiments of the method for fabricating a Schottky barrier transistor according to the present invention will now be described in more detail. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0045] First, step S1 is performed: a substrate 10 is provided, and a first metal silicide 20' is sequentially formed on the surface of the substrate 10, and a gate structure is formed on a portion of the surface of the first metal silicide 20'. The first metal silicide 20' is formed using a material comprising a first metal, such as... Figures 2 to 5 As shown.

[0046] The substrate 10 mentioned above can be an SOI substrate, such as... Figure 2 As shown, the SOI substrate includes a buried oxide layer 110 and a silicon layer 120 located on the surface of the buried oxide layer 110. Preferably, the step of providing the substrate 10 includes: oxidizing the silicon layer 120 and removing the oxidation products to thin the silicon layer 120, such as... Figure 3 As shown. More preferably, BOE etching is used to remove the above-mentioned oxidation products; more preferably, the thickness of the above-mentioned silicon layer 120 is 1 to 20 nm.

[0047] In a preferred embodiment, after providing the substrate 10, step S1 includes the following steps: epitaxially forming a first metal silicide 20' on the surface of the substrate 10, such as... Figure 4 As shown; a gate 30 is formed on the first metal silicide 20′, and a sidewall 40 is formed covering the surface of the gate 30. The gate 30 and the sidewall 40 constitute the gate structure described above, as follows. Figure 5 As shown.

[0048] In the preferred embodiment described above, to ensure high channel mobility, it is more preferably that SiGe is epitaxially grown to form a first metal silicide 20′. Furthermore, it is more preferably that the gate 30 is a stacked structure composed of a high-k dielectric layer and a metal gate.

[0049] When the gate 30 is a stacked structure composed of a high-k dielectric layer and a metal gate, to avoid interface degradation between the high-k dielectric layer and the first metal silicide layer 20, more preferably, the channel region further includes a cap layer (not shown in the figure) disposed between the first metal silicide layer 20 and the gate structure. More preferably, the material forming the cap layer is Si; more preferably, the thickness of the cap layer is 2-5 nm.

[0050] After completing step S1, step S2 is executed: a second metal silicide layer 60 is formed in the substrate 10 on both sides of the corresponding gate structure, and a third metal silicide layer 90 is formed in the first metal silicide 20′ on both sides of the corresponding gate structure, wherein the work function of the second metal silicide layer 60 is less than the work function of the third metal silicide layer 90, such as... Figures 6 to 9 As shown.

[0051] The step of forming the second metal silicide layer 60 may include: depositing a second metal material 50 on the gate structure and the first metal silicide 20′, such as... Figure 6 As shown; the second metal material 50 undergoes a first heat treatment to react the portions of the substrate 10 located on both sides of the gate structure with the second metal material 50, and the unreacted second metal material 50 is removed to obtain the second metal silicide layer 60, as shown. Figure 7 As shown.

[0052] To ensure the formation of a high Schottky barrier in the lower layers of the source / drain region, preferably, the work function of the second metal material 50 is 4.3–5.65 eV; more preferably, the second metal material 50 is selected from Al, Co, Ir, Ni, Pd, Pt, and Ti. y The material can be any of the above-mentioned preferred types, but is not limited to them. Those skilled in the art can reasonably select the second metallic material 50 that satisfies the above-mentioned work function based on existing technology. Furthermore, preferably, the temperature of the first heat treatment is 250–400°C.

[0053] In a preferred embodiment, a first heat treatment is performed to react a portion of the first metal silicide 20′ located on both sides of the gate structure with the second metal material 50. After removing the unreacted second metal material 50, a third metal silicide layer 90 is obtained. Figure 9 As shown.

[0054] In another preferred embodiment, a first heat treatment is performed to react a portion of the first metal silicide layer 20 located on both sides of the gate structure with the second metal material 50. After removing the unreacted second metal material 50, a fourth metal silicide layer 70 is obtained. The step of forming the third metal silicide layer 90 includes: depositing and forming a third metal material 80 on the gate structure and the fourth metal silicide layer 70, such as... Figure 8 As shown; the third metal material 80 undergoes a second heat treatment to react the portion of the fourth metal silicide layer 70 located on both sides of the gate structure with the third metal material 80. After removing the unreacted third metal material 80, a third metal silicide layer 90 is obtained, as shown. Figure 9 As shown.

[0055] To ensure the formation of a low Schottky barrier in the upper layer of the source / drain region, preferably, the work function of the third metal material 80 is 2.0–4.3 eV; more preferably, the third metal material 80 is selected from any one of Hf, Zr, La, Ti, Eu, and Gd. However, it is not limited to the above-mentioned preferred types, and those skilled in the art can reasonably select the third metal material 80 that satisfies the above work function based on existing technology. Furthermore, preferably, the temperature of the second heat treatment is 400–700°C.

[0056] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0057] The aforementioned Schottky barrier transistor has a high mobility channel, which can improve the on-state current of the device; the low Schottky barrier in the upper layer of the source-drain region can improve the on-state current of the transistor, while the high Schottky barrier in the lower layer can improve the device's immunity to short-channel effects and reduce the off-state current of the transistor, thereby improving the device's current switching ratio; furthermore, the structure of the stacked silicide in the source-drain region is fully compatible with current CMOS processes.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Schottky barrier transistor, comprising: SOI substrate, the SOI substrate comprising a silicon substrate, a buried oxide layer and a silicon layer stacked in sequence; A channel region located on the SOI substrate, the channel region including a SiGe layer located on the silicon layer; Gate structure located on the channel region; The source and drain regions are located on both sides of the gate structure. The source and drain regions include a second metal silicide layer and a third metal silicide layer located on both sides of the channel region. The second metal silicide layer is located in the silicon layer, and the third metal silicide layer is located on the second metal silicide layer and on both sides of the SiGe layer. The interface between the SiGe layer and the silicon layer is flush with the interface between the third metal silicide and the second metal silicide. The work function of the second metal silicide layer is less than the work function of the third metal silicide layer; The third metal silicide layer is formed of SiGe located on the silicon layer, and the SiGe forming the third metal silicide and the SiGe layer in the channel region come from the same SiGe material layer; The potential barrier between the SiGe layer and the third metal silicide layer is 0.5~1eV.

2. The Schottky barrier transistor according to claim 1, wherein, The Schottky barrier transistor is a PMOS transistor. The material forming the second metal silicide layer includes a second metal with a work function of 2.0~4.3 eV. The second metal silicide layer is selected from HfSi. x ZrSi x LaSi x TiSi x EuSi x and GdSi x Any one of the following, where 1≤x≤2.

3. The Schottky barrier transistor according to claim 1, wherein, The Schottky barrier transistor is a PMOS transistor. The material forming the third metal silicide layer includes Ge and a third metal, the work function of which is 4.3~5.65 eV. The third metal silicide layer is selected from Al2Si. x Ge y Co2Si x Ge y Ir2Si x Ge y Ni2Si x Ge y Pd2Si x Ge y Pt2Si x Ge y and Ti2Si x Ge y Any of the following, where 1≤x≤2 and 1≤y≤2.

4. The Schottky barrier transistor according to any one of claims 1 to 3, wherein, The channel region further includes a cap layer disposed between the SiGe layer and the gate structure, wherein the material forming the cap layer is Si, and the thickness of the cap layer is 2~5nm.

5. A method for fabricating a Schottky barrier transistor, comprising the following steps: An SOI substrate is provided, the SOI substrate comprising a silicon substrate, a buried oxide layer and a silicon layer stacked in sequence; A SiGe material layer is formed on the silicon layer; A gate structure is formed on the SiGe material layer; A second metal silicide layer is formed in the silicon layers on both sides of the gate structure; A third metal silicide layer is formed in the SiGe material layers on both sides of the gate structure; The work function of the second metal silicide layer is less than the work function of the third metal silicide layer; The potential barrier between the SiGe material layer and the third metal silicide layer is 0.5~1eV; The step of forming the second metal silicide layer includes: depositing a second metal material on the gate structure and the SiGe material layer, performing a first heat treatment on the second metal material to react the portion of the silicon layer located on both sides of the gate structure with the second metal material, and removing the unreacted second metal material to obtain the second metal silicide layer; The first heat treatment causes a portion of the SiGe material layer located on both sides of the gate structure to react with the second metal material. After removing the unreacted second metal material, the third metal silicide layer is obtained. The interface between the SiGe layer and the silicon layer is aligned with the interface between the third metal silicide and the second metal silicide.

6. The preparation method according to claim 5, wherein, Between the steps of forming the SiGe material layer and forming the gate structure, the following steps are also included: A cap layer is formed on the surface of the SiGe material layer, and the gate structure is located on the surface of the cap layer. The material forming the cap layer is Si, and the thickness of the cap layer is 2~5nm.

7. The preparation method according to claim 5, wherein, The work function of the second metallic material is 2.0~4.3eV, and the second metallic material is selected from any one of Hf, Zr, La, Ti, Eu and Gd.

8. The preparation method according to claim 5, wherein, The temperature of the first heat treatment is 250~400℃.

9. The preparation method according to any one of claims 5 to 8, wherein, The first heat treatment causes a portion of the SiGe material layer located on both sides of the gate structure to react with the second metal material. After removing the unreacted second metal material, a fourth metal silicide layer is obtained. A third metal material is deposited on the gate structure and the fourth metal silicide layer. The work function of the third metal material is 4.3~5.65eV, and the third metal material is selected from any one of Al, Co, Ir, Ni, Pd, Pt and Tiy. The third metal material is subjected to a second heat treatment to react the portion of the fourth metal silicide layer located on both sides of the gate structure with the third metal material. After removing the unreacted third metal material, the third metal silicide layer is obtained.

10. The preparation method according to claim 9, wherein, The temperature of the second heat treatment is 400~700℃.

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