Fan-out package structure and packaging method for a MEMS sensor chip and an ASIC chip

Abstract

The present invention discloses a fan-out package structure and a packaging method for a MEMS sensor chip and an ASIC chip, which are composed of a MEMS sensor chip, an ASIC chip and an interposer substrate. There is a cavity on the interposer substrate, and the ASIC chip is adhered in the cavity. The lead bonding area of the ASIC chip forms a fan-out bonding area through a redistribution process. Solder balls are printed on the bonding area to be soldered to the MEMS sensor chip or electrically connected to an external substrate. Through holes are formed on the interposer substrate to lead out the signals of the ASIC chip to the other side of the interposer substrate, and a wire bonding area is processed on the other side to be electrically connected to the external substrate or connected to the MEMS sensor chip through a ball-planting process of flip-chip bonding. Stress isolation grooves are provided on the interposer substrate for isolation, so as to avoid stress problems caused by thermal mismatch. This structure is applicable to the packaging of combinations of MEMS sensor chips and ASIC chips with different sizes and thicknesses, improves the processing flexibility, reduces the processing complexity and difficulty, can effectively reduce costs and is used for mass production.

Description

Technical Field

[0001] The present invention belongs to the field of MEMS chip packaging, and particularly relates to a fan-out packaging structure and method for a MEMS sensor chip and an ASIC chip (application-specific integrated circuit). Background Art

[0002] MEMS (Micro-Electro-Mechanical Systems) is the abbreviation of micro-electromechanical systems. MEMS manufacturing technology uses microfabrication technology, especially semiconductor wafer manufacturing technology, to manufacture various micro-mechanical structures, and combines with application-specific integrated circuits (ASICs) to form intelligent micro-sensors, micro-actuators, micro-optical devices and other MEMS components. MEMS components have the advantages of small size, low cost, high reliability, strong resistance to harsh environments, low power consumption, high intelligence, easy calibration and easy integration, and are widely used in consumer electronic products represented by smart phones. Taking smart phones as an example, it uses MEMS components such as gyroscopes, accelerometers, altimeters, microphones, electronic compasses, tuned antennas, and filters. With the increasingly fierce competition in the MEMS component market and the significant growth of wearable electronic products represented by smart watches, customers have higher and higher requirements for MEMS components. Small size, low power consumption and stable performance have become basic requirements. To further reduce the volume of MEMS system chips and lower costs, wafer-level packaging of sensor chips and application-specific integrated circuit chips has become an inevitable trend.

[0003] The fabrication of smaller semiconductor devices relies on achieving improvements in the horizontal and vertical electrical interconnections (3-D device integration) between multiple semiconductor devices at multiple levels. Horizontal electrical interconnections include redistribution layers (RDLs) formed as part of a fan-out wafer-level chip scale package (fo-WLCSP) or an embedded wafer-level ball grid array (eWLB), which provide electrical connections between semiconductor dies and points external to the package. Vertical interconnections are achieved using conductive through-silicon vias (TSVs) or through-hole vias (THVs). However, typically, the use of TSVs and THVs involves considerable time and devices, which reduces the units per hour (UPH) production and increases costs. The RDL serves as an intermediate layer for electrical interconnections within a package that includes electrical interconnections with package input / output (I / O) pads, and the package input / output (I / O) pads provide electrical connections from semiconductor dies within the semiconductor package to points outside the semiconductor package. The RDL can be formed on both the front and back surfaces of a semiconductor die within a semiconductor package and has thin wafer and panel processing capabilities. However, forming multiple RDLs on the front and back surfaces of a semiconductor die may require temporary bonding with a custom bonding material (which may require higher heat resistance) and can be a slow and expensive method for electrical interconnections for semiconductor packages, resulting in higher manufacturing costs. Additionally, the thin stack of RDLs includes structural limitations and reduced design flexibility. For example, the RDL provides limited mechanical strength and reliability for package handling. The RDL lacks modularity and is difficult to form in specific areas of a semiconductor package.

[0004] Currently, there are two common wafer-level packaging methods for MEMS sensor chips and application-specific integrated circuit (ASIC) chips: One is to bond the MEMS wafer and the dedicated circuit wafer by soldering or other means and then cut them. For example, in patent CN1789110B, the MEMS wafer and the application-specific integrated circuit (ASIC) wafer are bonded by solder pillars and then cut after bonding; in patent CN101939663B, the application-specific integrated circuit wafer and the MEMS structure are eutectically bonded to form a wafer-level package. Whether the MEMS sensor wafer and the application-specific integrated circuit (ASIC) wafer are directly wafer-bonded by soldering or eutectic bonding, during the bonding process, due to thermal mismatch, large stresses will be generated, which will have a significant impact on the performance of MEMS sensors, such as structures that are sensitive to stress, like gyroscopes, accelerometers, and pressure gauges.

[0005] Another packaging method is to cut the sensor wafer into chips, solder one or more MEMS sensor chips to one side of the application-specific integrated circuit (ASIC) wafer. Through-silicon vias are fabricated in the integrated circuit wafer. For example, Patent CN104603945B discloses the fabrication of through-silicon vias (TSVs) in an ASIC. The MEMS chip is connected to one side of the ASIC through the TSVs. The TSVs on the other side of the ASIC are connected to the signal leads of the ASIC and solder balls are implanted to achieve electrical connection with the outside world. In Patent CN103221333A, the MEMS sensor chip and the circuit control chip are integrated by bonding metal. Through-silicon vias are fabricated in the circuit control chip and led out to the other side of the circuit control chip, which is processed into a wire bonding area and solder balls are implanted. Both of the above two patents require the fabrication of through-silicon vias (TSVs) in the circuit chip. Through the through-silicon vias (TSVs), the signal of the MEMS chip on one side is led out and interconnected with the circuit chip and the external circuit on the other side of the circuit chip. The through-silicon vias require deep trench silicon etching and via filling. This processing process is completely incompatible with the CMOS process and requires a large amount of chip area. Moreover, the through-silicon vias will introduce stress, resulting in low performance of the circuit chip. Therefore, this method has a low cost performance and is not suitable for mass-produced products.

[0006] Patent CN205984951U discloses a double-sided fan-out structure. A cavity is opened on a silicon wafer, and the chip is glued into the cavity by a die attach adhesive. The lead-out area on the front side of the chip is led out through metal and solder balls are implanted in the lead-out area. Holes are opened on the other side of the wafer to expose the metal leads on the other side of the chip, and solder balls are fabricated. This fan-out process is suitable for thin chips. Since the thickness of MEMS chips is usually 500 - 1000 μm, opening deep trenches on the silicon wafer will cause the wafer to warp and make further processing impossible.

[0007] Patent US20210143131A1 provides a Package-on-Package (PoP) packaging method. The MEMS chip and the application-specific integrated circuit are packaged separately, and then soldered through the solder balls of the application-specific integrated circuit package and the metal leads of the MEMS chip package to achieve the stacking of two different packages. Among them, the application-specific integrated circuit is packaged in the encapsulant. Through a multi-layer process of a dielectric layer and a metal layer, the electrical signal is led out through the solder balls and connected to the carrier board. The electrical signal is led out from one side of the package to the other side through metal leads, and solder balls are fabricated. The MEMS chip is connected to the solder joints by wire bonding, and the pads are led out through leads and the lead areas are processed. This method requires taking into account the requirements of two different processes by separately packaging and integrating the two chips, with a large process difficulty and difficult operation. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to overcome the deficiencies existing in the prior art and provide a fan-out packaging structure for a MEMS sensor chip and an ASIC chip. The MEMS sensor chip and the ASIC chip are respectively welded or bonded to an interposer substrate to achieve wafer-level chip scale packaging. The MEMS sensor chip is welded on the surface of the interposer layer, and a stress isolation structure is processed on the interposer layer to isolate the influence of stress on the MEMS sensor chip and improve the product performance.

[0009] To solve the above technical problem, the present invention provides a fan-out packaging structure for a MEMS sensor chip and an ASIC chip, which consists of an interposer substrate, a MEMS sensor chip and an ASIC chip. There is a cavity on the front surface of the interposer substrate, and the ASIC chip is glued in the cavity through a die attach adhesive; a first dielectric layer is fabricated on the front surface of the interposer substrate, a dry film is pressed on the ASIC chip and the first dielectric layer, and openings are made in the dry film at the wire bonding areas corresponding to the ASIC chip to expose the wire bonding areas of the ASIC chip. A seed layer is sputtered on the wire bonding areas of the ASIC chip and metal is electroplated on the seed layer to form metal wires. A first RDL layer is coated on the dry film and patterned to lead out the metal wires, and the metal wires are connected to the first solder balls;

[0010] There are vias on the interposer substrate, and the vias are filled with a conductive material. There is an insulating layer between the conductive material and the inner wall of the vias to form conductive vias. There is a lead-out area on the conductive vias, and the signals of the conductive vias are led out to the front surface of the interposer substrate through the lead-out area and the metal wires;

[0011] A second dielectric layer is deposited on the back surface of the interposer substrate, openings are made in the areas corresponding to the conductive vias on the second dielectric layer and metal is sputtered to form metal bonding areas. A second RDL layer is coated on the back surface of the second dielectric layer and patterned to expose the metal bonding areas, and the metal bonding areas are connected to the second solder balls;

[0012] The MEMS sensor chip is bonded to the front surface of the interposer substrate through the first solder balls or bonded to the back surface of the interposer substrate through the second solder balls.

[0013] Through the fan-out packaging structure, the present invention welds and bonds the MEMS sensor chip and the ASIC chip to the interposer substrate respectively to achieve wafer-level chip scale packaging. Since the MEMS sensor chip is sensitive to stress, the sensor chip is welded on the surface (front or back) of the interposer substrate, and a stress isolation structure is processed on the interposer substrate, thus avoiding stress problems caused by thermal mismatch. This structure is applicable to MEMS sensor chips and ASIC chips of different sizes and thicknesses, improves the flexibility of processing, reduces the complexity and difficulty of processing, can effectively reduce costs and is used for mass production. The stress isolation structure can isolate the influence of stress on the MEMS sensor chip and improve the yield and performance of the product.

[0014] The intermediate substrate is selected as a silicon wafer because the thermal expansion coefficient of the silicon wafer is consistent with that of the ASIC and MEMS sensor chips. Slots are formed in the silicon wafer to create cavities, and the ASIC chip is installed in the form of die bonding. The redistribution process (RDL) is used to rearrange the lead-out areas of the ASIC chip, and this rearrangement can achieve direct connection to the outside or connection to the MEMS sensor chip. Through-silicon vias (TSVs) are formed in the silicon wafer to lead out electrical signals from one side of the silicon wafer to the other side, realizing direct electrical connection to the outside or connection to the MEMS sensor chip. In this way, one side of the silicon wafer is electrically connected to the outside, and the other side is connected to the MEMS sensor chip. Stress isolation grooves are processed beside the through-silicon vias on the side of the silicon wafer where it is in contact with the MEMS sensor chip. The width of the stress isolation grooves ranges from several micrometers to dozens of micrometers, and the depth ranges from several micrometers to hundreds of micrometers. Through the stress isolation grooves, the stress of the silicon wafer can be isolated from the stress of the MEMS sensor chip, effectively reducing the stress caused by thermal mismatch.

[0015] The MEMS sensor mentioned above is a measurement method that does not contact the external environment, such as an accelerometer, gyroscope, image sensor, etc. It can also be a measurement method that contacts the external environment, such as a pressure sensor, flow sensor, microphone, etc. Solder balls are printed on the lead contact area of the MEMS sensor for welding with the silicon wafer.

[0016] The ASIC chip is thinned to a certain thickness, glued in the cavity of the silicon wafer by die bonding adhesive, and the signals are led out to the surface of the silicon wafer through electroplated copper wires.

[0017] To solve the above technical problems, the present invention also provides a fan-out packaging method for MEMS sensor chips and ASCI chips, including the following steps:

[0018] (1) Coating a mask on the front side of the dielectric wafer and etching deep grooves;

[0019] (2) Growing an insulating layer on the inner wall of the deep grooves, depositing a conductive material on the insulating layer to fill the deep grooves, forming conductive grooves, removing the mask and grinding the surface flat;

[0020] (3) Depositing a first dielectric layer on the front side of the dielectric wafer and patterning it to expose the conductive grooves;

[0021] (4) Depositing a metal on the first dielectric layer and patterning it to form a lead-out area;

[0022] (5) Etching the first dielectric layer and the dielectric wafer to form a cavity;

[0023] (6) Gluing the ASIC chip in the cavity by die bonding adhesive;

[0024] (7) Stick a dry film on the ASIC chip and the first dielectric layer, and open holes at the corresponding positions of the lead-out area and the wire bonding area of the ASIC chip to expose the lead-out area and the wire bonding area;

[0025] (8) Deposit metal as a seed layer, apply glue and pattern it according to the circuit layout pattern, and then electroplate metal to form metal wires;

[0026] (9) Coat the dry film with a first RDL layer and pattern the first RDL layer to lead out the metal wires;

[0027] (10) Thinning the dielectric wafer from the back to expose the conductive grooves to become conductive vias;

[0028] (11) Deposit a second dielectric layer on the back of the dielectric wafer, and open holes to expose the conductive vias. Deposit metal and pattern it at the conductive vias to form metal bonding areas;

[0029] (12) Fabricate a second RDL layer on the back of the second dielectric layer, and open holes to expose the metal bonding areas;

[0030] (13) Plant second solder balls on the wire bonding area of the MEMS sensor wafer and cut it into MEMS sensor chips;

[0031] (14) Weld the MEMS sensor chips to the metal bonding areas or metal wires through the second solder balls;

[0032] (15) Cut the fabricated wafer into single chips.

[0033] When the MEMS sensor chips are welded to the metal bonding areas, in step (11), open holes on the second dielectric layer and fabricate stress isolation grooves on the back of the dielectric wafer.

[0034] When the MEMS sensor chips are welded to the metal wires, in step (9), open holes on the first RDL layer and fabricate stress isolation grooves on the front of the dielectric wafer.

[0035] The fan-out packaging method of the MEMS sensor chips and ASIC chips of the present invention welds and bonds the MEMS sensor chips and ASIC chips to the interposer substrate respectively to achieve wafer-level chip scale packaging. Since the MEMS sensor chips are relatively sensitive to stress, the sensor chips are welded to the surface (front or back) of the interposer substrate, and a stress isolation structure is processed on the interposer substrate, thereby avoiding stress problems caused by thermal mismatch. This method is applicable to MEMS sensor chips and ASIC chips of different sizes and thicknesses, can improve the processing flexibility, reduce the processing complexity and difficulty, can effectively reduce the cost and be used for mass production. The stress isolation structure can isolate the influence of stress on the MEMS sensor chips and improve the yield and performance of the products. Description of the Drawings

[0036] Figure 1 It is a schematic diagram of the fan-out package structure of the MEMS sensor chip and the ASIC chip in the first embodiment.

[0037] Figure 2 — Figure 16 It is a flowchart of the fan-out package method for the MEMS sensor chip and the ASIC chip in the first embodiment.

[0038] Figure 17 It is a schematic diagram of the fan-out package structure of the MEMS sensor chip and the ASIC chip in the second embodiment.

[0039] Figure 18 — Figure 26 It is a flowchart of the fan-out package method for the MEMS sensor chip and the ASIC chip in the second embodiment.

[0040] Figure 27 It is a schematic diagram of the stress isolation groove. Specific implementation manners

[0041] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0042] First embodiment

[0043] A fan-out package structure of a MEMS sensor chip and an ASIC chip, as Figure 1 shown, is composed of a silicon wafer 111, a MEMS sensor chip 300, and an ASIC chip 200. There is a cavity 106 on the front side of the silicon wafer 111. The ASIC chip 200 is adhered to the cavity 106 through a die attach adhesive 201. A first dielectric layer 104 is fabricated on the front side of the silicon wafer 111. A dry film 107 is pressed on the ASIC chip 200 and the first dielectric layer 104. An opening is made in the dry film 107 corresponding to the wire bonding area 202 of the ASIC chip 200 to expose the wire bonding area 202 of the ASIC chip 200. A seed layer is sputtered on the wire bonding area 202 of the ASIC chip 200 and copper is electroplated on the seed layer to form a copper wire 109. A polyimide is coated on the dry film 107 to form a first RDL layer 110 and the area for leading out the copper wire 109 is opened. A first solder ball 117 is printed in the opened area to form a path for the ASIC chip to be electrically connected to the outside;

[0044] There are through-silicon vias 103 on the silicon wafer 111. The through-silicon vias 103 are filled with a conductive material, polysilicon. There is silicon oxide isolation between the polysilicon and the inner wall of the through-silicon vias 103. The through-silicon vias 103 are connected to the lead-out area 105. The signals of the through-silicon vias 103 are led out to the front side of the silicon wafer 111 through the lead-out area 105 and the metal wire 109;

[0045] On the back side of the silicon wafer 111, a second dielectric layer 112 is deposited. An opening is made in the area of the second dielectric layer 112 corresponding to the silicon through hole 103, and metal is sputtered to form a metal bonding area 113. A polyimide is coated on the back side of the second dielectric layer 112 to form a second RDL layer 114 and is patterned to expose the metal bonding area 113. The metal bonding area 113 is connected to the second solder ball 302, and a stress isolation groove 115 is machined on the silicon wafer 111. The function of the stress isolation groove 115 is to avoid stress problems caused by thermal mismatch. The second solder ball 302 printed on the lead bonding area 301 of the MEMS sensor chip 300 is soldered to the metal bonding area 113 on the back side of the silicon wafer 111.

[0046] In order to obtain Figure 1 the fan-out package structure of Figure 2 — Figure 16 The flow of the fan-out packaging method for the MEMS sensor chip and the ASIC chip is given, specifically as follows:

[0047] A mask 101 is laid on the silicon substrate 100 and a deep groove 102 is etched. This deep groove 102 is used for the processing of the silicon through hole, as Figure 2 shown; an oxide layer is grown on the inner wall of the deep groove 102 and doped polysilicon is deposited on the oxide layer to fill the deep groove 102. The surface mask 101 is removed and the surface is polished to form a silicon through hole 103, as Figure 3 shown; silicon dioxide is deposited as the first dielectric layer 104 and is patterned to open the silicon dioxide above the silicon through hole 103, as Figure 4 shown; metal is deposited and patterned to form a lead-out area 105, as Figure 13 shown; the first dielectric layer 104 and the silicon substrate 100 are etched to form a cavity 106. The depth of this cavity 106 depends on the thickness of the ASIC chip. The deeper the depth of the cavity 106, the greater the impact on the subsequent processing. Therefore, the thinner the ASIC chip, the better, as Figure 6 shown; the ASIC chip 200 is adhered in the cavity 106 through an adhesive 201, as Figure 7 shown; a dry film 107 is pasted on the surfaces of the silicon substrate 100 and the ASIC chip 200, and openings are made at the lead bonding area 202 and the lead-out area 105 of the ASIC chip 200, as Figure 8 shown; a thin layer of metal, such as metals like nickel, titanium, chromium, etc., is deposited on the surfaces of the dry film 107 and the exposed lead bonding area 202 and lead-out area 105 for use as a seed layer 108 for the subsequent electroplating process, as Figure 9 shown; glue is applied and patterned according to the layout of the circuit arrangement. After patterning, copper is electroplated. After electroplating is completed, the glue is removed and the exposed seed layer is removed to form copper wires 109, as Figure 10 shown; polyimide is applied and patterned to expose the copper wires 109 to form a first RDL layer 110, asFigure 11 As shown; the back surface of the thinned silicon substrate 100 is thinned to expose the through-silicon via 103, and the thinned silicon substrate 100 becomes the silicon wafer 111, as Figure 12 shown; deposit silicon dioxide on the back surface of the silicon wafer 111 as the second dielectric layer 112, and open a hole to expose the through-silicon via 103. After exposure, deposit and pattern metal to form the metal bonding region 113, as Figure 13 shown; open a hole in the second dielectric layer 112 and process a silicon groove by etching or laser to form a stress isolation groove 115; coat and pattern polyimide or silicon dioxide on the second dielectric layer 112 to form the second RDL layer 114, and expose the metal bonding region 113 by patterning, as Figure 14 shown; solder balls 302 are implanted on the wire bonding area 301 of the MEMS sensor wafer and cut into single MEMS sensor chips 300, as Figure 15 shown; print the first solder balls 117 in the exposed area of the copper wire 109 to form a path for electrical connection between the ASIC chip and the outside; bond the MEMS sensor chip 300 and the metal bonding region 113 with solder balls 302, and cut the wafer into single chips, as Figure 16 shown.

[0048] Embodiment 2

[0049] A fan-out package structure for a MEMS sensor chip and an ASIC chip, as Figure 17 shown, which is composed of a silicon wafer 131, a MEMS sensor chip 300 and an ASIC chip 200. There is a cavity 106 on the front surface of the silicon wafer 131. The ASIC chip 200 is adhered to the cavity 106 by a die attach film 201. A first dielectric layer 104 is fabricated on the front surface of the silicon wafer 131. A dry film 107 is pressed on the ASIC chip 200 and the first dielectric layer 104. A hole is opened in the dry film 107 corresponding to the wire bonding region 202 of the ASIC chip 200 to expose the wire bonding region 202 of the ASIC chip 200. A seed layer is sputtered on the wire bonding region 202 of the ASIC chip 200 and copper is electroplated on the seed layer to form a copper wire 129. Polyimide is coated on the dry film 107 to form a first RDL layer 130 and the region for leading out the copper wire 129 is opened; a stress isolation groove 135 is processed on the silicon wafer 131, and the function of the stress isolation groove 135 is to avoid stress problems caused by thermal mismatch;

[0050] The second solder balls 302 printed on the wire bonding area 301 of the MEMS sensor chip 300 are welded to the front surface of the silicon wafer 131 to form an electrical connection between the MEMS sensor chip 300 and the ASIC chip 200;

[0051] There is a through-silicon via 103 on the silicon wafer 131. The through-silicon via 103 is filled with conductive polysilicon. There is a silicon dioxide isolation between the polysilicon and the inner wall of the through-silicon via 103. The through-silicon via 103 is connected to the lead-out area 105. The signal of the through-silicon via 103 is led out through the lead-out area 105 and the metal wire 129 to the front side of the silicon wafer 131;

[0052] A second dielectric layer 132 is deposited on the back side of the silicon wafer 131. An opening is made in the area corresponding to the through-silicon via 103 on the second dielectric layer 132 and metal is sputtered to form a metal bonding area 133. A polyimide is coated on the back side of the second dielectric layer 132 to form a second RDL layer 134 and is patterned to expose the metal bonding area 133. A second solder ball 137 is printed on the exposed metal bonding area 133.

[0053] In order to obtain Figure 17 the fan-out package structure, Figure 18 — Figure 26 The flow of the fan-out packaging method for the MEMS sensor chip and the ASIC chip is given. Among them, the Figure 1 — Figure 9 shown flow methods are the same. This embodiment is based on the Figure 9 shown structure for subsequent operations. Specifically:

[0054] Apply glue and pattern according to the layout of the circuit arrangement. After patterning, electroplate copper metal. After electroplating is completed, remove the glue and the exposed seed layer to form a copper wire 129, as Figure 18 shown; Apply and pattern polyimide to expose the copper wire 129 to form a first RDL layer 130, as Figure 19 shown; Thin the back side of the silicon substrate 100 to expose the through-silicon via 103. The thinned silicon substrate 100 becomes the silicon wafer 131, as Figure 20 shown; Deposit silicon dioxide on the back side of the silicon wafer 131 as the second dielectric layer 132, and open an opening to expose the through-silicon via 103. After exposure, deposit metal and pattern to form a metal bonding area 133, as Figure 21 shown; Coat polyimide or silicon dioxide on the second dielectric layer 132 and pattern to form a second RDL layer 134, and expose the metal bonding area 133 through patterning, as Figure 22 shown; Solder ball 137 is implanted on the back side metal bonding area 133, as Figure 23 shown; Open an opening on the first dielectric layer 130 and process a silicon groove by etching or laser as a stress isolation groove 135, as Figure 24 shown; Solder ball 302 is implanted on the lead welding area 301 of the MEMS sensor wafer and cut into single MEMS sensor chips 300, as Figure 25 shown; Bond the MEMS sensor chip 300 and the silicon wafer 131 through the solder ball 302, and cut the wafer into single chips, asFigure 26 as shown

[0055] The stress isolation grooves 115(135) in the above-mentioned first and second embodiments are all silicon grooves, which can be processed by etching or other methods such as laser. In order to balance stress, the structure of the stress isolation groove is a symmetric structure, so the structure can adopt a circular isolation structure 115(135), such as Figure 27 (a) as shown; or a square isolation structure 115(135), such as Figure 27 (b) as shown

[0056] In the present invention, a low-stress wafer-level chip scale package of a MEMS sensor chip and an ASIC chip is realized through a fan-out package method. The fan-out package structure is composed of a MEMS sensor chip, an ASIC chip, and an interposer substrate (silicon wafer). It can flexibly match MEMS sensor chips and ASIC chips of different sizes and thicknesses. Therefore, it can be applied to different types of MEMS sensor chips, such as chips that do not directly contact the external environment, such as accelerometers and gyroscopes, or sensor chips that contact the external environment, such as pressure sensors and microphones. The application-specific integrated circuit is a signal readout circuit supporting the corresponding sensor. The silicon interposer substrate serves as a carrier for the MEMS sensor chip and the ASIC chip. A cavity with a certain depth is etched on the silicon interposer substrate, and the ASIC chip is glued in the cavity with a die attach adhesive. The lead bonding areas of the ASIC chip are re-arranged through a Re-Distribution Layer process. Through-silicon vias are made on the silicon interposer substrate to lead out the signals of the ASIC chip. Solder balls are implanted on the lead welding areas of the MEMS sensor chip and are connected to the metal bonding areas on the silicon interposer substrate through flip-chip bonding. In order to reduce stress, stress isolation grooves are made on the silicon interposer substrate to reduce the influence of stress on the MEMS sensor chip. A wafer-level chip scale package of a low-stress MEMS sensor chip and an ASIC chip is realized. Through the re-wiring technology on the silicon interposer substrate, it is not restricted by the sizes and PAD layouts of the MEMS chip and the ASIC chip, and two or more chips can be flexibly combined into different products, shortening the product development time, reducing the R & D cost, being suitable for rapid large-scale production, effectively reducing the chip and packaging costs, and at the same time effectively reducing the influence of external stress on the MEMS sensor chip through stress isolation, improving the product yield rate

[0057] The above is only the best implementation mode of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several deformations or equivalent replacements can be made to the technical solution of the present invention, and the same technical effects can also be achieved, which should also be regarded as belonging to the protection scope of the present invention

Claims

1. A fan-out package structure for a MEMS sensor chip and an ASIC chip, which is composed of an interposer substrate, a MEMS sensor chip and an ASIC chip. There is a cavity on the front side of the interposer substrate, and the ASIC chip is adhered in the cavity by die attach glue. Characterized in that: A first dielectric layer is fabricated on the front side of the interposer substrate. A dry film is pressed on the ASIC chip and the first dielectric layer. Openings are made in the dry film at the wire bonding areas corresponding to the ASIC chip to expose the wire bonding areas of the ASIC chip. A seed layer is sputtered on the wire bonding areas of the ASIC chip and metal is electroplated on the seed layer to form metal wires. A first RDL layer is coated on the dry film and patterned to lead out the metal wires, and the metal wires are connected to the first solder balls; There are vias on the interposer substrate. The vias are filled with conductive materials, and there is an insulating layer between the conductive materials and the inner walls of the vias for isolation, forming conductive vias. The conductive vias are connected to the lead-out areas, and the signals of the conductive vias are led out to the front side of the interposer substrate through the lead-out areas and the metal wires; A second dielectric layer is deposited on the back side of the interposer substrate. Openings are made in the areas corresponding to the conductive vias on the second dielectric layer and metal is sputtered to form metal bonding areas. A second RDL layer is coated on the back side of the second dielectric layer and patterned to expose the metal bonding areas, and the metal bonding areas are connected to the second solder balls; There are stress isolation grooves on the interposer substrate; The MEMS sensor chip is bonded to the front side of the interposer substrate through the first solder balls or bonded to the back side of the interposer substrate through the second solder balls.

2. The fan-out package structure for a MEMS sensor chip and an ASIC chip according to claim 1, Characterized in that: The interposer substrate is a silicon wafer.

3. The fan-out package structure for a MEMS sensor chip and an ASIC chip according to claim 1 or 2, Characterized in that: The structure of the stress isolation grooves is a symmetric structure.

4. The fan-out package structure for a MEMS sensor chip and an ASIC chip according to claim 3, Characterized in that: The MEMS sensor is an accelerometer, a gyroscope, an image sensor, a pressure sensor or a microphone.

5. The fan-out package structure for a MEMS sensor chip and an ASIC chip according to claim 3, Characterized in that: The conductive material is metal or polysilicon.

6. A fan-out packaging method for a MEMS sensor chip and an ASIC chip, Characterized in that, It includes the following steps: (1) Coating a mask on the front side of the dielectric wafer and etching deep grooves; (2) Growing an insulating layer on the inner walls of the deep grooves and depositing conductive materials on the insulating layer to fill the deep grooves, forming conductive grooves, removing the mask and grinding the surface flat; (3) Depositing a first dielectric layer on the front side of the dielectric wafer and patterning it to expose the conductive grooves; (4) Depositing metal on the first dielectric layer and patterning it to form lead-out areas; (5) Etching the first dielectric layer and the dielectric wafer to form a cavity; (6) Adhering the ASIC chip in the cavity by die attach glue; (7) Laying a dry film on the ASIC chip and the first dielectric layer, and making openings at the corresponding positions of the metal leads and the wire bonding areas of the ASIC chip to expose the lead-out areas and the wire bonding areas; (8) Deposit metal as a seed layer, apply photoresist and pattern it according to the circuit layout pattern, and then electroplate metal to form metal lines; (9) The first RDL layer is coated on the dry film and the first RDL layer is patterned to lead out the metal lines; (10) Thinning the dielectric wafer from the back to expose the conductive grooves to become conductive vias; (11) Deposit a second dielectric layer on the back of the dielectric wafer, open holes to expose the conductive vias, deposit and pattern metal at the conductive vias to form metal bonding pads; (12) Fabricate a second RDL layer on the back of the second dielectric layer and open holes to expose the metal bonding pads; (13) Mount the second solder balls on the lead bonding area of the MEMS sensor wafer and cut it into MEMS sensor chips; (14) Solder the MEMS sensor chips to the metal bonding pads or metal lines through the second solder balls; (15) Cut the fabricated wafer into single chips.

7. The fan-out packaging method of the MEMS sensor chip and the ASIC chip according to claim 6, characterized in that: When the MEMS sensor chip is soldered to the metal bonding pads, in step (11), open holes in the second dielectric layer and fabricate stress isolation grooves on the back of the dielectric wafer.

8. The fan-out packaging method of the MEMS sensor chip and the ASIC chip according to claim 6, characterized in that: When the MEMS sensor chip is soldered to the metal lines, in step (9), open holes in the first RDL layer and fabricate stress isolation grooves on the front of the dielectric wafer.

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