Chip Testing Method, Equipment and Circuit

Abstract

The present invention provides a chip testing method, device and circuit. The chip testing method includes: in response to a first type of preset test instruction, controlling a grounding pin of a chip under test to connect to a non-zero potential, where the first type of preset control instruction at least includes an ODT detection instruction; outputting a control stream corresponding to the preset control instruction to the chip under test, detecting a parameter corresponding to the preset test instruction of the chip under test and outputting a detection result. Embodiments of the present invention can perform ODT testing of a chip without externally connecting a pull-up voltage.

Description

Background Art

[0002] ODT (On Die Terminal) resistors are functions set in DRAM technology to reduce terminal signal reflection. When writing data, in order to achieve impedance matching of the input signal and ensure the quality of the input signal inside the DRAM, the ODT resistor is turned on after receiving the write control signal, and the time point of turning on the ODT resistor directly affects the quality of the DRAM write signal. The JEDEC (Joint Electron Device Engineering Council) standard clearly stipulates the requirements for the ODT timing of DRAMs. Therefore, before the chip leaves the factory, the chip needs to be tested for ODT timing.

[0003] Figure 1 It is an equivalent circuit diagram of the connection between the on-chip terminal, ODT resistor and the automatic test equipment (ATE) in the related art. Refer to Figure 1 , when the DRAM chip receives a write instruction, the switch S0 in series with the ODT resistor RTT closes, and the pin under test DQ is pulled down through the resistor RTT. In order to measure the connection time point between the resistor RTT and the pin under test DQ, in the related art, a pull-up resistor Vterm is set on the signal line connecting the pin under test DQ at the ATE device end. Furthermore, the access time of the ODT resistor can be detected by detecting the voltage change time point on the pin under test DQ.

[0004] However, with the upgrading of ATE technology and other characteristic test requirements, the external Vterm voltage has been gradually phased out. In this case, how to implement the ODT timing test has become a difficult problem.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure. Therefore, it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a chip testing method, device and circuit, which are used to at least overcome to some extent the problem that the chip cannot be tested for ODT after the pull-up resistor is optimized by the automatic test equipment due to the limitations and defects of the related art.

[0007] According to a first aspect of the present disclosure, there is provided a chip testing method, including: controlling a ground pin of a chip under test to connect to a non-zero potential in response to a first type of preset test instruction, where the first type of preset control instruction at least includes an ODT detection instruction; outputting a control flow corresponding to the preset control instruction to the chip under test, detecting a parameter corresponding to the preset test instruction of the chip under test, and outputting a detection result.

[0008] In an exemplary embodiment of the present disclosure, the first type of preset test control instruction includes an ODT detection instruction, and the controlling the ground pin of the chip under test to connect to a non-zero potential in response to the first type of preset control instruction includes: controlling the ground pin of the chip under test to connect to a first voltage in response to the ODT detection instruction.

[0009] In an exemplary embodiment of the present disclosure, the outputting a control flow corresponding to the preset control instruction to the chip under test, detecting a parameter corresponding to the preset test instruction of the chip under test, and outputting a detection result includes: outputting a data write control instruction to the chip under test at a first time point; detecting a second time point when the voltage of a target input / output pin of the chip under test changes; and determining that the target input / output pin passes the ODT detection when the difference between the second time point and the first time point meets a preset value.

[0010] In an exemplary embodiment of the present disclosure, the first voltage is less than the minimum power supply voltage of the chip under test.

[0011] In an exemplary embodiment of the present disclosure, the first type of preset control instruction includes a read / write synchronization signal clock test instruction, and the controlling the ground pin of the chip under test to connect to a non-zero potential in response to the first type of preset control instruction includes: controlling the ground pin of the chip under test to connect to a second voltage in response to the read / write synchronization signal clock test instruction.

[0012] In an exemplary embodiment of the present disclosure, the second voltage is 0.1V.

[0013] In an exemplary embodiment of the present disclosure, it further includes: controlling the ground pin of the chip under test to connect to a zero potential in response to a first type of preset test end instruction or a second type of preset test instruction.

[0014] According to a second aspect of the present disclosure, there is provided a chip testing device, including: a chip connection module, including a plurality of connection terminals for connecting a plurality of pins of a chip under test, the plurality of pins including a ground pin, and the plurality of connection terminals including a ground connection terminal for connecting the ground pin; a power supply setting module, with a first end connected to the ground connection terminal, a second end connected to a first voltage, a third end connected to a second voltage, and a fourth end grounded; a test control module, electrically connected to the power supply setting module and the chip connection module, configured to output control commands to the chip under test, read the states of the plurality of pins of the chip under test, and in response to a first type of preset test instruction, control the first end to be connected to one end other than the fourth end.

[0015] In an exemplary embodiment of the present disclosure, the first type of preset test instruction includes an ODT test instruction, and the test control module is configured to: in response to the ODT test instruction, control the first end to be only connected to the second end; output a data write control instruction to the chip under test through the plurality of connection terminals at a first time point; read the voltage of a target input / output pin of the chip under test through the plurality of connection terminals to determine a second time point when the voltage of the target input / output pin changes; and when the difference between the second time point and the first time point meets a preset value, determine that the target input / output pin passes the ODT detection.

[0016] In an exemplary embodiment of the present disclosure, the first voltage is less than the minimum power supply voltage of the chip under test.

[0017] In an exemplary embodiment of the present disclosure, the first type of preset test instruction includes a read / write synchronization signal clock test instruction, and the test control module is configured to: in response to the read / write synchronization signal clock test instruction, control the first end to be only connected to the third end; output a data read control instruction to the chip under test through the plurality of connection terminals at a third time point; read the read / write synchronization signal clock pin and the data pin of the chip under test to detect a fourth time point when the rising edge of data transmission appears on the read / write synchronization signal clock pin; and when the difference between the fourth time point and the third time point meets a preset condition, determine that the read / write synchronization signal clock of the chip under test passes the test.

[0018] In an exemplary embodiment of the present disclosure, the second voltage is 0.1V.

[0019] In an exemplary embodiment of the present disclosure, the power supply setting module includes a first resistor, with a first end of the first resistor connected to the first end of the power supply setting module, and a second end of the first resistor electrically connected to the second end, the third end, and the fourth end of the power supply setting module.

[0020] In an exemplary embodiment of the present disclosure, the first resistor is 50 ohms.

[0021] According to a third aspect of the present disclosure, there is provided a chip test circuit, including: a first terminal for connecting to a ground pin of a chip under test; a first switch having two ends respectively connected to the first terminal and a first voltage, for connecting the first terminal and the first voltage in response to a first control signal; a second switch having two ends respectively connected to the first terminal and a second voltage, for connecting the first terminal and the second voltage in response to a second control signal; and a third switch having two ends respectively connected to the first terminal and a zero potential, for connecting the first terminal and the zero potential in response to a third control signal.

[0022] In the embodiment of the present disclosure, by controlling the ground pin of the chip under test to connect to a non-zero potential in response to a first type of preset test instruction, when the ODT resistor is connected to the pin under test, a voltage change can occur at the pin under test through the non-zero voltage at the second end of the ODT resistor. Furthermore, the ODT resistor connection time point of the pin under test can be measured without connecting an external pull-up resistor.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0025] Figure 1 is an equivalent circuit diagram of the connection between a chip terminal, an ODT resistor, and an automatic test equipment (Auto Test Equipment) in the related art.

[0026] Figure 2 is a flowchart of a chip test method in an exemplary embodiment of the present disclosure.

[0027] Figure 3 is a circuit diagram that can implement the Figure 2 shown functions in an embodiment of the present disclosure.

[0028] Figure 4 is an application Figure 3 block diagram of a chip test device according to the shown embodiment.

[0029] Figure 5 is an equivalent circuit diagram of a chip test device 400 when performing an ODT test in an embodiment of the present disclosure.

[0030] Figure 6 In one embodiment of the present disclosure Figure 5 is a schematic diagram of the voltage change during the shown test process.

[0031] Figure 7 is an equivalent circuit diagram of the chip test device 400 when performing read-write synchronization signal clocking in one embodiment of the present disclosure.

[0032] Figure 8 is a timing diagram of testing the read-write synchronization signal clock in an embodiment of the present disclosure.

[0033] Figure 9 is a circuit diagram of the power supply setting module in another embodiment of the present disclosure.

[0034] Figure 10 is a block diagram of an electronic device in an exemplary embodiment of the present disclosure. Detailed implementation manners

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring the various aspects of the present disclosure.

[0036] In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0037] The example embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0038] Figure 2 is a flowchart of a chip testing method in an exemplary embodiment of the present disclosure.

[0039] ReferenceFigure 2 , the chip testing method 200 may include:

[0040] Step S1, in response to a first type of preset test instruction, control the ground pin of the chip under test to connect to a non-zero potential, where the first type of preset control instruction at least includes an ODT detection instruction;

[0041] Step S2, output a control flow corresponding to the preset control instruction to the chip under test, detect a parameter corresponding to the preset test instruction of the chip under test, and output a detection result.

[0042] In the embodiment of the present disclosure, by controlling the ground pin of the chip under test to connect to a non-zero potential in response to a first type of preset test instruction, when the ODT resistor is connected to the pin under test, a voltage change can occur at the pin under test through the non-zero voltage at the second end of the ODT resistor. Furthermore, the ODT resistor access time point of the pin under test can be measured without connecting an external pull-up resistor.

[0043] In an exemplary embodiment of the present disclosure, the first type of preset test control instruction includes an ODT detection instruction. Step S1 includes controlling the ground pin of the chip under test to connect to a first voltage in response to the ODT detection instruction. Step S2 includes outputting a data write control instruction to the chip under test at a first time point, and detecting a second time point when the voltage of the target input / output pin of the chip under test changes. When the difference between the second time point and the first time point meets a preset value, it is determined that the target input / output pin passes the ODT detection. Herein, the first voltage is, for example, less than the minimum power supply voltage of the chip under test.

[0044] In an exemplary embodiment of the present disclosure, the first type of preset control instruction includes a read / write synchronization signal clock test instruction. Step S1 includes: controlling the ground pin of the chip under test to connect to a second voltage in response to the read / write synchronization signal clock test instruction; Step S2 includes: outputting a data read control instruction to the chip under test through the plurality of connection ends at a third time point, reading the read / write synchronization signal clock pin and the data pin of the chip under test to detect a fourth time point when the data transmission rising edge of the read / write synchronization signal clock pin appears; when the difference between the fourth time point and the third time point meets a preset condition, it is determined that the read / write synchronization signal clock of the chip under test passes the test. In an embodiment of the present disclosure, the second voltage may be, for example, 0.1V.

[0045] Figure 3 This is what can be achieved in an embodiment of the present disclosure Figure 2 The circuit diagram of the shown function.

[0046] Refer to Figure 3 , in an embodiment, the chip testing circuit 300 may include:

[0047] A first terminal 31 for connecting to the ground pin VSS of the chip under test;

[0048] A first switch S1, with two ends respectively connected to the first terminal 31 and a first voltage V1, for connecting the first terminal and the first voltage V1 in response to a first control signal;

[0049] A second switch S2, with two ends respectively connected to the first terminal 31 and a second voltage V2, for connecting the first terminal 31 and the second voltage V2 in response to a second control signal;

[0050] A third switch S3, with two ends respectively connected to the first terminal 31 and a zero potential GND, for connecting the first terminal 31 and the zero potential GND in response to a third control signal.

[0051] Figure 3 The circuit shown can be applied in a chip testing device.

[0052] When the chip testing device performs an ODT test on the chip, it outputs a data write control instruction to the chip under test through other connection terminals, and then outputs a first control signal to control the first switch S1 to close and the second switch S2 and the third switch S3 to open, so that the ground pin of the chip under test is connected to the first voltage V1 through the first terminal 31.

[0053] When the chip testing device performs a read-write synchronization signal clock (tDQSCK) test on the chip, it outputs a data read control instruction to the chip under test through other connection terminals, and then outputs a second control signal to control the second switch S2 to close and the first switch S1 and the third switch S3 to open, so that the ground pin of the chip under test is connected to the second voltage V2 through the first terminal 31.

[0054] In addition, when the chip testing device performs other tests on the chip, it can also respond to a first type of preset test end instruction or a second type of preset test instruction to control the ground pin of the chip under test to be connected to a zero potential. In Figure 3 the illustrated embodiment, that is, it outputs a third control signal to control the first switch S1 and the second switch S2 to open and the third switch S3 to close, so that the ground pin of the chip under test is connected to the zero potential GND through the first terminal 31.

[0055] It can be understood that although in Figure 3 , three switches are provided to be respectively connected to three voltages, in other embodiments of the present disclosure, more switches can also be provided to connect more voltages to achieve different test purposes. In addition, only one switch (such as a single-pole double-throw switch) can also be provided to achieve the purpose of connecting the first terminal 31 to different voltages. The present disclosure does not make special restrictions on this, and those skilled in the art can set the number of switches, the types of switches, and the voltage values of the connected voltages according to different technical purposes.

[0056] Figure 4 is an application Figure 3 The block diagram of the chip testing device according to the illustrated embodiment.

[0057] Referring to Figure 4 , the chip testing device 400 may include:

[0058] A chip connection module 41, including a plurality of connection terminals for connecting a plurality of pins of the chip under test 40, the plurality of pins including a ground pin VSS, and the plurality of connection terminals including a ground connection terminal 411 for connecting the ground pin VSS;

[0059] A power supply setting module 42, with a first end 421 connected to the ground connection terminal 411, a second end 422 connected to a first voltage V1, a third end 423 connected to a second voltage V2, and a fourth end 424 grounded;

[0060] A test control module 43, electrically connected to the power supply setting module 42 and the chip connection module 41, for outputting control commands to the chip under test 40, reading the states of the plurality of pins of the chip under test 40, and in response to a first type of preset test instruction, connecting the first end of the power supply setting module 42 to one end other than the fourth end 424.

[0061] Among them, the power supply setting module 42 of the chip testing device 400 may be implemented by Figure 3 the chip testing circuit according to the illustrated embodiment, and the control logic of the test control module 43 may execute Figure 2 the chip testing method according to the illustrated embodiment.

[0062] Figure 5 is the equivalent circuit diagram of the chip testing device 400 in an embodiment of the present disclosure when performing an ODT test.

[0063] Referring to Figure 5 , when the chip testing device 400 performs an ODT test, the test control module 43 is set to: in response to an ODT test instruction, control the first end to be connected only to the second end; output a data write control instruction to the chip under test through the plurality of connection terminals at a first time point; read the voltage of the target input / output pin of the chip under test through the plurality of connection terminals to determine a second time point when the voltage of the target input / output pin changes; when the difference between the second time point and the first time point meets a preset value, determine that the target input / output pin passes the ODT detection.

[0064] At this time, the first end of the ODT resistor RTT is connected to the data pin DQ of the chip under test 50 through the switch S0, and the second end of the resistor RTT is connected to the first voltage V1. The test equipment ATE continuously monitors the voltage of the data pin DQ. When the switch S0 is not closed, the voltage V of the data pin DQ DQ is a floating voltage (V float ); when the chip under test 50 responds to the data write control signal and closes the switch S0, the voltage V on the data pin DQ DQ changes due to the voltage division effect of the first voltage V1 by the resistor RTT. Therefore, the closing time of the switch S0 can be detected in a timely manner. In order to make this voltage change large enough to clearly detect the closing time of the switch S0, in an embodiment of the present disclosure, the first voltage can be set to be less than the minimum power supply voltage of the chip under test. For example, the first voltage V1 is set to 2V - 3V, or set to -1.5V - 2V. In other voltage environments, the first voltage V1 can also be other values as long as the above purpose can be achieved.

[0065] Figure 6 is a schematic diagram of the voltage change during the test process in an embodiment of the present disclosure Figure 5 .

[0066] Referring to Figure 6 , before the first time point T1, the voltage V of the data pin DQ of the chip under test DQ is equal to the floating voltage V float . At the second time point T2, which is a period of time after the first time point T1, the voltage V of the data pin DQ DQ becomes V ODT . The value of V ODT is related to the first voltage V1, the ODT resistor RTT, and the internal impedance of the chip connection module 41. By increasing the first voltage V1, V ODT can be made more obvious than V float . By calculating whether the difference between the second time point T2 and the first time point T1 meets the range specified by the JEDEC standard, it can be determined whether the ODT Timing of the data pin DQ meets the standard and whether the test is passed.

[0067] During the read and write process of the DRAM, the ODT state needs to be kept open for a period of time before and after the data is officially sent. Therefore, the relevant tODTLON timing (ODT resistor access duration, access time point) can be tested through the embodiment of the present disclosure.

[0068] The above situation where the pin under test is the data pin DQ is only an example. In actual applications, the pin under test can also be pins with ODT modes such as DQS and DMI. The present disclosure is not limited thereto.

[0069] Since the ground pin VSS is connected to a non-zero voltage, in Figure 5 the illustrated embodiment, the chip under test 50 is not suitable for normal operation. Therefore, control instructions can be output through other pins to control the chip under test 50 not to respond to the write signal (the memory cells of the DRAM do not generate electrical signals on the IO channel). At the same time, at the ATE end, no data signal is written to the chip under test 50. That is, in the ODT test mode, the chip under test 50 does not perform other actions except connecting the resistance RTT.

[0070] In some embodiments, in order to better perform impedance matching, in the chip under test 50, the switch S0 may consist of a group of switches, and each switch is connected to an ODT resistor. The resistance values of these ODT resistors can be the same or different. Thus, the chip under test 50 can determine which switch or switches to close and which one or more of the multiple ODT resistors to connect according to the received data write control signal, so as to achieve better impedance matching and prevent signal reflection. It can be understood that in the drawings of the embodiments of the present disclosure, only the switch S0 is used to functionally represent this structure, and the setting of the actual ODT circuit and resistor in the chip under test is not limited.

[0071] The method provided by the embodiments of the present disclosure can also be used to test whether the read-write synchronization signal clock (tDQSCK) of the chip meets the standard.

[0072] For a DRAM, when receiving a data read control instruction, an internal output synchronization clock signal is output to output the data to be read. The time difference (i.e., the data preparation time) between the third time point T3 when the synchronization clock signal is output and the fourth time point T4 when the data to be read starts to be output also needs to meet the JEDEC standard. Therefore, it is necessary to test this read-write synchronization signal clock.

[0073] Figure 7 is the equivalent circuit diagram of the chip test device 400 in an embodiment of the present disclosure when performing the read-write synchronization signal clock.

[0074] Referring to Figure 7 , when the chip test device 70 performs a read-write synchronization signal clock test instruction, the test control module 43 can be set as follows: in response to the read-write synchronization signal clock test instruction, control the first end to be only connected to the third end; output a data read control instruction to the chip under test through the multiple connection ends at the third time point; read the read-write synchronization signal clock pin and the data pin of the chip under test to detect the fourth time point when the rising edge of the data transmission on the read-write synchronization signal clock pin appears; when the difference between the fourth time point and the third time point meets the preset condition, determine that the read-write synchronization signal clock of the chip under test passes the test.

[0075] In an exemplary embodiment of the present disclosure, the second voltage is 0.1V.

[0076] In Figure 7 the illustrated embodiment, the ground pin of the chip under test 70 is connected to the second voltage V2, thereby reducing the noise of the read / write synchronization signal clock, enabling the test equipment ATE to view the waveforms of the DQSCK pin and the DQ pin of the chip under test 70 in real time.

[0077] Figure 8 is the timing diagram of testing the read / write synchronization signal clock in the embodiment of the present disclosure.

[0078] Referring to Figure 8 , after the test equipment ATE outputs a data read control signal through a command at the third time point T3, the test equipment ATE can view the waveform changes of the DQS pin and the waveform changes of the DQ pin in real time, so as to find the fourth time point T4 when the data rising edge is generated on the DQ pin. By calculating the time difference between the fourth time point T4 and the third time point T3, it is determined whether the read / write synchronization signal clock of the chip under test meets the standard.

[0079] In another embodiment, the first type of preset control signal may also include an RTP time (tRTP) test signal, so that the test control module 42 can control the ground pin of the chip under test to be connected to the second voltage V2, implementing the same test logic as tDQSCK. This will not be elaborated here.

[0080] Figure 9 is the circuit diagram of the power supply setting module in another embodiment of the present disclosure.

[0081] Referring to Figure 9 , in an exemplary embodiment of the present disclosure, the power supply setting module 42 further includes a first resistor R1. The first end of the first resistor R1 is connected to the first end 421 of the power supply setting module 42, and the second end of the first resistor R1 is connected to the first ends of the first switch S1, the second switch S2, and the third switch S3, that is, electrically connected to the second end 422, the third end 423, and the fourth end 424 of the power supply setting module 42. In an exemplary embodiment of the present disclosure, the first resistor is 50 ohms.

[0082] Figure 9 The illustrated first resistor R1 can also be arranged Figure 3 in the chip test circuit shown, at the same position.

[0083] By connecting a 50Ω resistor in series between the power supply setting module 41 (chip test circuit) and the ground pin of the chip, the signal noise can be further reduced and the viewing efficiency of the real-time waveform can be improved when performing the test represented by the first type of preset control signal.

[0084] Finally, when the test represented by the first type of preset control signal is completed, or when performing a test represented by a second type of preset control signal that requires the ground pin of the chip to be connected to zero potential, the test control module 43 of the chip test device 400 can be set to: in response to the end instruction of the first type of preset test or the second type of preset test instruction, control the ground pin of the chip under test to be connected to zero potential. In Figure 5 or Figure 3 In the embodiment shown, that is, control the first switch S1 and the second switch S2 to be turned off, and the third switch S3 to be turned on, so that the ground pin of the chip under test is connected to zero potential GND.

[0085] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more of the above-mentioned modules or units can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0086] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, method, or program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuit", "module", or "system" here.

[0087] Next, refer to Figure 10 to describe an electronic device 1000 capable of implementing the test control module 43 of the present invention. Figure 10 The electronic device 1000 shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present invention.

[0088] As Figure 10 shown, the electronic device 1000 is presented in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one of the above-mentioned processing units 1010, at least one of the above-mentioned storage units 1020, and a bus 1030 connecting different system components (including the storage unit 1020 and the processing unit 1010).

[0089] Among them, the storage unit stores program code, and the program code can be executed by the processing unit 1010, so that the processing unit 1010 executes the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification. For example, the processing unit 1010 can execute the method as shown in the embodiments of the present disclosure.

[0090] The storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 10201 and / or a cache storage unit 10202, and may further include a read-only storage unit (ROM) 10203.

[0091] The storage unit 1020 may also include a program / utilities 10204 having a set (at least one) of program modules 10205. Such program modules 10205 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment.

[0092] The bus 1030 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus structures.

[0093] The electronic device 1000 may also communicate with one or more external devices 1100 (such as a keyboard, a pointing device, a Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 1000, and / or may communicate with any device that enables the electronic device 1000 to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication may be through an input / output (I / O) interface 1050. And, the electronic device 1000 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 1060. As shown in the figure, the network adapter 1060 communicates with other modules of the electronic device 1000 through the bus 1030. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0094] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or can be implemented by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0095] In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium, on which a program product capable of implementing the above methods in this specification is stored. In some possible implementation manners, various aspects of the present invention can also be implemented in the form of a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification.

[0096] The program product for implementing the above method according to an embodiment of the present invention may be a portable compact disc read-only memory (CD-ROM) and includes program code, and can run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0097] The program product may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0098] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal may take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable signal medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0099] The program code contained on the readable medium can be transmitted by any appropriate medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination of the above.

[0100] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0101] In addition, the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the chronological order of these processes. Additionally, it is also easy to understand that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0102] Other embodiments of the present disclosure will be readily apparent to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only to be considered as exemplary, and the true scope and concept of the present disclosure are pointed out by the claims.

Claims

1. A chip testing method, characterized in that, it includes: Controlling the ground pin of the chip under test to connect to a non-zero potential in response to a first type of preset test instruction, and the first type of preset control instruction at least includes an ODT detection instruction; Outputting a control flow corresponding to the preset control instruction to the chip under test, detecting parameters corresponding to the preset test instruction of the chip under test, and outputting a detection result; The first type of preset test control instruction includes an ODT detection instruction, and the controlling the ground pin of the chip under test to connect to a non-zero potential in response to the first type of preset control instruction includes: Controlling the ground pin of the chip under test to connect to a first voltage in response to the ODT detection instruction; The outputting a control flow corresponding to the preset control instruction to the chip under test, detecting parameters corresponding to the preset test instruction of the chip under test, and outputting a detection result includes: Outputting a data write control instruction to the chip under test at a first time point; Detecting a second time point when the voltage of the target input / output pin of the chip under test changes; When the difference between the second time point and the first time point meets a preset value, determining that the target input / output pin passes the ODT detection.

2. The chip testing method according to claim 1, characterized in that, The first voltage is less than the minimum power supply voltage of the chip under test.

3. The chip testing method according to claim 1, characterized in that, The first type of preset control instruction includes a read / write synchronization signal clock test instruction, and the controlling the ground pin of the chip under test to connect to a non-zero potential in response to the first type of preset control instruction includes: Controlling the ground pin of the chip under test to connect to a second voltage in response to the read / write synchronization signal clock test instruction.

4. The chip testing method according to claim 3, characterized in that, The second voltage is 0.1V.

5. The chip testing method according to claim 1, characterized in that, it further includes: Controlling the ground pin of the chip under test to connect to a zero potential in response to a first type of preset test end instruction or a second type of preset test instruction.

6. A chip testing device, characterized in that, it includes: A chip connection module, including a plurality of connection ends for connecting a plurality of pins of the chip under test, the plurality of pins including a ground pin, and the plurality of connection ends including a ground connection end for connecting the ground pin; A power supply setting module, with a first end connected to the ground connection end, a second end connected to a first voltage, a third end connected to a second voltage, and a fourth end grounded; A test control module, electrically connected to the power supply setting module and the chip connection module, for outputting a control command to the chip under test, reading the states of a plurality of pins of the chip under test, and controlling the first end to be connected to one end other than the fourth end in response to a first type of preset test instruction; The first type of preset test instruction includes an ODT test instruction, and the test control module is set to: In response to the ODT test instruction, control the first end to be only connected to the second end; Outputting a data write control instruction to the chip under test through the plurality of connection ends at a first time point; Read the voltage of the target input / output pins of the chip under test through the multiple connection ends to determine the second time point when the voltage of the target input / output pins changes; When the difference between the second time point and the first time point meets a preset value, determine that the target input / output pins pass the ODT test.

7. The chip testing device according to claim 6, wherein the first voltage is less than the minimum power supply voltage of the chip under test.

8. The chip testing device according to claim 6, characterized in that, The first type of preset test instructions includes a read-write synchronous signal clock test instruction, and the test control module is set to: In response to the read-write synchronous signal clock test instruction, control the first end to be connected only to the third end; Output a data read control instruction to the chip under test through the multiple connection ends at a third time point; Read the read-write synchronous signal clock pin and the data pin of the chip under test to detect the fourth time point when the rising edge of data transmission on the read-write synchronous signal clock pin appears; When the difference between the fourth time point and the third time point meets a preset condition, determine that the read-write synchronous signal clock of the chip under test passes the test.

9. The chip testing device according to claim 6, characterized in that, The second voltage is 0.1V.

10. The chip testing device according to claim 6, characterized in that, The power supply setting module includes a first resistor. The first end of the first resistor is connected to the first end of the power supply setting module, and the second end of the first resistor is electrically connected to the second end, the third end, and the fourth end of the power supply setting module.

11. The chip testing device according to claim 10, characterized in that, The first resistor is 50 ohms.

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