Physical co-design method for flow layer under continuous microfluidic biochip

Abstract

The application provides a continuous microfluidic biochip underflow layer physical collaborative design method, which realizes the underflow layer physical design work in three stages.(1) Logic design stage: through the first proposed logic layout and component direction layout adjustment method, the excellent logic position and logic direction of the component are obtained, which greatly improves the efficiency while ensuring the high-quality layout solution.(2) Component mapping and bounding box gap layout adjustment stage: based on the bounding box strategy, the component logic design result of the previous stage is mapped to the actual physical design space, and the best bounding box gap is obtained through the bounding box gap layout adjustment.(3) Shrink layout adjustment stage: based on the connection graph relationship between components, two new layout adjustment methods, namely along-flow channel shrinkage and multi-graph shrinkage, are proposed, which further efficiently improves the quality of the underflow layer physical design. The application not only effectively improves the quality of the underflow layer physical design, but also greatly improves the efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design technology for continuous microfluidic biochips, and in particular to a fluid spherical physical co-design method for continuous microfluidic biochips. Background Technology

[0002] Continuous microfluidic biochips, also known as laboratory-on-a-chip (POCs), integrate essential biochemical functional components (such as mixers, heaters, filters, and detectors), offering numerous advantages such as high precision, high throughput, high automation, miniaturization, and low sample consumption. Therefore, they have received increasing attention in recent years and have been successfully applied to nucleic acid extraction, rapid pathogen detection, cell culture, clinical diagnostics, and DNA analysis. Fluid spherical physics co-design plays a crucial role in the overall design quality and efficiency of biochips. Current biochip technologies suffer from low overall design quality and inefficiency. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a fluid spherical physical co-design method under continuous microfluidic biochips, which effectively improves the quality of fluid spherical physical design and also achieves a significant increase in efficiency.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a fluidic physics co-design method under continuous microfluidic biochips, including logical layout, component orientation layout adjustment, bounding box gap layout adjustment, flow channel shrinkage, and multi-graph shrinkage; each component is initially set as a unit in the logical space, and based on the connection relationship between components, two exchange operations, proximity movement and target jump, are used; through the multi-graph shrinkage strategy, a new round of layout adjustment is performed on test cases containing multiple connected graphs.

[0005] In a preferred embodiment, the size of the logical space is set to the smallest rectangle with an area that can accommodate all components and whose adjacent side lengths are similar. First, each component is placed into each unit of the logical space in ascending order of component number. The component number is represented by a non-zero positive integer, and empty logical positions are represented by zero, thereby initializing the logical space. Second, based on the connection relationship between components, two exchange operations, namely proximity movement and target jump, are used to achieve a clustering effect, that is, the Manhattan distance between connected component units in the logical space is small.

[0006] In a preferred embodiment, the proximity swap operation targets components adjacent to the component in all four directions, and swaps their logical positions with the component unit that yields the greatest net benefit. The Manhattan distance between each component is only 1 unit. The net benefit is the sum of the Manhattan distances between the two components and all connected components before the swap, minus the difference between the sum of the Manhattan distances between the two components and all connected components after the swap. The net benefit is calculated as follows:

[0007]

[0008] Where a is an active switching component, b is a passively switching neighbor component, and the Manhattan logical distance between a and b is only 1; a_links is the number of components connected to component a, b_links is the number of components connected to component b; dir is a direction in the four cardinal directions, and dis is the Manhattan logical distance between the two components. For the distance gain of the active switching component a in a certain dir direction; To actively exchange the Manhattan distance between component a and its connected component i before they move to a neighboring location, The Manhattan distance between active exchange component a and its connected component i after a neighboring move; To actively exchange the Manhattan distance between component b and its connected component j before they move to a neighboring location, The Manhattan distance between active exchange component b and its connected component j after a neighboring move;

[0009] After calculating the net profit of all components in all four directions, swap the logical positions with the component in the direction of maximum profit, and iterate the calculation and swapping process until the net profit of all components in all four directions is less than or equal to zero.

[0010] In a preferred embodiment, firstly, the edge with the largest Manhattan distance and which is not locked is selected. Based on the probability that the degree of each component at both ends of the edge accounts for the sum of their degrees, roles are assigned to these two components. The component with the highest probability is assigned as the target component, and the other component is assigned as the jump component. Secondly, if there is an empty logical position around the target component, the jump component jumps directly to that position. If there is no empty logical position around the target component, a component is randomly selected from the eight surrounding components. The net profit is calculated using equation (2), and the component is traversed in a clockwise direction until the first component with a non-negative net profit is obtained by exchanging positions with the jump component. The jump position exchange operation is then performed. If the net profit of exchanging positions with all surrounding components is negative, the jump is abandoned. The edge is locked in this round, and the iteration continues until all edges are locked. Then, all edges are unlocked to start a new round of iteration. This process is repeated until the iteration threshold is reached or the net profit in equation (1) is positive, and the iteration ends.

[0011]

[0012] Where edges is the total number of edges, the formula calculates the difference in Manhattan distance between the components at both ends of all edges before and after the jump action, and takes this as the net gain of the entire logical space. E all The total gain of the current target jump in the entire logical space; The Manhattan distance between the two components connecting the edges before the target jump. The Manhattan distance between the two components of the connecting edge after the target jump action.

[0013] In a preferred embodiment, the component orientation layout adjustment is specifically achieved by calculating the sum of the Manhattan distances between the port and the connected components in four orientations to obtain the direction with the minimum distance as the optimized layout direction of the component; the logical position of the port is the same as the position of the logical unit adjacent to the port.

[0014] In a preferred embodiment, after the first stage of work is completed, the logical position and logical direction of the components are obtained, and the components are placed using a bounding box strategy. The bounding box strategy is to uniformly use the smallest square bounding box of equal area as a container to wrap each component, and its side length is equal to the maximum size of all components in two dimensions.

[0015] In a preferred embodiment, after the components are placed, the layout quality is evaluated through actual wiring, and the fitness value function F is calculated as follows:

[0016] F=α×C+β×L+γ×A (3)

[0017] Where C is the number of flow channel intersections generated after the layout and routing work, L is the total length of the flow channel, and A is the overall area of ​​the flow layer; α, β and γ are weights, which are 300, 20 and 1 respectively.

[0018] In a preferred embodiment, the routing algorithm uses a two-stage A* algorithm to route all flow channels. In the first stage, as many flow channels as possible are successfully routed without allowing flow channel intersections. In the second stage, the restriction of not allowing flow channel intersections is lifted, and all flow channels that failed to route in the previous stage are routed again until all flow channels are successfully routed.

[0019] The routing sequence follows the proximity principle, that is, the ascending order of the Manhattan distance between the components at both ends of the flow channel is used as the routing sequence, so that the shorter flow channels that occupy less resources have a higher priority routing sequence.

[0020] In a preferred embodiment, in the wiring algorithm, after the second stage of work is completed, the flow channel is contracted; the flow channel contraction is to shorten the flow channel as much as possible along the only flow channel connected to it while satisfying the constraints, and move the component to the corresponding new position.

[0021] In a preferred embodiment, after shrinking along the flow channel, a multi-graph shrinkage method is adopted. The specific strategy of multi-graph shrinkage is to treat all components and flow channels in a single graph as homogeneous blocks, without changing the shape and orientation of the blocks, and move them as close as possible to the northwest direction in physical space. If the application use case has only one connected graph, the multi-graph shrinkage stage is skipped and the final fluid layer physical design solution is directly output. If there are multiple connected graphs, the final fluid layer physical design solution is output after multi-graph shrinkage optimization.

[0022] Compared with existing technologies, this invention has the following advantages: In the process of spherical physical design, it changes the previous method of separating layout and wiring, and utilizes a dynamic feedback mechanism to feed back wiring results to the layout during the layout adjustment stage, thereby improving the quality of spherical physical design. However, current physical co-design methods still have significant room for improvement in both quality and efficiency. Attached Figure Description

[0023] Figure 1 The overall algorithm design flow of the preferred embodiment of the present invention;

[0024] Figure 2 This is the initial state of the logical space in a preferred embodiment of the present invention;

[0025] Figure 3 This refers to the exchange operation of two component units in the logical layout of a preferred embodiment of the present invention.

[0026] Figure 4 The diagram illustrates the logical layout effect of a preferred embodiment of the present invention; (a) initial logical layout, (b) result after logical layout optimization;

[0027] Figure 5 This is a schematic diagram illustrating the effect of component orientation layout adjustment in a preferred embodiment of the present invention; (a) fixed component orientation layout, (b) layout after component orientation adjustment;

[0028] Figure 6 This is a bounding box strategy placement component according to a preferred embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of the adjustment of the enclosure box gap layout according to a preferred embodiment of the present invention;

[0030] Figure 8 This is a schematic diagram of the flow channel contraction strategy before and after a preferred embodiment of the present invention. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0034] This invention specifically includes the following strategies:

[0035] I. This invention designs a novel layout algorithm: logical layout. This algorithm initializes each component as a unit in the logical space, and based on the connection relationships between components, utilizes two exchange operations—neighborhood movement and target jump—to efficiently obtain the optimal logical positions of all components.

[0036] II. In the process of layout adjustment, this invention not only considers the component objects, but also, for the first time, considers the orientation of the specific connecting ports on the components, further reducing the granularity. By adjusting the component orientation layout, the orientation of the ports on the components is optimized, significantly reducing the number of flow channel intersections and the total length of the flow channels.

[0037] III. Based on the connection relationship between components within a single connected graph, this invention proposes a layout adjustment strategy that shrinks along the flow channel, significantly reducing the total length of the flow channel by utilizing existing wiring information.

[0038] IV. This invention takes into account the two types of component connection relationships, namely, singly connected graphs and multi-connected graphs. Through a multi-graph shrinkage strategy, a new round of layout adjustments is made to test cases containing multiple connected graphs, effectively reducing the overall area of ​​the flow layer.

[0039] refer to Figures 1 to 8 Specifically:

[0040] 1. Overall Algorithm Design Flow:

[0041] like Figure 1 As shown, the overall design process mainly includes strategies such as logical layout, component orientation layout adjustment, bounding box gap layout adjustment, flow channel shrinkage, and multi-image shrinkage. It can be mainly divided into three stages, such as... Figure 1 As shown.

[0042] The first stage, logical design, includes two algorithms: logical layout and component orientation layout adjustment. These aim to achieve optimal logical positions and orientations for components within the logical space. First, the logical layout initializes the logical space. Then, based on the connections between components, it utilizes position swapping operations between two types of components in the logical layout to minimize the Manhattan distance between connected components, achieving a clustering effect and thus obtaining optimal logical positions, reducing the total length of the flow channels and the number of flow channel intersections. Second, considering that connectivity between components needs to be specific to port connectivity, this invention further reduces granularity by designing a component orientation layout adjustment strategy. By adjusting the logical orientation of components, the position of ports within components is adjusted, minimizing the Manhattan distance between connected ports on connected components to obtain optimal logical orientations, further reducing the total length of the flow channels and the number of flow channel intersections.

[0043] Phase Two: Component Mapping and Bounding Box Gap Adjustment. First, to map components from their logical locations to their actual locations while maintaining the optimal logical positions and orientations of the components after Phase One, this invention employs a bounding box strategy for component placement. This involves uniformly enclosing all components in a square container with the smallest side length, and then mapping each bounding box to the actual layout and routing physical space with a uniform initial gap. Second, after component placement, routing operations are performed on all flow channels based on the ascending order of the Manhattan distance between the components at both ends of the flow channel, obtaining the flow layer physical design solution under the initial bounding box gap. Finally, to maximize the quality of the current flow layer physical design, layout adjustments are made to increase the bounding box gap, and this process is iterated until the set gap threshold is reached. After iteration, the optimal bounding box gap is obtained.

[0044] The third stage: Shrink layout adjustment. Building upon the optimal bounding box gaps achieved in the previous stage for layout and routing, this invention implements two shrink-based layout adjustment methods in stages: shrinking along flow channels and multi-graph shrinking. First, to reduce the total length of flow channels, considering the relatively small number of component ports, components can shrink from their own ports along the already routed flow channels towards the ports of connected components. Second, if multiple connected graphs exist in the application, after shrinking along flow channels, there may be significant redundant gaps between connected graphs (including all components and flow channels within a single connected graph). To further optimize the overall flow layer area, this invention proposes a multi-graph shrinking strategy, which can effectively reduce area redundancy between graphs, resulting in a more compact overall structure.

[0045] 2. Specific technical steps of the algorithm:

[0046] 2.1 Logic Design:

[0047] 2.1.1 Logical Layout:

[0048] This invention implements the functions of traditional layout in two steps and proposes a new algorithm for logical layout. The goal is to first efficiently obtain a high-quality logical layout solution that is convergent, stable and has good aggregation effect, and then map the logical position of the component to the actual physical position through the method of placing specific components.

[0049] The logical space size is set to the smallest rectangle with the area that can accommodate all components and whose adjacent sides are of similar length. For example... Figure 2 As shown, firstly, each component is placed into each cell of the logical space in ascending order of its component number. Component numbers are represented by non-zero positive integers, and empty logical positions are represented by zero, thus initializing the logical space. Secondly, based on the connections between components, two swapping operations—adjacent movement and target jump—are used to achieve a clustering effect, that is, minimizing the Manhattan distance between connected component cells in the logical space. It can be seen that the logical layout does not change the size of the logical space.

[0050] like Figure 3 As shown in (a), the proximity swap operation targets components adjacent to component 6 in all four directions, and swaps their logical positions with the component unit that yields the largest net gain. The Manhattan distance between each component is only 1 unit. The net gain is the sum of the Manhattan distances between the two components and all connected components before the swap, minus the difference between the sum of the Manhattan distances between the two components and all connected components after the swap. The net gain is calculated as follows:

[0051]

[0052] Where a is an active switching component, b is a passively switching neighbor component, and the Manhattan logical distance between a and b is only 1; a_links is the number of components connected to component a, b_links is the number of components connected to component b; dir is a direction in the four cardinal directions, and dis is the Manhattan logical distance between the two components.

[0053] After calculating the net profit of all components in all four directions, swap their logical positions with the component in the direction of maximum profit. Iterate this calculation and swapping process until the net profit of all components in all four directions is less than or equal to zero. For example... Figure 3 As shown in (b), due to the order of calculations, a group of components with good aggregation effect already exists in the middle part of the figure, represented as the middle rectangular area. Since the step size of the neighbor swap is only 1, the net benefit of moving to the left for the swap is less than or equal to zero. Through the neighbor swap operation, component 32 cannot cross the middle rectangular area to get closer to the target component 6 that is connected to it. Therefore, the target jump swap operation is proposed.

[0054] Similar to the neighbor move operation, the target jump operation also evaluates the benefit based on the Manhattan distance between the connected components. First, select the edge with the largest Manhattan distance that is not locked, and assign roles to the two components according to the probability that the degree of each component at both ends of the edge accounts for the sum of their degrees. Assign the component with the higher probability as the target component and the other component as the jump component. Second, if there is an empty logical position around the target component, the jump component jumps directly to that position; if there is no empty logical position around the target component, randomly select one component from the eight surrounding components, calculate the net benefit using equation (2), and traverse in a clockwise direction until the first component with a non-negative net benefit is obtained by exchanging positions with the jump component, and then perform the jump position exchange operation; if the net benefit of exchanging positions with all surrounding components is negative, then abandon the jump. In this round, lock the edge, iterate until all edges are locked, then unlock all edges to start a new round of iteration, repeat this process until the iteration threshold is reached or there is a positive net benefit in equation (1), and end the iteration. The direct goal of the target jump is to break the benefit bottleneck and change the effect of the current component logical layout structure.

[0055]

[0056] Where edges is the total number of edges, the formula calculates the difference in Manhattan distance between the components at both ends of all edges before and after the jump action, which is the net gain of the entire logical space.

[0057] 2.1.2 Component orientation layout adjustment:

[0058] This invention proposes a stage for adjusting the component orientation layout based on the default component orientation. For example... Figure 5 As shown, the numbers in each component are their sequence numbers. In both the left and right diagrams, the logical positions of the components remain unchanged, and components 1, 2, and 25 are well-grouped next to component 19, which is connected to them. However, Figure 5 In (a), the default component layout orientation uses the left input port and the right output port. Compared to this, the component orientation layout is adjusted. Figure 5 (b) The length of the flow channel is greatly reduced, while avoiding the occurrence of Figure 5 The upper left corner of (a) is an excessively long flow channel.

[0059] This layout adjustment specifically calculates the sum of the Manhattan distances between the port and connected components in four orientations, using the direction with the minimum distance as the optimized layout orientation for the component. The logical position of a port is the same as the position of its adjacent logical unit. The logical position of the unique output port of component 2 is equal to the logical position of component 19, and the distance between them is zero. Figure 5 In (a), the distance from the unique output port of component 2 to component 19 is two units.

[0060] 2.2 Component mapping and bounding box gap layout adjustment:

[0061] 2.2.1 Bounding box strategy for placing components:

[0062] After completing the first phase of work, we obtained excellent component logical positions and directions. The next step is to map these logical positions to their actual physical positions to obtain a physical layout solution. Therefore, this invention employs a bounding box strategy to place components.

[0063] The bounding box strategy uses a uniform minimum square bounding box of equal area as a container to wrap each component, with its side length equal to the maximum size of all components in two dimensions.

[0064] like Figure 6 As shown, the numbered rectangular blocks of varying sizes in the diagram represent components, while the nine equal-sized bounding squares form bounding boxes. All components are placed in the top left corner of the bounding box by default, and the initial spacing between each bounding box is 1. It can be seen that the bounding box strategy effectively inherits the logical position and direction of components from the first stage. However, compared to smaller components, there is some redundant space inside the bounding box (represented in the diagram as the remaining space inside the bounding box excluding the components). In the third stage, a shrinking layout adjustment method will be used to further optimize the redundancy in the overall area of ​​the flow layer.

[0065] 2.2.2 Actual cabling assessment:

[0066] After placing the components, to measure the layout quality under a certain bounding box gap, the layout quality is evaluated through actual routing. The fitness value function is calculated as follows:

[0067] F=α×C+β×L+γ×A (3)

[0068] Where C is the number of flow channel intersections generated after placement and routing, L is the total length of the flow channels, and A is the overall area of ​​the flow layer. α, β, and γ are weights, with values ​​of 300, 20, and 1, respectively.

[0069] In terms of routing algorithm, this invention uses a two-stage A* algorithm to route all flow channels. In the first stage, while disallowing flow channel intersections, the algorithm aims to successfully route as many flow channels as possible. In the second stage, the restriction on flow channel intersections is lifted, and routing continues for all flow channels that failed in the previous stage until all flow channels are successfully routed. This algorithm helps reduce the number of flow channel intersections to a certain extent and also ensures the overall routing success of flow channels under relatively abundant routing resources. The routing sequence adopts a proximity principle, using the ascending order of the Manhattan distance between the components at both ends of the flow channel as the routing order. This gives shorter flow channels that consume fewer resources a higher priority for routing, helping to reserve more routing resources for subsequent flow channels, increasing the number of flow channels successfully routed in the first stage, and reducing the number of flow channel intersections. All routing-related work in this invention uses the two-stage A* routing algorithm based on this routing sequence.

[0070] 2.2.3 Layout adjustments for the gaps between the enclosure boxes:

[0071] When components are initially placed, the initial spacing between bounding boxes is set to one unit, which may result in insufficient wiring resources. To maximize the quality of the fluidic layer physical design, further layout adjustments are required. Since the sizes of components may vary significantly, directly adjusting the layout based on the component gaps makes it difficult to preserve the previously optimal logical positions of the components and ensure that connected components are well-grouped together. Therefore, this invention proposes a layout adjustment that increases the bounding box gaps.

[0072] like Figure 7 As shown, to achieve from Figure 7 (a) to Figure 7 In (b), the bounding box gap increases by only one unit per round. The iteration ends when the maximum gap threshold is reached, and the optimal bounding box gap is saved. The maximum gap threshold is positively correlated with the number of component ports in the application.

[0073] 2.3 Shrinkage Layout Adjustment:

[0074] 2.3.1 Contraction along the flow channel:

[0075] After the second phase of work was completed, considering that some components might have a significant area difference from the bounding box, there was ample wiring space within the bounding box. Furthermore, in biochip applications, the number of ports on components is small, typically single digits, or even leaf dangling point components with a degree of 1, reducing the difficulty of shrinking a single graph. Therefore, this invention proposes a new layout adjustment method: shrinking along the flow channel. Shrinking along the flow channel involves moving the dangling point component along the only connected flow channel, shortening that flow channel as much as possible while satisfying constraints, and then moving the component to the corresponding new position.

[0076] like Figure 8 As shown in the left and right images, the layout of two hanging point components has been adjusted. Figure 8 In (a), the component is in its un-shrinked state, and is placed by default in the top left corner of the bounding box. However, there is sufficient physical space to allow the hanging point component to be adjusted to a better position. Figure 8 In (b), the state of the component after it has contracted along the flow channel is shown, which is different from the state of the component after it has contracted along the flow channel. Figure 8 Compared to (a), this significantly reduces the flow channel length while avoiding the generation of a flow channel intersection.

[0077] 2.3.2 Multi-image collapse:

[0078] After shrinking along the flow channel, the connectivity structure of a single graph is optimized. However, there are two scenarios in application use cases: one containing only one connected graph and one containing multiple connected graphs. Shrinking along the flow channel only applies to a single graph; if multiple connected graphs are included, the considerable area redundancy that may exist between graphs after shrinking is ignored. To address this issue, after calculating the number of connected graphs, a new layout adjustment method is proposed: the multi-graph shrinking method. This strategy can optimize the overall area of ​​the flow layer without changing the number of flow channel intersections and the total length of the flow channel, while satisfying constraints.

[0079] The specific strategy for multi-graph shrinkage is to treat all components and flow channels in a single graph as homogeneous tiles, without changing their shape and orientation, and to move them as close as possible to the northwest direction in physical space. For example... Figure 3 As shown, if the application use case has only one connected graph, the multi-graph shrinkage stage is skipped and the final fluid layer physical design solution is directly output; if there are multiple connected graphs, the final fluid layer physical design solution is output after multi-graph shrinkage optimization.

Claims

1. A method for physical co-design of flow layers under continuous microfluidic biochips, characterized in that, The layout adjustment includes logical layout, component direction layout adjustment, bounding box gap layout adjustment, along flow channel shrinkage and multi-graph shrinkage; each component is initially placed in each cell in the logical space, and based on the connection relationship between components, two exchange operations of adjacent movement and target jump are used; through the multi-graph shrinkage strategy, a new round of layout adjustment is performed on the test case containing multiple connected graphs; The logical space is set to be an area minimum rectangle capable of accommodating all components and having similar lengths of adjacent edges; first, each component is sequentially placed in each cell in the logical space in ascending order of component serial numbers, the component serial numbers are represented by non-zero positive integers, and the empty logical positions are represented by zero, so as to realize the initialization of the logical space; second, based on the connection relationship between components, the target jump exchange operation is used to achieve the aggregation effect, that is, the Manhattan distance of the connected component cells in the logical space is small.

2. The method according to claim 1, wherein, The adjacent exchange operation is aimed at the components adjacent to the component in four directions, and the logical positions of the two components with the maximum net benefit are exchanged, and the Manhattan distance between them is only 1 unit; the net benefit is the sum of the Manhattan distances of the two components before exchange and all connected components, minus the difference between the sum of the Manhattan distances of the two components after exchange and all connected components; the net benefit is calculated as: Wherein, a is the active exchange component, b is the passive exchange adjacent component, the Manhattan logical distance of a and b is only 1; a_links is the number of components connected with component a, b_links is the number of components connected with component b; dir is a certain direction in the four directions of east, west, south and north, dis is the Manhattan logical distance between two components; is the distance gain of the active exchange component a in a certain determined dir direction; is the Manhattan distance of the active exchange component a and the component i connected with it before adjacent movement, is the Manhattan distance of the active exchange component a and the component i connected with it after adjacent movement; is the Manhattan distance of the active exchange component b and the component j connected with it before adjacent movement, is the Manhattan distance of the active exchange component b and the component j connected with it after adjacent movement; After calculating the net benefits of all components in four directions, the logical positions of the components in the direction with the maximum benefit are exchanged, and the iteration calculation and exchange process is iterated until the net benefits of all components in four directions are less than or equal to zero.

3. The method of claim 2, wherein the method further comprises: First, select the edge with the maximum Manhattan distance and not locked, and assign roles to the two components according to the probability of the degree of each component accounting for the sum of the degrees of the two components, and assign the component with the larger probability as the target component and the other component as the jump component; second, if there is an empty logical position around the target component, the jump component directly jumps to the position; if there is no empty logical position around the target component, randomly select one component from the surrounding eight components, calculate the net benefit using formula (2), and traverse in the clockwise direction until the first net benefit of the component exchanging position with the jump component is non-negative, and perform the position exchange operation of jumping; if the net benefits of all components around the exchange position are negative, give up jumping; lock the edge in this round, iterate until all edges are locked, then unlock all edges to start a new round of iteration, repeat this process until the iteration threshold is reached or there is a positive net benefit in formula (1), and end the iteration; Wherein, edges is the number of all edges, in which the difference of Manhattan distance between components at both ends of all edges before and after the jump action is calculated as the net benefit of the entire logical space; E all is the total benefit of the target jump in the entire logical space; is the Manhattan distance between the components at both ends of the connecting edge before the target jump, is the Manhattan distance between the components at both ends of the connecting edge after the target jump.

4. The method of claim 3, wherein the method further comprises: The component direction layout adjustment specifically calculates the sum of the Manhattan distances between the ports and the connected components in four directions to obtain the minimum distance direction as the optimized layout direction of the component; the logical position of the port is the same as the logical cell position adjacent to the port.

5. The method of claim 4, wherein the method further comprises: After the first stage of work is completed, the logical position and logical direction of the component are obtained, and the bounding box strategy is used to place the component; the bounding box strategy is to uniformly use an equal-area minimum square bounding box as a container to wrap each component, and the side length is equal to the maximum size of all components in two dimensions.

6. The method of claim 5, wherein the method further comprises: After placing the components, the layout quality is evaluated by actual wiring, and the calculation formula of the fitness value function F is: F=α×C+β×L+γ×A (3) Wherein, C is the number of flow channel intersection points generated after layout and routing work, L is the total length of flow channel, A is the overall area of flow layer; α, β and γ are weights, which are 300, 20 and 1 respectively.

7. The method of claim 6, wherein the method further comprises: On the routing algorithm, two-stage A* algorithm is used to route all flow channels; in the first stage, flow channels are successfully routed without allowing flow channel intersection points; in the second stage, the restriction of not allowing flow channel intersection points is removed, and all flow channels that fail to route in the previous stage are routed again until all flow channels are successfully routed. On the routing sequence, the principle of proximity is adopted, that is, the Manhattan distance between the components at both ends of the flow channel is used as the ascending order of routing sequence, so that short flow channels with less resource occupation have high priority order routing.

8. The method of claim 7, wherein the method further comprises: On the routing algorithm, after the second stage work is completed, the flow channel is contracted; along the flow channel contraction is to shorten the flow channel and move the components to the corresponding new position under the premise of meeting the constraints.

9. The method of claim 8, wherein, After the flow channel contraction, the multi-graph contraction method is used; the specific strategy of multi-graph contraction is to regard all components and flow channels in a single graph as homogeneous blocks, without changing the shape and direction of the blocks, and moving them to the northwest of the physical space. If there is only one connected graph in the application use case, skip the multi-graph contraction stage and directly output the final flow layer physical design solution. If there are multiple connected graphs, after multi-graph contraction optimization, output the final flow layer physical design solution.

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