A method for aircraft engine fault diagnosis based on intelligent chip technology

Abstract

The present invention provides an aircraft engine fault diagnosis method based on intelligent chip technology. The method extracts raw engine fault data and improves the model's generalization capability through data preprocessing. An intelligent fault diagnosis model based on a deep neural network is designed, deeply coupling the self-attention mechanism with a convolutional neural network and an LSTM network to improve fault diagnosis accuracy. After repeated testing and model parameter adjustment, an optimal intelligent fault diagnosis model is obtained. A hardware IP core is designed on an FPGA, and hardware acceleration optimization design based on loop unrolling is implemented to increase computational speed. The chip's back-end design is then completed. This application provides maintenance personnel with an intelligent aircraft engine fault diagnosis chip with high fault diagnosis accuracy, strong generalization capability, and fast computational speed, thereby improving engine safety and reliability and reducing maintenance costs and troubleshooting time.

Description

Technical Field

[0001] The present application mainly relates to the field of intelligent chip technology for fault diagnosis, and in particular to an aircraft engine fault diagnosis method based on intelligent chip technology, which can optimize processing and intelligently analyze the original fault data of complex control systems such as aircraft engines, automobile engine electronics, and similar industrial equipment, determine the complex relationship between key data information and various fault symptoms, and achieve accurate and rapid fault diagnosis. Background Art

[0002] Aircraft engines are the core systems of aircraft, and their operational stability and reliability directly impact operational safety. An engine failure can, at best, reduce operational efficiency and cause economic losses, while at worst, it can lead to serious safety incidents and significant financial losses. Therefore, accurate and rapid diagnosis of aircraft engine faults can effectively improve reliability and maintainability, enhance the scientific nature of maintenance decisions, and is crucial for ensuring safe and reliable aircraft operation. It is also crucial for reducing operating costs, shortening maintenance cycles, and improving economic efficiency.

[0003] The relationship between aircraft engine fault symptoms and causes often exhibits a nonlinear and complex relationship. Deep Neural Networks (DNNs), with their fault-tolerance, adaptability, and self-learning capabilities, can effectively represent arbitrary functional relationships. Therefore, in a data-driven environment, using DNNs for intelligent fault diagnosis and determining the nonlinear mapping between fault symptoms and causes is a promising technology approach.

[0004] However, existing DNN-based fault diagnosis solutions do not fully consider that different sensors contain different fault information. When processing data, key data features are missed, resulting in low fault diagnosis accuracy and insufficient generalization ability of the algorithm model. In addition, these solutions do not fully consider the characteristics of each layer of DNN (including convolutional layers, activation functions, fully connected layers, pooling layers, etc.), fail to perform targeted hardware design optimization, and have the problem of slow computing speed.

[0005] Lei et al. [1] proposed a wind turbine fault diagnosis method based on long short-term memory (LSTM) combined with convolutional neural network (CNN). However, it only considered the use of convolution to extract features at a single scale, and the model generalization ability was not high. Downs et al. [2]Proposed an end-to-end multi-scale incentive attention convolutional neural network for motor fault diagnosis, but only used the traditional attention weighting module, which only noticed the relationship between the source data sequence and the target data sequence, but did not pay attention to the relationship between their internal data; Google Machine Translation Team [3] A self-attention mechanism (SAM) has been proposed. It not only addresses the internal relationships between source or target data sequences but also adds the relationships within the source data sequence to those within the target data sequence, thereby capturing the interrelationships between the two. However, incorporating the self-attention mechanism into an intelligent fault diagnosis model for aircraft engines requires consideration of key parameters such as channel and time information of the original aircraft engine fault data.

[0006] The deep neural network computing platform based on application-specific integrated circuit (ASIC) has the advantages of fast operation speed and low power consumption. However, in order to verify the function of ASIC chip in advance, it is usually necessary to implement it in hardware on field-programmable gate array (FPGA). Ma et al. [4] The use of loop splitting and loop tiling techniques to achieve FPGA-based convolutional neural network acceleration, but there is a problem of low hardware efficiency. [5] Parallel computing circuits were designed to increase network computing speed, but this approach focused solely on optimizing the parallel computing of the convolutional layer's intellectual property (IP) cores, ignoring the specific characteristics of other IP cores, such as activation functions, fully connected layers, and pooling layers. This leaves room for design optimization. Furthermore, this parallel computing approach is suitable for object detection in images but not for aircraft engine fault diagnosis.

[0007] Therefore, it is necessary to design a deep neural network model that can comprehensively consider the characteristics of raw fault data under different sensors and different working conditions, so as to improve the accuracy and generalization ability of aircraft engine fault diagnosis; and for the hardware implementation of this model, combining the characteristics of convolutional layers, activation functions, fully connected layers, pooling layers, etc., a hardware acceleration optimization technology based on loop unrolling is proposed to accelerate the computing speed of the intelligent fault diagnosis chip and improve the timeliness of fault diagnosis.

[0008] References:

[0009] [1] Lei J, Liu C, Jiang D. Fault diagnosis of wind turbine based on longshort-term memory networks[J]. Renewable Energy, 2019,133:422-432.

[0010] [2] Tang Si, Chen Xinchu, Zheng Song. Motor bearing fault diagnosis based on attention and multi-scale convolutional neural network[J]. Electrical Technology, 2020, 21(11): 32-38.

[0011] [3]Vaswani A,Shazeer N,Parmar N,et al.Attention Is All You Need[C].Advances in neural information processing systems,2017,5998-6008.

[0012] [4]Ma Y, Suda N, Cao Y, et al. Scalable and modularized RTL compilation of convolutional neural networks onto FPGA[C]. 2016 26th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2016: 1-8.

[0013] [5] Mei Zhiwei, Ding Xingjun, Liu Jinpeng. Accelerated design of YOLOv3-tiny convolutional neural network based on FPGA[J]. Ship Electronic Countermeasures, 2022, 45(2): 81-88,108. Summary of the Invention

[0014] 1. Purpose of the invention:

[0015] The purpose of this application is to address the shortcomings of the above-mentioned existing fault diagnosis technologies and provide an aircraft engine fault diagnosis method based on intelligent chip technology. This application first performs pre-processing operations such as visualization analysis, normalization, and exponential weighted smoothing on the raw fault data accumulated during aircraft engine operation to improve the model's generalization ability. Then, a DNN-based intelligent fault diagnosis model is designed, deeply coupling the SAM with the CNN and LSTM networks to extract the relationship between each sensor parameter and the amount of decay information under different operating conditions, thereby improving the model's fault diagnosis accuracy. Then, after training and debugging, the optimal intelligent fault diagnosis model is obtained, and the model weight parameters are extracted and saved. Then, the hardware implementation of the optimal intelligent diagnosis model is completed on the FPGA, and hardware acceleration design optimization based on loop unrolling is performed to speed up the calculation speed. Finally, the chip back-end design work is completed, realizing an aircraft engine intelligent fault diagnosis chip with high fault diagnosis accuracy and fast calculation speed.

[0016] 2. Technical solution:

[0017] To achieve the above objectives, this application will be implemented using the following technical solutions:

[0018] A method for diagnosing aircraft engine faults based on intelligent chip technology comprises the following steps:

[0019] Step 1: obtaining raw fault data of an aircraft engine during operation, the raw fault data being collected by a sensor; performing a first preprocessing on the raw fault data to obtain second fault data; the first preprocessing includes visual analysis, marking fault labels, and data set division; the data set division includes a training set, a test set, and a validation set;

[0020] Step 2: Using kernel density estimation, perform a data set distribution consistency analysis on the second fault data described in step 1 to obtain third fault data; the third fault data has eliminated data with inconsistent data features to ensure that the data of the validation set and test set described in step 1 cover the key data features of the training set data;

[0021] Step 3: performing a second preprocessing on the third fault data in step 2 to obtain fourth fault data; the second preprocessing includes normalization processing based on system operating conditions and exponential weighted smoothing processing;

[0022] Step 4: Design an intelligent fault diagnosis model based on a deep neural network. The intelligent fault diagnosis model consists of two parts: the first part uses a first convolution kernel to extract local data features, and the second part uses a second convolution kernel to extract global data features. Each part includes an input layer, a CNN module, a SAM module, an LSTM module, and a fully connected layer.

[0023] Step 5: Use the training set and validation set of the fourth fault data described in step 3 as input data for the intelligent fault diagnosis model described in step 4. During model training, sparse classification cross entropy is used as the loss function, Adam is used as the optimizer, and accuracy is used as the evaluation indicator of the training model. Perform multiple model training and hyperparameter adjustments to determine the network's structural depth, the number, size, and step size of the convolution kernels, the number of neurons, and the activation function, and obtain a preliminarily optimized intelligent fault diagnosis model.

[0024] Step 6: Use the test set of the fourth fault data described in step 3 as the input of the preliminarily optimized intelligent fault diagnosis model described in step 5 to perform a test, and return to step 5 again to adjust the model hyperparameters according to the output results until the model output results meet the expected error standard acceptance criteria, and finally obtain the optimal intelligent fault diagnosis model, and save the weight parameters of the optimal intelligent fault diagnosis model;

[0025] Step 7: Design an FPGA-based hardware IP core using the optimal intelligent fault diagnosis model described in step 6 in the design software; the hardware IP core design includes code design for a convolution calculation IP core, a pooling calculation IP core, an activation function IP core, and a fully connected calculation IP core;

[0026] Step 8: Performing hardware acceleration optimization design based on loop unrolling on the hardware IP core described in step 7, and performing verification and synthesis to obtain an optimized circuit file; the hardware acceleration optimization design based on loop unrolling includes loop unrolling of the computation code for the convolutional layer, activation function, fully connected layer, and pooling layer, and optimizing the corresponding computation circuit design;

[0027] Step 9: Perform chip back-end design work such as testability design, layout planning, clock tree synthesis, routing, parasitic parameter extraction, and layout physical verification on the circuit file described in step 8 to realize an intelligent fault diagnosis chip for aircraft engines with high fault diagnosis accuracy and fast calculation speed.

[0028] The specific steps described in step 1 are as follows:

[0029] The raw fault data described in 1.1, i.e., various types of fault data collected by multiple different types of sensors, including aircraft engine temperature state parameters, pressure state parameters, speed state parameters, bleed air flow parameters, and lubricating oil detection parameters, are used as input data for the intelligent fault diagnosis model based on the deep neural network;

[0030] 1.2 Data Visualization: Using Python, we visualize the sensor data for each fault. We analyze the data trends, remove parameters that do not affect system performance, and retain parameters that contain fault information as input for model training.

[0031] 1.3 Set fault labels for the data in 1.2 above according to the fault type:

[0032] Various types of fault labels are set in the form of digital codes: [0, 1, 2, . . . , 5], where 0 represents the fault label when the aircraft engine is operating normally, 1 represents the fault label when the aircraft engine temperature parameter is abnormal, 2 represents the fault label when the aircraft engine pressure state parameter is abnormal, 3 represents the fault label when the aircraft engine speed state parameter is abnormal, 4 represents the fault label when the aircraft engine bleed air flow parameter is abnormal, and 5 represents the fault label when the aircraft engine lubricating oil detection parameter is abnormal;

[0033] 1.4 Divide the data that has been visually analyzed and labeled with fault labels into 10 equal parts, ensuring that the amount of data in each part is the same. Randomly select 6 parts as the training set, and then randomly select 2 parts from the remaining 4 parts as the validation set. Finally, the remaining 2 parts are the test set.

[0034] The kernel density estimation described in step 2 is to estimate the probability density function of the given data. After the kernel density distribution analysis is performed, the data distribution consistency of the validation set, test set and training set is ensured to ensure the consistency of the data features in each data set. Taking one-dimensional data as an example, suppose there are n data: x1, x2, x3, ..., x n , the probability density function of the data is f(x).

[0035] The kernel density function formula is:

[0036]

[0037] where x i represents the i-th data, n is the amount of data, f(x i ) is the probability density function of the ith data, and h is the bandwidth in the kernel density estimation.

[0038] The specific steps of performing the second preprocessing of the data described in step 3 are as follows:

[0039] 3.1 Normalize the data based on the aircraft engine operating conditions to eliminate the impact of dimension and enhance data stability. Since a certain fault may exist under different operating conditions, the data at this time will show different data characteristics due to different operating conditions. In order to better extract the change characteristics of the data, it is necessary to classify the fault data under the same operating conditions and then perform normalization. The formula is:

[0040]

[0041] where x i Represents a data sample (x1, x2, x3, ..., x n ) in the i-th data, X i ∈[0,1] and dimensionless, for x i After normalization, the data x j Represents a data sample (x1, x2, x3, ..., x n ) in the jth data, max 1≤j≤n {x j} for x1, x2, x3, …, x n The maximum value, min 1≤j≤n {x j} for x1, x2, x3, …, x n The minimum value in ;

[0042] 3.2 Since the original fault data contains a lot of noise, in order to improve the accuracy of the data and increase the generalization ability of the model, it is necessary to perform exponential weighted smoothing on the data to filter out the noise interference in the data. The formula is as follows:

[0043] G(t)=α*g(t)+(1-α)*G(t-1)

[0044] Where G(t) is the value of g(t) at the current moment after smoothing, g(t) is the data value collected by a certain sensor at the current moment, G(t-1) is the result of smoothing at the previous moment, and α is the intensity of smoothing, which ranges from 0 to 1.

[0045] The design structure of the intelligent fault diagnosis model based on deep neural network described in step 4 is as follows:

[0046] 4.1 The input layer of the model mainly takes all sensor data of the system t cycles as the input of the model;

[0047] 4.2 After the input layer, the convolutional neural network (CNN) module is connected. This module consists of two one-dimensional convolutional layers and a maximum pooling layer. A Dropout layer is added between each convolutional layer to prevent overfitting, and its output coefficient is 0.3. The configuration parameters of the two convolutional layers are the same. To ensure that the output feature size remains unchanged after the convolution operation, the height of the convolution kernel is 3, the number is 128, the moving step is 1, and all zeros are padded. The activation function uses ReLU to achieve nonlinear mapping of different features. The pooling layer size in each combination is 2, and the other configurations are the default values ​​to halve the size of the output features. The output size of the final module is S*N, where N is the feature dimension, which is equal to the number of convolution kernels in the last convolutional layer. S is the length of the output sequence. When the convolution kernel moving step is 1, its calculation formula is as follows:

[0048] S=W-H+1

[0049] Where W is the sequence length of the input data, and H is the height of the convolution kernel;

[0050] 4.3 Then the output data of the CNN module is input into the self-attention mechanism SAM module. First, the output of the CNN module is integrated with global maximum pooling and global average pooling, and the output size after global pooling is N. Then, the same two-layer perceptrons are used to learn the N features of the global pooling output to obtain the relationship and information between them. To ensure that the output size of the perceptron is still N, the number of neurons in the second layer must be the same as the output dimension of the CNN module. Then, the outputs of the two perceptrons are merged by element-wise summation, and the sum is normalized by the Softmax function to obtain the attention weight α of different features. N . Secondly, because the dilation rate is used in the dilation convolution to increase the spacing between values ​​when the convolution kernel processes data, the receptive field is expanded, which is beneficial for the extraction of long-distance information. Therefore, two dilation convolutions are used to extract important information from the output of the CNN module. To ensure that the output size after convolution remains unchanged, the size, moving step, and padding of the convolution kernel are the same as those of the CNN module. The number of convolution kernels is the feature dimension of the input data, and the dilation rate is 3. The Softmax function is then used for normalization to obtain the self-attention weight β of the input sequence. S . Then compare it with the obtained S*α N N is multiplied to obtain running loops of different importance;

[0051] 4.4 Connect the Long Short-Term Memory (LSTM) module to the SAM module. The LSTM module has an LSTM layer with 128 neurons per gate and a Tanh activation function, enabling the fault diagnosis network model to promptly learn the temporal information in the data features. To reduce the prediction model's sensitivity to small changes in the data, a Dropout layer with a node output coefficient of 0.2 is added after the LSTM layer. 20% of the neurons in the LSTM layer are assigned zero weights to prevent overfitting and further improve the accuracy of the intelligent fault diagnosis model.

[0052] 4.5 Finally, a fully connected layer is connected after the LSTM module to perform regression analysis on the information extracted by the previous modules. Since the model has multi-scale input, the analysis results of different parts are summed and averaged as the final fault diagnosis result. The calculation formula for each neuron in the fully connected layer is as follows:

[0053]

[0054] in is the output of the dth neuron in the lth layer, F is the activation function, z l-1 is the number of neurons in the l-1 layer, is the weight of the cth neuron in the l-1th layer in the lth layer, is the output of the cth neuron in the l-1th layer, is the bias of the dth neuron in the lth layer.

[0055] The specific steps of training the model, adjusting the hyperparameters, and obtaining the diagnostic model described in step 5 are as follows:

[0056] 5.1 The training set and validation set of the data are used as inputs to the intelligent fault diagnosis model. The validation set is input into the model after the training set is completed to verify the generalization ability of the model.

[0057] 5.2 The loss function during model training uses sparse classification cross entropy, and its formula is as follows:

[0058]

[0059] Where m is the total number of samples, k is the number of fault categories, and p ek is the true probability of the kth type of failure occurring in the eth sample, q ek is the predicted probability of the kth type of failure occurring in the eth sample;

[0060] 5.3 The optimizer used for model training is Adam, and accuracy is used as the network evaluation indicator;

[0061] 5.4 After setting the above points, compile the model and perform repeated iterative training to determine the following hyperparameters:

[0062] The structural depth of the intelligent fault diagnosis model based on deep neural networks, the number, size and step size of convolution kernels, the dropout coefficient, the number of neurons and activation function, the number of iterations, the number of batches fed into the model each time, the smoothing strength of the summand weighted smoothing process, and the width of the input data;

[0063] During the training process, you can output the loss values ​​of the test set and validation set for each iteration to determine whether the model is overfitting. Combined with the accuracy analysis of each fault classification result, you can determine whether you need to return to step 5.4 to adjust the hyperparameters. After repeated debugging, you can achieve the best fault classification results.

[0064] The specific steps described in step 6 are as follows:

[0065] Input the test set data into the initially optimized intelligent fault diagnosis model to further verify the model's generalization capabilities. If the classification results for the test set are unsatisfactory and fail to meet the expected error acceptance criteria, this indicates that there are still problems with model training, possibly underfitting or overfitting. Return to steps 5.4-5.5 and retrain and debug. Once the output results for the test set meet the requirements, the final optimal model is obtained and the model weights are saved.

[0066] The specific steps for hardware IP core design described in step 7 are as follows:

[0067] 7.1 Use the Vivado HLS tool to create project projects corresponding to the convolution calculation IP, pooling calculation IP, activation function IP, and fully connected calculation IP, and use the C language to implement the functions of each of the above IPs;

[0068] 7.2 Select the FPGA chip model, first design the convolution calculation IP core, define the convolution kernel function, declare the weight array, input array, output array, and bias array, and write the convolution algorithm code;

[0069] 7.3 Design the pooling calculation IP to implement 2x2 max pooling. Declare that the cache array is used to cache the comparison results. Use three cache arrays to perform pairwise comparisons on the input data. After storing the data in two sets of cache arrays, perform a second comparison in the second clock cycle and store the final results in the third cache array.

[0070] 7.4 Design the activation function IP, which mainly declares the cache array used to store the comparison results, compares the input array elements with 0 one by one, and stores the results in the cache array;

[0071] 7.5 Design the fully connected computing IP, declare the input array, output array, weight array, and bias array used by the fully connected layer, and write the corresponding fully connected layer algorithm code;

[0072] 7.6. Add AXI interface declaration code during code writing so that the IP core with AXI interface is automatically generated during HLS synthesis, so that the parameters of each IP core function can be transmitted using the AXI bus interface;

[0073] 7.7 Add HLS preprocessing instructions to the core calculation or comparison code in each IP core code, and add array splitting instructions to the declared arrays to achieve pipeline and parallel operations of calculations during HLS synthesis.

[0074] The specific steps described in step 8 are as follows:

[0075] 8.1 Analysis of the convolution layer loop code. A typical convolution operation can be viewed as a multiplication-accumulation operation with six layers of nested for loops. The loop factors are cho, chi, row, col, kr, and kc (cho represents the output feature map channel, row and col represent the output feature map size, chi represents the input feature map size, and kr and kc represent the convolution kernel size). The three arrays involved in the operation are the three-dimensional data out[chout][R][C] (output data), the four-dimensional array weights[chout][chin][K][K] (weight parameters), and the three-dimensional array input[chin][S*R+K][S*C+K] (input data).

[0076] 8.2 After theoretical analysis, the input feature map channel and the output feature map channel are selected as the loop expansion parameters of the convolution layer;

[0077] 8.3 In view of the parallel calculation of the input feature map channels and output feature map channels of the convolution layer, a multiplication-accumulation array circuit is designed to realize the parallel multiplication-accumulation operation of multiple groups of data after the loop is expanded. For the multiplication-accumulation processing element unit (PE), each PE unit can complete the convolution operation of multiple groups of input feature map channels of an output feature map channel. If the parallel convolution operation of the output feature map channel is to be realized, a multiplication-accumulation array composed of multiple PEs is required to complete it. In the array, the storage module that stores the input feature map input must transmit the elements of multiple input channels to multiple PE units at the same time, that is, the input feature map data received by each PE is the same, so the storage module of the input feature map is still split according to the input channel;

[0078] 8.4 Analysis of activation function code. Since the ReLU activation function only involves comparison with the value 0, the hardware only needs to implement a comparator. Unlike other activation functions, which require a lookup table to implement complex exponential or even logarithmic calculations, this application mainly uses the ReLU activation function and, based on its characteristics, chooses to perform loop expansion on the output feature map channels.

[0079] 8.5 Analyze the fully connected layer calculation code. Since the input and output dimensions of the fully connected layer are both 1, the data input to the fully connected layer is already one-dimensional data. Therefore, the essence of the fully connected layer is to change the array size to an array that meets the requirements through matrix multiplication and finally output it. Therefore, for the fully connected layer, the output feature channel is loop expanded;

[0080] 8.6 Analyze the calculation code of the pooling layer. Since the output feature map size of the pooling layer will continue to change as the pooling layer goes deeper, we choose to expand the output feature size loop;

[0081] 8.7 Verification includes C code functional verification and IP core post-synthesis verification. C code verification involves writing the main verification function, i.e., the testbench function. This function calls the IP core designed in step 7 according to the previously designed neural network model, constructs the corresponding model, and imports the pending fault data and saved model parameters for verification.

[0082] 8.8 After functional verification of the C code, perform IP core synthesis, followed by C&RTL joint simulation. After verification, obtain the circuit file that can be used for chip back-end design.

[0083] The specific steps described in step 9 are as follows:

[0084] 9.1 Design for Test (DFT) involves inserting scan chains into the circuit file described in step 8, converting non-scan cells (such as registers) into scan cells. The software tool used is Synopsys' DFTCompiler.

[0085] 9.2 Floorplanning involves placing the macrocell modules required for the chip in the circuit file. This generally determines the placement of various functional circuits, such as IP modules, RAM, I / O pins, etc. This directly affects the final chip area. The software tool used is Synopsys' Astro.

[0086] 9.3 Clock Tree Synthesis (CTS) involves properly routing the clocks in the circuit file so that they are symmetrically connected to each register unit. This minimizes the difference in clock delay when the clocks arrive at each register from the same clock source. The software tool used is Synopsys' Physical Compiler.

[0087] 9.4 Place & Route is to complete the routing of common signals in the circuit file, including the routing between various standard cells (basic logic gate circuits). The software tool used is Synopsys' Astro.

[0088] 9.5 Parasitic parameter extraction is necessary because the inherent resistance of the wire, the mutual inductance between adjacent wires, the coupling capacitance, etc., can generate signal noise, crosstalk, and reflections within the chip, causing signal voltage fluctuations and variations. If severe, this can lead to signal distortion and errors. Therefore, parasitic parameter extraction is necessary for further analysis and verification to resolve signal integrity issues. The software tool used is Synopsys' Star-RCXT.

[0089] 9.6 Layout physical verification is the functional and timing verification of the physical layout after wiring is completed, including comparison and verification of the layout with the gate-level circuit diagram after logic synthesis, design rule checking (checking whether the connection spacing, connection width, etc. meet the chip process requirements), and electrical rule checking (checking for electrical rule violations such as short circuits and open circuits). The software tool used is Hercules from Synopsys.

[0090] 9.7 After completing the chip back-end design, the GDS II file can be handed over to the chip foundry to complete the chip manufacturing, packaging and testing work, thereby realizing the aircraft engine intelligent fault diagnosis chip designed in this embodiment with high fault diagnosis accuracy and fast calculation speed.

[0091] 3. Beneficial effects:

[0092] Compared with the existing technology, the aircraft engine fault diagnosis method based on intelligent chip technology proposed in this application can produce the following beneficial effects:

[0093] (1) In step 4, SAM is deeply coupled with CNN and LSTM networks to design and implement an intelligent fault diagnosis model with high fault diagnosis accuracy and strong generalization ability. The SAM module designed in this application can focus on the relationship between various sensor parameters and the amount of decay information under different operating conditions. It can not only obtain different importance weights of input data features to highlight important decay information in sensor parameters and suppress unimportant information, but also obtain importance weights in different states to highlight decay information when system performance degrades and reduce the impact when the system is in normal state.

[0094] (2) Step 8 meticulously analyzes the algorithm code for the convolutional layer, activation function, fully connected layer, and pooling layer, and proposes a hardware acceleration optimization design method based on loop unrolling. This method improves the computational speed of the aircraft engine intelligent fault diagnosis chip with minimal hardware resource consumption. For the convolutional layer, loop unrolling is performed on the input and output feature map channels, and a dedicated multiplication-accumulation array circuit is designed to implement parallel computing. For the activation function and fully connected layers, loop unrolling is performed on the output feature map channels. For the pooling layer, loop unrolling is performed based on the output feature size selected based on the algorithm characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 This is a flow chart for the design of an intelligent fault diagnosis chip for aircraft engines in this application.

[0096] Figure 2 This is a structural diagram of the intelligent fault diagnosis model based on deep neural network in this application.

[0097] Figure 3 This is the SAM module structure diagram in this application.

[0098] Figure 4 Schematic diagram of the multiplication-accumulation array used to implement parallel computing in this application.

[0099] Figure 5 This is the structural diagram of the aircraft engine intelligent fault diagnosis chip in this application. DETAILED DESCRIPTION

[0100] In order to better explain this application, a detailed description will be given below with reference to the accompanying drawings.

[0101] Figure 1The key process of designing an intelligent fault diagnosis chip for aircraft engines in this application is as follows: first, the original fault data of the aircraft engine is preprocessed for the first time (including visual analysis, marking fault labels, and data set division), and then the data set distribution consistency analysis, normalization, and exponentially weighted smoothing are performed to obtain the processed training set, test set, and validation set; then, an intelligent fault diagnosis model based on a deep neural network is designed, and the training set and validation set are input into the model. After multiple model training and hyperparameter adjustments, a preliminarily optimized intelligent fault diagnosis model is obtained; the test set is input into the preliminarily optimized intelligent fault diagnosis model to determine whether the model output meets the expected error accuracy acceptance criteria. If not, the model hyperparameters need to be further adjusted until they meet the requirements to obtain the optimal intelligent fault diagnosis model; then, the hardware IP core is designed for the optimal intelligent fault diagnosis model, and an optimization design based on loop unrolling is implemented; finally, the chip design work is completed to obtain an intelligent fault diagnosis chip.

[0102] Combine Figure 1 The design flow chart of the aircraft engine intelligent fault diagnosis chip builds an aircraft engine intelligent fault diagnosis model based on a deep neural network. The specific implementation steps are as follows:

[0103] Step 1: Obtain original fault data during aircraft engine operation, the original fault data being collected by sensors of the aircraft engine; perform a first preprocessing on the original fault data to obtain second fault data; the first preprocessing includes visual analysis, marking fault labels, and data set division; the data set division includes a training set, a test set, and a validation set.

[0104] Various fault data collected by sensors during engine operation are collected as raw fault data for the intelligent fault diagnosis model. The data collected by the sensors includes engine temperature, pressure, speed, bleed air flow, and lubricating oil parameters. These data are used as input data for the intelligent fault diagnosis model based on a deep neural network.

[0105] The visualization analysis described above uses Python language to perform data visualization operations, that is, to intuitively represent the sensor data of each fault in a visual form, analyze the changing trend of the data, eliminate the sensor data that does not contain fault information, and retain the data containing fault information as the input of model training.

[0106] The fault labels are digitally coded to represent various types of faults. The labels are [0, 1, 2, ..., 5], where 0 represents the fault label for normal engine operation, 1 represents the fault label for abnormal engine temperature parameters, 2 represents the fault label for abnormal engine pressure state parameters, 3 represents the fault label for abnormal engine speed state parameters, 4 represents the fault label for abnormal engine bleed air flow parameters, and 5 represents the fault label for abnormal engine oil detection parameters. This method maps complex engine fault types to corresponding numbers, making it easier for maintenance personnel to promptly identify the specific fault in the aircraft engine.

[0107] The data set division mentioned above refers to dividing the data that has been visually analyzed and marked with fault labels, that is, dividing all the data into 10 parts on average, ensuring that the amount of data in each part is the same, randomly selecting 6 parts as training sets, and then randomly selecting 2 parts from the remaining 4 parts as validation sets, and finally the remaining 2 parts as test sets. The training set is used to train the intelligent fault diagnosis model based on deep neural networks, the validation set is used to determine the network structure of the model and adjust the hyperparameters, and the test set is used to detect whether the finally designed intelligent fault diagnosis model has achieved the expected design goals. The purpose of evenly dividing all the data into 10 parts is to ensure that the amount of data contained in each part is the same, so the data features contained in each part are also similar. The training model requires the most data, so the training set accounts for the largest proportion, followed by the validation set and the test set. The ratio between them is 6:2:2, which meets the needs of deep neural network model training, verification, and testing.

[0108] Step 2: Use kernel density estimation to perform a data set distribution consistency analysis on the second fault data described in step 1 to obtain third fault data; the third fault data has eliminated data with inconsistent data features to ensure that the data of the validation set and test set described in step 1 cover the key data features in the training set data.

[0109] Before designing an intelligent fault diagnosis model based on a deep neural network, it is necessary to perform a distribution consistency analysis on the training set, validation set, and test set in the data set to ensure that the three subsets maintain the same data characteristics in the data composition. If the data of the validation set and the training set are similar to the training data in distribution, the generalization effect of the model will be better, that is, it will have better adaptability to data that has not appeared. Of course, it is not required to be exactly the same as the distribution of the training data, but it should not be too different from the training data. This application uses kernel density estimation to detect whether the distribution of the training set and the test set is consistent.

[0110] The kernel density estimation is to estimate the probability density function of the given data. The validation set, test set and training set divided by kernel density distribution analysis are consistent with the data distribution in the training set. Taking one-dimensional data as an example, suppose there are n data: x1, x2, x3, ..., x n , the probability density function of the data is f(x). The kernel density function formula is:

[0111]

[0112] where x i represents the i-th data, n is the amount of data, f(x i ) is the probability density function of the ith data, and h is the bandwidth in the kernel density estimation.

[0113] Using the data visualization analysis described in step 1, we can intuitively detect whether the distribution of each parameter in the training set is consistent with the distribution of each parameter in the test set. That is, the probability density curve distribution is relatively consistent, indicating that the test set data covers the features in the training set data, further ensuring the generalization ability of the constructed model.

[0114] Step 3: perform a second preprocessing on the third fault data in step 2 to obtain fourth fault data; the second preprocessing includes normalization processing based on system operating conditions and exponential weighted smoothing processing.

[0115] Analysis of the various sensor parameters in the dataset reveals significant disparity between them. Large-dimensional data can dominate the predictions of deep neural network models, rendering smaller-dimensional data ineffective and leading to poor model predictions. Furthermore, the presence of outliers in the data can increase network model training time and potentially prevent the model from converging. Therefore, normalization of the input data to the model is necessary to eliminate the influence of dimensionality and outliers in the parameters.

[0116] Since a certain engine fault may exist under different operating conditions, the data at this time will have different characteristics due to different operating conditions. In order to better extract the change characteristics of the data, it is necessary to classify the fault data under the same operating conditions and then perform normalization processing. The formula is:

[0117]

[0118] where x i Represents a data sample (x1, x2, x3, ..., x n ) in the i-th data, X i ∈[0,1] and dimensionless, for x i After normalization, the data x j Represents a data sample (x1, x2, x3, ..., x n) in the jth data, msx 1≤j≤n {x j} for x1, x2, x3, …, x n The maximum value, min 1≤j≤n {x j} for x1, x2, x3, …, x n The minimum value in .

[0119] However, simply normalizing the state parameters monitored by the sensors does not reflect the actual operating conditions of the engine. In most literature, researchers do not consider this and simply perform simple normalization on each dataset, eliminating the operating condition information in the dataset as useless information.

[0120] Therefore, in condition-based normalization, all monitoring records for different operating conditions are first categorized as a benchmark for data processing under the same operating conditions. The sensor parameters are then scaled using the normalization operation described above. This ensures that the parameters under different operating conditions are somewhat aligned, making them comparable. This approach is particularly effective when sensor data exhibit similar behavior but are centered around different means.

[0121] Since the original data contains a lot of noise, in order to improve the accuracy of the data, it is necessary to perform exponential weighted smoothing on the data to filter out the noise interference in the data. The formula is as follows:

[0122] G(t)=α*g(t)+(1-α)*G(t-1)

[0123] Where G(t) is the value of g(t) at the current moment after smoothing, g(t) is the data value collected by a certain sensor at the current moment, G(t-1) is the result of smoothing at the previous moment, and α is the intensity of smoothing, which ranges from 0 to 1.

[0124] After normalizing the data based on operating conditions, exponentially weighted smoothing was used to remove noise. Setting the smoothing weight to 0.4 significantly reduced data fluctuations while preserving the data's characteristics, effectively reducing noise. Testing the data before and after processing revealed that the root mean square error (RMS) of the intelligent fault diagnosis model on the denoised test set was 18.1% lower than on the unprocessed test set.

[0125] Figure 2The structure of the intelligent fault diagnosis model based on deep neural network designed by this application is shown. The model consists of an input layer, a CNN module, a SAM module, an LSTM module, and a fully connected layer. The input layer is responsible for transmitting the fault data to the subsequent modules; this application uses a small 3*3 convolution kernel to extract the local features of the fault data, and a large 7*7 convolution kernel to extract the global features of the fault data. The CNN module consists of a convolution layer-Dropout layer-convolution layer-maximum pooling layer; in order to extract the relationship between the parameters of each sensor and the amount of decay information under different operating conditions, a SAM module is designed to further process the output data of the CNN module; the LSTM module is used to capture the time information features in the fault data. The module consists of an LSTM layer-activation function-Dropout layer; the fully connected layer is responsible for performing regression analysis on the extracted information of the previous modules, converting the output data of the LSTM module into one dimension, and outputting the fault diagnosis result after passing through the activation function, summing, and averaging.

[0126] Combine Figure 2 Based on the structure diagram of the aircraft engine intelligent fault diagnosis model of deep neural network, a multi-scale CNN-SAM-LSTM intelligent fault diagnosis model is designed. The specific steps are as follows:

[0127] Step 4: Design an intelligent fault diagnosis model based on a deep neural network; the intelligent fault diagnosis model consists of two parts, the first part uses the first convolution kernel to extract local data features, and the second part uses the second convolution kernel to extract global data features; each part includes an input layer, a CNN module, a SAM module, an LSTM module and a fully connected layer.

[0128] The first convolution kernel is a small kernel, which can better extract local information. The size of the small convolution kernel selected in this application is 3*3. The second convolution kernel is a large kernel, which is more suitable for data with a wider information distribution. The size of the large convolution kernel selected in this application is 7*7. The size of the CNN's receptive field of view is determined by the size of the convolution kernel, which determines the extraction of important information. It is generally believed that small convolution kernels can better extract local information than large convolution kernels. However, for raw engine fault data, the information changes continuously with the operating conditions. At the beginning of operation, the data recorded by each sensor is very stable for a long period of time, and the data does not contain any degradation information. However, as the aircraft engine's service life increases, the occurrence of faults will cause the performance of the aircraft engine to deteriorate, and the monitoring data will contain more and more degradation information. Moreover, the data monitored by different sensors will show different characteristics. Therefore, the raw engine fault data has the characteristic of a more global distribution. To combine the strengths of large and small convolution kernels, this application uses convolution kernels of different sizes to establish a multi-channel model when designing a DNN-based intelligent fault diagnosis model.

[0129] The input layer mainly uses all sensor data of the system t cycles processed by steps 1 to 3 as input to the DNN-based intelligent fault diagnosis model.

[0130] The CNN module is connected after the input layer. This module consists of two convolutional layers combined with a max pooling layer, with a dropout layer added between each convolutional layer to prevent overfitting. The configuration parameters of the two convolutional layers are the same. To ensure that the output feature size remains unchanged after the convolution operation, the convolution kernel has a stride of 1 and uses all zero padding. The activation function uses ReLU to achieve nonlinear mapping of different features. The pooling layer size in each combination is 2, and all other configurations are default values ​​to halve the size of the output features. The final output size of the CNN module is S*N, where N is the feature dimension, equal to the number of convolution kernels in the last convolutional layer, and S is the length of the output sequence.

[0131] When the convolution kernel movement step is 1, the calculation formula for the convolution module output data is as follows:

[0132] S=W-H+1

[0133] Among them, W is the sequence length of the input data, and H is the height of the convolution kernel.

[0134] Then the output data of the CNN module is input into the SAM module, whose structure is as follows Figure 3 shown.

[0135] Figure 3 The structure of the self-attention mechanism (SAM) module designed in this application is shown. This module processes the output data of the CNN module through global maximum pooling and global average pooling, sums the two, and then passes it through the Softmax function to obtain the attention weights of different features. This weight is then multiplied by the output data of the CNN module. In addition, the module also processes the output data of the CNN module through two dilated convolutions and the Softmax function to obtain the self-attention weights of the input sequence. This weight is then multiplied by the above calculation result to obtain the output data of the SAM module.

[0136] The output of the CNN module consists of a multi-sensor parameter sequence. Each column of feature data in each sequence represents a parameter, monitored by different sensors during engine operation. Different faults lead to varying degrees of engine performance degradation, and the degradation information contained in the monitoring data will also vary. For the same fault, the sensor associated with it will contain important degradation information, while the parameters monitored by other sensors may contain only a small amount of useful information.

[0137] Therefore, this application designs a SAM module between different monitoring parameters, that is, a self-attention mechanism module, to identify the differences in different monitoring parameters of the engine, highlight the important degradation information therein, and obtain the importance weights in different states to highlight the degradation information when the system performance degrades and reduce the impact when the system is in normal state.

[0138] First, the output of the CNN module is integrated with global maximum pooling and global average pooling to achieve an output size of N. The same two perceptrons are then used to learn the N features of the global pooling output to obtain the relationship and information between them. To ensure that the output size of the perceptron remains N, the number of neurons in the second layer must be the same as the output dimension of the CNN module. The outputs of the two perceptrons are then combined using element-wise summation and normalized using the Softmax function to obtain the attention weights α for different features. N Finally, the attention weight is multiplied by the output of the CNN module to obtain feature information of different importance, namely α N The larger it is, the more important the decay information contained in the corresponding feature after multiplication.

[0139] During the entire process of an aircraft engine from operation to failure, only the sensor data after the failure occurs will contain degradation information. Before that, there will be almost no degradation information in its normal operation stage. Therefore, it is necessary to focus on the operating cycles in the input sequence where the failure occurred. Since the dilation rate is used to increase the spacing between the values ​​when the convolution kernel processes the data, it expands the perception field and is conducive to the extraction of long-distance information. Therefore, two dilated convolutions are used to extract important information from the output of the CNN module. To ensure that the output size after convolution remains unchanged, the size, moving step, and padding of the convolution kernel are the same as those of the CNN module. The number of convolution kernels is the feature dimension of the input data, and the dilation rate is 3. The Softmax function is then used for normalization to obtain the self-attention weight β of the input sequence. S . S Compared with the obtained S*α N N is multiplied to obtain the running loops with different importance, that is, the output β of the SAM module S S*α N N. The larger the value, the more important the operating cycle at this moment is for the fault diagnosis of the aircraft engine.

[0140] Connect the LSTM module to the SAM module. The LSTM module has one LSTM layer, with 128 neurons per gate and the Tanh activation function. This allows the fault diagnosis network model to promptly learn the temporal information in the data features. To reduce the prediction model's sensitivity to small changes in the data, a dropout layer with a node output coefficient ratio of 0.2 is added after the LSTM layer. This layer assigns zero weights to 20% of the neurons in the network to prevent overfitting and further improve the accuracy of the intelligent fault diagnosis model.

[0141] Finally, a fully connected layer is connected after the LSTM module to perform regression analysis on the information extracted by the previous modules. Because the intelligent fault diagnosis model has multi-scale input, the analysis results of different parts are summed and averaged as the final fault diagnosis result. The calculation formula for each neuron in the fully connected layer is as follows:

[0142]

[0143] in is the output of the dth neuron in the lth layer, F is the activation function, z l-1 is the number of neurons in the l-1 layer, is the weight of the cth neuron in the l-1th layer in the lth layer, is the output of the cth neuron in the l-1th layer, is the bias of the dth neuron in the lth layer.

[0144] In step 5, the training set and validation set of the fourth fault data described in step 3 are used as input data for the intelligent fault diagnosis model described in step 4. During model training, sparse categorical cross entropy is used as the loss function, Adam is used as the optimizer, and fault diagnosis accuracy is used as the evaluation metric for the training model. Multiple model training and hyperparameter adjustments are performed to determine the network's structural depth, the number, size, and stride of convolution kernels, the number of neurons, and the activation function, to obtain a preliminarily optimized intelligent fault diagnosis model.

[0145] The loss function during model training uses sparse classification cross entropy, and its formula is as follows:

[0146]

[0147] Where m is the total number of samples, k is the number of fault categories, and p ek is the true probability of the kth type of failure occurring in the eth sample, q ek is the predicted probability of the kth type of failure occurring in the eth sample.

[0148] Table 1 Hyperparameter adjustment space of some DNN-based intelligent fault diagnosis models

[0149]

[0150] The optimizer uses Adam, and accuracy is used as the evaluation metric for the training model. After setting the above points, compile the model and perform repeated iterative training to determine the following hyperparameters:

[0151] Table 1 shows the tuning space for some hyperparameters, including the structural depth of the intelligent fault diagnosis network, the number, size, and stride of convolution kernels, the dropout coefficient, the number of neurons and activation function, the number of iterations, the number of batches fed into the model at a time, the smoothing strength of the summand weighted smoothing process, and the width of the input data.

[0152] Table 2 Random search hyperparameter adjustment results

[0153]

[0154] During training, the model can be overfitted by observing or plotting the loss values ​​for the test and validation sets at each iteration. The accuracy of each fault classification result can be combined to determine whether retraining and parameter adjustment are necessary. Through repeated adjustments, the optimal fault classification results are achieved. Using a random search algorithm, 120 searches were performed, and the three with the best parameter adjustment results were selected, as shown in Table 2. Here, MSE is the mean squared error (MSE) of the model on the validation set, α represents the smoothing strength of the exponentially weighted smoothing, S is the number of convolution kernels in the CNN module, epochs is the number of iterations, Mn is the number of neurons in the first layer of the perceptron, Do is the score ratio of the node outputs in the Dropout layer, Ln is the number of neurons in the LSTM module, Dn is the number of neurons in the fully connected layer, batch_size is the batch size, and s is the input sequence length. Table 2 shows that the MSE is minimized during the 97th decimation, indicating that the corresponding hyperparameters are the optimal model parameters among the random search epochs.

[0155] In step 6, the test set in the fourth fault data described in step 3 is used as the input of the preliminary optimized intelligent fault diagnosis model described in step 5 for testing. According to the output results, the network structure is modified and the parameters are adjusted again in step 5 until the model output results meet the expected error standard acceptance criteria. Finally, the expected optimal intelligent fault diagnosis model is obtained, and the weight parameters of the optimal intelligent fault diagnosis model are saved.

[0156] If the classification results of the test set are not ideal and cannot meet the expected error standard acceptance criteria, it means that there are still problems with the model training, which may be underfitting or overfitting. This application will use K-kold cross-validation to evaluate the accuracy of the intelligent fault diagnosis model, especially on the trained model, to test its performance on new data, which can reduce overfitting to a certain extent; in addition, it enables the model to further learn as much useful information as possible from limited data. K-kold cross-validation divides all data sets into r parts, and then takes out one of them as the validation set each time during training without repetition, and the remaining r-1 parts are used as the real training set of the model for training, and then the mean square error of the intelligent fault diagnosis model on the validation set is calculated. MSE u It represents the mean square error of the intelligent fault diagnosis model on the u-th validation set. Finally, the MSE of all r parts u Take the average to get the final mean square error O r , the calculation formula is as follows:

[0157]

[0158] Step 7: Design the optimal intelligent fault diagnosis model described in step 6 into an FPGA-based hardware IP core in the design software; the hardware IP core design includes code design for a convolution calculation IP core, a pooling calculation IP core, an activation function IP core, and a fully connected calculation IP core.

[0159] The EDA design software mainly used in this application is the Vivado HLS tool, which can use C language to design the various computing IP cores of the intelligent fault diagnosis model.

[0160] First, design the convolution calculation IP core, define the convolution kernel function, declare the weight array, input array, output array, and bias array, and write the convolution algorithm code.

[0161] Next, we design a pooling calculation IP to implement maximum pooling of size 2x2. We declare a cache array to temporarily store cache comparison results. We use three cache arrays to perform pairwise comparisons on the input data. After storing the data in two sets of cache arrays, we perform a second comparison in the second clock cycle, and store the final results in the third cache array.

[0162] Redesign the activation function IP, mainly declaring the cache array used to store the comparison results, comparing the input array elements with 0 one by one, and storing the results in the cache array.

[0163] Then design the fully connected computing IP, declare the input array, output array, weight array, and bias array used by the fully connected layer, and write the corresponding fully connected layer algorithm code.

[0164] During the code writing process, add AXI interface declaration code to automatically generate an IP core with an AXI interface during HLS synthesis, allowing the parameters of each IP core function to be transmitted using the AXI bus interface. Add HLS preprocessing instructions to the core calculation or comparison code in each IP core code, and add array splitting instructions to declared arrays to achieve pipeline and parallel calculations during HLS synthesis.

[0165] Step 8: Perform hardware acceleration optimization design based on loop unrolling on the hardware IP core described in step 7, and perform verification and synthesis to obtain an optimized circuit file; the hardware acceleration optimization design based on loop unrolling includes loop unrolling of the calculation code of the convolution layer, activation function, fully connected layer, and pooling layer, and optimizing the corresponding calculation circuit design.

[0166] For the convolution layer, the convolution operation can be regarded as a multiplication and accumulation operation containing 6 layers of nested for loops. The loop factors are cho, chi, row, col, kr, and kc (cho represents the output feature map channel, chout is the maximum number of output feature map channels; chi represents the size of the input feature map, chin is the maximum input feature map size; row represents the row of the output feature map, col represents the column of the output feature map, R is the maximum number of rows of the output feature map, and C is the maximum number of columns of the output feature map; kr and kc represent the width and height of the convolution kernel. The convolution kernel used in this application has the same width and height, and K is the height or width of the maximum convolution kernel). The three arrays involved in the operation are three-dimensional data out[chout][R][C] (output data), four-dimensional array weights[chout][chin][K][K] (weight parameter), and three-dimensional array input[chin][S*R+K][S*C+K] (input data).

[0167] The calculation code of the convolutional layer is as follows:

[0168] for(cho=0;cho <chout;cho++){

[0169] for(chi=0;chi <chin;chi++){

[0170] for(row=0;row <R;row++){

[0171] for(col=0;col <C;col++){

[0172] for(kr=0;kr <K;kr++){

[0173] for(kc=0;kc <K;kc++){

[0174] Out[cho][row][col]+=weights[cho][chi][kr][kc]*

[0175] input[chi][S*row+kr][S*col+kc];}}}}}}

[0176] This calculation code shows that in a single loop of the convolutional layer, the output data is the output data of the previous loop, plus the product of the current input data and the current weight parameter, which is a multiplication-accumulation calculation. To complete all calculations of the convolutional layer, six nested for loops are required. That is, based on the characteristics of the output feature map channel, input feature map, output feature map, and convolution kernel, a total of chout×chin×R×C×K×K cycles of multiplication-accumulation calculations are completed.

[0177] For the multi-layer nested for loop of convolution calculation, loop expansion can be selectively performed, so that the convolution layer can perform parallel computing operations when implementing the hardware, thus speeding up the calculation speed of the intelligent fault diagnosis platform based on FPGA. However, loop expansion also means that more hardware resources are required. If the loop body of the convolution operation is expanded, the number of copies required is 10. ^5 Even 10 ^6 This requires orders of magnitude more circuits. This is impossible with the logic resources of some low-end FPGA chips, and even high-end FPGAs will occupy a significant portion of the logic resources. Therefore, it is necessary to comprehensively consider the algorithm characteristics, task features, implementation difficulties, resource consumption, and computing speed.

[0178] If you cyclically expand the convolution kernel size, you can choose to expand the kernel width, height, or both. This expansion essentially performs parallel computations on each element of the kernel. However, the computational parallelism achieved by this method is limited by the kernel size. For example, for a kernel size of 3, the design space for parallel computation is limited. In other words, the parallelism achieved by cyclically expanding the kernel size is very limited and does not significantly improve computational speed.

[0179] Similarly, if the input feature map size is loop expanded, since the fault data involved in this application has the same size in width and height and the parameters are small, the design space for implementing parallel computing is also limited.

[0180] The loop expansion of the output feature map size is essentially a parallel computation of the convolutional layer's output feature map elements, meaning that multiple output feature map elements can be output at once. Although a wide range of selectable parallelism is available, this is only possible in the relatively early convolutional layers of the convolutional neural network model. Both the convolutional and pooling layers in a convolutional neural network can help reduce the size of the output feature map. Therefore, as the convolutional neural network becomes more advanced, the parallelism selection space for this method will become smaller and smaller, or even disappear. Furthermore, as the available parallelism becomes smaller and smaller, the corresponding hardware circuits must also be modified. This leads to the need to design hardware circuits with multiple degrees of parallelism to achieve the loop expansion of the output feature map sizes of different convolutional layers. This design is time-consuming, labor-intensive, and inefficient.

[0181] The loop expansion of the input feature map channels and the output feature map channels is the most suitable loop expansion for convolutional layer operations. Due to the characteristics of convolutional neural networks, the number of output feature map channels increases as the convolution layer goes deeper. Because the pooling layer only reduces the size of the output feature map and does not affect the number of channels, the number of output feature map channels is the same as the number of input feature map channels of the next convolutional layer. Therefore, the number of input feature channels and the output feature map gradually increase with each convolution layer. Therefore, the space for parallelism selection will become larger and larger, rather than decreasing until there is no parallelism like the output feature map size. For most convolutional neural networks, even in the first convolution layer, the number of output feature channels is usually 16 / 32 / 64, which is a relatively large value, so a larger degree of parallelism can be selected. Although the number of input feature map channels in the first layer may be only 1 or 3, due to the effect of the first convolutional layer, the number of input feature map channels in the second layer is equal to the number of output feature map channels in the first layer. Starting from the second layer, the number of input feature map channels is relatively large. Can it be expanded together with the number of output feature map channels? In other words, a high degree of parallelism can be achieved starting from the second layer. Therefore, only the first convolutional layer requires special design considerations. The design of the first convolutional layer can be designed by expanding only the number of output feature map channels. Starting from the second layer, the number of input feature map channels and the number of output feature map channels can be expanded.

[0182] The main operations of the convolutional layer calculation loop are: reading the corresponding elements in the input and weights arrays, multiplying them, then reading the corresponding elements in the output array, adding them to the previous product, and writing the final result back to the corresponding position in the output array. Therefore, in order to achieve the parallel multiplication and accumulation of multiple sets of data after the input feature map channel and the output feature map channel loop are expanded, it is necessary to design a multiplication and accumulation array, such as Figure 4 shown.

[0183] Figure 4 This application represents the multiplication-accumulation array designed to implement parallel calculations of input feature map channels and output feature map channels in the convolution layer. If the parallelism of the loop expansion is 8, the inputs of the multiplication-accumulation unit are 8 elements from the input data and weight parameters respectively. These data must first pass through 8 multipliers and then through 7 adders. The output data is the convolution operation result of multiple output feature map channels. These multipliers and adders are called multiplication-accumulation PE units. However, to implement parallel convolution operations of the output feature map channels, a multiplication-accumulation array composed of multiple PE units is required to complete it.

[0184] Figure 4 In the multiplication-accumulation array, the component consisting of adders and multipliers is called a processing element (PE) unit. Assuming the parallelism of the input channel loop unrolling is 8, the inputs to the multiplication-accumulation units in the PE are 8 elements from the input array and the weights array, respectively. To implement parallel multiplication-accumulation, the PE uses 7 adders to accommodate parallel operations after multiplication and addition. Each PE unit can perform convolution operations on multiple input feature map channels for one output feature map channel. To implement parallel convolution operations on output feature map channels, a multiplication-accumulation array consisting of multiple PEs is required. In the array, the storage module storing the input feature map input must simultaneously transmit elements of multiple input channels to multiple PE units. In other words, each PE receives the same input feature map data. Therefore, the input feature map storage module is still divided by input channel. For the storage module storing the weight parameters, since each PE is responsible for parallel computation of one output channel, the weight values ​​transmitted to each PE module should be the weights of the corresponding channel of that PE. The storage module storing weights[chout][chin][K][K] needs to be split in both its first and second dimensions, that is, a single-port RAM instance is separately instantiated for it, with a total of chout×chin. This allows for providing weights corresponding to multiple input channels to a single PE, and for providing weights corresponding to the output channels to each PE. Similarly, the storage module for the output feature map also needs to be split accordingly. Unlike the input feature map and weights, which only have data read operations and are implemented by instantiating multiple single-port RAMs, the storage module for the output feature map array output requires both data read and write operations, so multiple dual-port RAM instances are required to implement the split module. For the output feature map storage module of the convolutional layer, that is, the input feature map storage module of the subsequent activation function, since the activation function does not change the number of channels, the output storage module of the activation function is consistent with the storage module of the convolutional layer.

[0185] Through the above analysis, the weight storage requires the most data read operations in the execution of a loop body. Each multiplier corresponding to each PE unit needs to input a corresponding weight parameter. Therefore, the LUT resources in the FPGA chip are used to instantiate the single-port RAM for weight storage. For the input and output feature map storage, the Block RAM resources are used to instantiate the single-port and dual-port RAM respectively.

[0186] For the activation function, assuming the activation function is v(x), its calculation code is as follows:

[0187] for(cho=0;cho <chout;cho++){

[0188] for(row=0;row <R;row++){

[0189] for(col=0;col <C;col++){

[0190] Out[cho][row][col]=v{input[cho][row][col]};}}}

[0191] This calculation code shows that for the activation function v(x), the output data Out[cho][row][col] of a single loop is the value of the input data input[cho][row][col] after the activation function v(x) is calculated. To complete all the calculations of the activation function, it is necessary to complete a total of chout×R×C loop calculations based on the output feature map channels and the features of the output feature map.

[0192] Since the ReLU activation function only involves a comparison with the value of 0, the hardware only needs to implement a comparator. Unlike other activation functions, it does not need to use a lookup table to implement complex exponential calculations or even logarithmic calculations. Therefore, this application mainly uses the ReLU activation function, and according to its characteristics, the output feature channel loop expansion method can be adopted so that the operation of the activation function can be processed in parallel according to the channel. For the input feature map storage module of the activation function, that is, the output feature map storage module of the convolution layer, since the activation function does not change the number of channels, the output storage module of the activation function is consistent with the storage module of the convolution layer.

[0193] The calculation code of the fully connected layer is as follows:

[0194] for(cho=0;cho <chout;cho++){

[0195] for(chi=0;chi <chin;chi++){

[0196] Out[cho][row][col]+=weights[cho][chi]*input[chi];}}

[0197] This calculation code shows that in a single loop calculation of the fully connected layer, the current output data Out[cho][row][col] is the product of the previous output data plus the layer weight parameters weights[cho][chi] and the current input data input[chi]. To complete all calculations of the fully connected layer, a total of chout × chin loop calculations are completed based on the output feature map channels and the characteristics of the input feature map.

[0198] Compared to the computational code for the convolutional layer, the fully connected layer's computational code only contains loops for the output feature map channels and the input feature map channels. It can be observed that the dimensions of the fully connected layer's input [chi] and output [cho] are both 1. The data input to the fully connected layer is already one-dimensional, so the essence of the fully connected layer is to resize the array to a suitable size through matrix multiplication, and then output it. Referring to the discussion of loop unrolling for the convolutional layer, this application chooses to unroll the loop for the output feature channels for the fully connected layer.

[0199] After convolution calculations, a large amount of feature data is generated. If directly transmitted to the fully connected layer, it may lead to slow data learning and prone to overfitting. Therefore, a pooling layer is needed to downsample the output data of the convolution layer. While maintaining the data characteristics, it reduces the amount of data and parameters to prevent overfitting.

[0200] The calculation code of the pooling layer is as follows:

[0201] for(row=0;row <R;row++){

[0202] for(col=0;col <C;col++){

[0203] for(cho=0;cho <chout;cho++){

[0204] temp1 = ["maximum value of data before pooling kernel"];

[0205] temp2 = ["maximum value of data after pooling kernel"];

[0206] temp3=(temp1>temp2?temp1:temp2);

[0207] Out[cho][row][col]=temp3;}}}

[0208] This calculation code indicates that this application uses global max pooling. In a single loop calculation of the pooling layer, the output data Out[cho][row][col] is the maximum value of the data before and after the pooling kernel. To complete all calculations of the pooling layer, a total of R×C×chout loop calculations are required based on the characteristics of the output feature map and the output feature channel.

[0209] Since the size of the output feature map will continue to change as the pooling layer goes deeper, referring to the discussion on the loop expansion of the convolution layer, for the pooling layer, this application chooses to loop expand the size of the output feature map.

[0210] Verify and synthesize the IP core designed above. Verification includes both C code functional verification and post-synthesis verification of the IP core. C code verification involves writing the main verification function, or testbench, which calls the IP core designed in Step 7 according to the previously designed neural network model. This constructs the corresponding model, imports the pending fault data and saved model parameters, and performs verification. After functional verification of the C code, perform IP core synthesis, followed by C&RTL co-simulation. After verification, obtain the circuit files suitable for back-end design.

[0211] Step 9: Perform chip back-end design work such as testability design, layout planning, clock tree synthesis, routing, parasitic parameter extraction, and layout physical verification on the circuit file described in step 8 to realize an intelligent fault diagnosis chip for aircraft engines with high fault diagnosis accuracy and fast calculation speed.

[0212] The previous steps primarily completed the chip front-end design and simulation work, verifying the functional logic of the intelligent fault diagnosis model proposed in this application and its performance indicators when running on an FPGA, including fault diagnosis accuracy and calculation speed. However, ASICs and FPGAs differ significantly, such as the need to consider the effects of parasitic capacitance and inductance. Therefore, the chip back-end design work is required to ensure that the chip's functionality and performance indicators meet the expected design requirements after tape-out.

[0213] The chip back-end design mainly includes design for test (DFT), layout planning, clock tree synthesis (CTS), routing (Place&Route), parasitic parameter extraction and layout physical verification.

[0214] The testability design involves inserting scan chains into the circuit file described in step 8, converting non-scan units (such as registers) into scan units. The software tool used is Synopsys's DFT Compiler.

[0215] Layout planning involves placing the macro-unit modules required for the chip in the circuit file. This determines the overall placement of various functional circuits, such as IP modules, RAM, I / O pins, etc., which directly affects the final chip area. The software tool used is Synopsys' Astro.

[0216] Clock tree synthesis involves properly routing the clocks in the circuit file so that they are symmetrically connected to each register unit. This minimizes the difference in clock delay when the clocks arrive at each register from the same clock source. The software tool used is Synopsys' Physical Compiler.

[0217] Routing is to complete the routing of common signals in the circuit file, including the routing between various standard units (basic logic gate circuits). The software tool used is Astro from Synopsys.

[0218] The resistance of the wires themselves, the mutual inductance between adjacent wires, the coupling capacitance, etc., can generate signal noise, crosstalk, and reflections inside the chip, causing signal voltage fluctuations and variations. In severe cases, this can lead to signal distortion and errors. Therefore, parasitic parameters need to be extracted and re-analyzed and verified to resolve signal integrity issues. The software tool used is Synopsys' Star-RCXT.

[0219] Physical verification of the layout is the functional and timing verification of the physical layout after wiring is completed, including comparison and verification of the layout with the gate-level circuit diagram after logic synthesis, design rule checking (checking whether the connection spacing, connection width, etc. meet the chip process requirements), and electrical rule checking (checking for electrical rule violations such as short circuits and open circuits). The software tool used is Hercules from Synopsys.

[0220] After completing the chip back-end design, the GDS II file can be handed over to the chip foundry to complete the chip manufacturing, packaging and testing work, thereby realizing an aircraft engine intelligent fault diagnosis chip designed in this embodiment with high fault diagnosis accuracy and fast calculation speed.

[0221] Combine Figure 5 The structure of the aircraft engine intelligent fault diagnosis chip. This application proposes an aircraft engine fault diagnosis method based on intelligent chip technology. The specific steps are as follows:

[0222] First, the aircraft engine monitoring parameters and the weight parameters of the intelligent fault diagnosis model are pre-stored in the SD card (wherein, the monitoring parameters can also be transmitted to the intelligent fault detection chip in real time through the connecting line). The CPU reads these parameters from the SD card and stores them in the off-chip DDR memory to complete the initialization operation. According to the data transmission path of the intelligent fault diagnosis chip, the CPU reads the required weight parameters from the DDR memory, and at the same time reads the aircraft engine monitoring parameters and completes the data preprocessing work, and then transmits them to the aircraft engine intelligent fault diagnosis chip to complete the entire DNN-based fault information calculation process. The output results of the chip will be written back to the DDR storage, which serves as an important basis for maintenance personnel to determine whether the aircraft engine has a fault and what kind of fault has occurred, thereby achieving fast and accurate aircraft engine fault diagnosis.

[0223] If the intelligent fault diagnosis model needs to be updated and improved later, it can be controlled by the CPU to call each IP core again, construct a new deep neural network model, and update the relevant weight parameters of the optimal intelligent fault diagnosis model in the SD card, so as to achieve rapid update of the intelligent fault diagnosis chip function.

[0224] This application uses raw fault data generated by aircraft engine operation to train an intelligent fault diagnosis model based on a deep neural network. First, the data is extensively analyzed. Taking into account the system's operating conditions, the data is preprocessed to improve the generalization capability of the intelligent fault diagnosis model. Next, a CNN-SAM-LSTM-based intelligent fault diagnosis model for aircraft engines is established. The SAM module designed in this application focuses on the relationship between sensor parameters and the amount of decay information under different operating conditions. This not only assigns different importance weights to input data features to highlight important decay information in sensor parameters and suppress unimportant information, but also assigns importance weights to different states to emphasize decay information when system performance degrades and minimize the impact of normal system conditions. This improves the model's fault diagnosis accuracy and further enhances its generalization capability. After repeated testing, the optimal intelligent fault diagnosis model is obtained and the model weight parameters are saved for hardware implementation. The hardware implementation of the intelligent fault diagnosis model is then completed on an FPGA platform. The algorithm code for the convolutional layer, activation function, fully connected layer, and pooling layer is carefully analyzed. A hardware acceleration optimization method based on loop unrolling is proposed, which improves computational speed at a minimal resource cost. For the convolutional layer, the input feature map channel and the output feature map channel are selected for loop expansion based on the characteristics of the algorithm, and a dedicated multiplication-accumulation array is designed to realize the parallel operation of multiplication and accumulation of multiple groups of data after the loop expansion. For the ReLU activation function and the fully connected layer, the output feature map channel is selected for loop expansion based on the characteristics of their respective calculation codes. For the pooling layer, the output feature size is selected for loop expansion based on the characteristics of the algorithm. Finally, the chip backend design related work is completed to realize an intelligent aircraft engine fault diagnosis chip with high fault diagnosis accuracy and fast calculation speed. Compared with existing solutions, this application can help maintenance personnel accurately and quickly diagnose various faults in aircraft engines, reducing maintenance costs and time.

[0225] The above is a specific implementation scheme of the present application. The embodiments described in this application are merely descriptions of preferred implementation schemes and are not intended to limit the concept and scope of the embodiments of the present application. Without departing from the design concept of the present application, various modifications and improvements made by engineers and technicians in this field to the technical solutions of the present application should fall within the scope of protection of the present invention. The technical content for which protection is sought in this application has been fully recorded in the claims.

Claims

1. A method for diagnosing aircraft engine faults based on intelligent chip technology, characterized in that: The steps are as follows: Step 1: Obtain raw fault data from the aircraft engine during operation. The raw fault data is collected by sensors. Perform a first preprocessing on the raw fault data to obtain second fault data. The first preprocessing includes visual analysis, fault labeling, and data set division. The data set division includes a training set, a test set, and a validation set. Step 2: Use kernel density estimation to perform a data set distribution consistency analysis on the second fault data in step 1 to obtain third fault data. The third fault data has eliminated data with inconsistent data features, ensuring that the validation set and test set data in step 1 cover the key data features in the training set data. Step 3: performing a second preprocessing on the third fault data of step 2 to obtain fourth fault data; the second preprocessing includes normalization processing based on system operating conditions and exponential weighted smoothing processing; Step 4: Design an intelligent fault diagnosis model based on a deep neural network. The intelligent fault diagnosis model consists of two parts. The first part uses the first convolution kernel to extract local data features, and the second part uses the second convolution kernel to extract global data features. Each part includes an input layer, a CNN module, a SAM module, an LSTM module, and a fully connected layer. Step 5: Use the training set and validation set of the fourth fault data in step 3 as input data for the intelligent fault diagnosis model in step 4. During model training, sparse classification cross entropy is used as the loss function, Adam is used as the optimizer, and accuracy is used as the evaluation indicator of the training model. Perform multiple model training and hyperparameter adjustments to determine the network's structural depth, the number, size, and step size of the convolution kernels, the number of neurons, and the activation function, and obtain a preliminarily optimized intelligent fault diagnosis model. Step 6: Use the test set of the fourth fault data in step 3 as the input of the intelligent fault diagnosis model preliminarily optimized in step 5 for testing. Return to step 5 again to adjust the model hyperparameters according to the output results until the model output results meet the expected error standard acceptance criteria. Finally, the optimal intelligent fault diagnosis model is obtained, and the weight parameters of the optimal intelligent fault diagnosis model are saved. Step 7: Design the optimal intelligent fault diagnosis model in step 6 into an FPGA-based hardware IP core in the design software; Hardware IP core design includes code design for convolution computing IP core, pooling computing IP core, activation function IP core, and fully connected computing IP core; Step 8: Perform hardware acceleration optimization design based on loop unrolling on the hardware IP core of step 7, and perform verification and synthesis to obtain the optimized circuit file; The hardware acceleration optimization design based on loop unrolling includes loop unrolling of the computational code for convolutional layers, activation functions, fully connected layers, and pooling layers, and optimizing the corresponding computational circuit design. Step 9: Perform chip back-end design work such as testability design, layout planning, clock tree synthesis, routing, parasitic parameter extraction and layout physical verification on the circuit file of step 8.

2. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1, characterized in that: The specific steps in step 1 are as follows: 1.1 Raw fault data, i.e., various types of fault data collected by multiple different types of sensors, including aircraft engine temperature, pressure, speed, bleed air flow, and lubricating oil detection parameters. These parameters serve as input data for the intelligent fault diagnosis model based on a deep neural network. 1.2 Data Visualization: Using Python, we visualize the sensor data for each fault. We analyze the data trends, remove parameters that do not affect system performance, and retain parameters that contain fault information as input for model training. 1.3 Set fault labels for the data in step 1.2 according to the fault type: Various types of fault labels are set in the form of digital codes: [0, 1, 2, . . . , 5], where 0 represents the fault label when the aircraft engine is operating normally, 1 represents the fault label when the aircraft engine temperature parameter is abnormal, 2 represents the fault label when the aircraft engine pressure state parameter is abnormal, 3 represents the fault label when the aircraft engine speed state parameter is abnormal, 4 represents the fault label when the aircraft engine bleed air flow parameter is abnormal, and 5 represents the fault label when the aircraft engine lubricating oil detection parameter is abnormal; 1.4 Divide the dataset that has undergone visual analysis and labeled fault labels into 10 equal parts, ensuring that the amount of data in each part is the same. Randomly select 6 parts as training sets, and then randomly select 2 parts from the remaining 4 parts as validation sets. Finally, the remaining 2 parts are test sets.

3. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1 is characterized in that: The kernel density estimation in step 2 is to estimate the probability density function of the given data. After the kernel density distribution analysis is performed, the data distribution consistency of the validation set, test set and training set is ensured to ensure the consistency of the data features in each data set. Suppose there are n data: x1, x2, x3, ..., x n , the probability density function of the data is f(x); The kernel density function formula is: where x i represents the i-th data, n is the amount of data, f(x i ) is the probability density function of the ith data, and h is the bandwidth in the kernel density estimation.

4. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1, characterized in that: The specific steps for the second preprocessing of data in step 3 are as follows: 3.1 Classify the fault data under the same operating conditions and then perform normalization. The formula is: where x i Represents a data sample (x1, x2, x3, ..., x n ) in the i-th data, X i ∈[0,1] and dimensionless, for x i After normalization, the data x j Represents a data sample (x1, x2, x3, ..., x n ) in the jth data, max 1≤j≤n {x j } for x1, x2, x3, …, x n The maximum value, min 1≤j≤n {x j } for x1, x2, x3, …, x n The minimum value in ; 3.2 Since the original fault data contains a lot of noise, it is necessary to perform exponential weighted smoothing on the data to filter out the noise interference in the data. The formula is as follows: G(t)=α*g(t)+(1-α)*G(t-1) Where G(t) is the value of g(t) at the current moment after smoothing, g(t) is the data value collected by a certain sensor at the current moment, G(t-1) is the result of smoothing at the previous moment, and α is the intensity of smoothing, which ranges from 0 to 1.

5. The aircraft engine fault diagnosis method based on smart chip technology according to claim 1 is characterized in that: The design structure of the intelligent fault diagnosis model based on deep neural network in step 4 is as follows: 4.1 The input layer of the model takes all sensor data of the system t cycles as the input of the model; 4.2 After the input layer, a convolutional neural network (CNN) module is connected. The CNN module consists of two one-dimensional convolutional layers and a maximum pooling layer. A Dropout layer is added between each convolutional layer to prevent overfitting, and the output coefficient is 0.

3. The configuration parameters of the two convolutional layers are the same. To ensure that the output feature size remains unchanged after the convolution operation, the height of the convolution kernel is 3, the number is 128, the moving step is 1, and all zero padding is used. The activation function uses ReLU to achieve nonlinear mapping of different features. The size of the pooling layer in each combination is 2, which halves the size of the output feature. The output size of the final module is S*N, where N is the feature dimension, which is equal to the number of convolution kernels in the last convolutional layer. S is the length of the output sequence. When the convolution kernel moving step is 1, its calculation formula is as follows: S=W-H+1 Where W is the sequence length of the input data, and H is the height of the convolution kernel; 4.3 Input the output data of the CNN module into the self-attention mechanism SAM module; First, the output of the CNN module is integrated with global maximum pooling and global average pooling, and the output size after global pooling is N; Then, the same two-layer perceptrons are used to learn the N features of the global pooling output to obtain the relationship and information between them. To ensure that the output size of the perceptron remains N, the number of neurons in the second layer must be the same as the output dimension of the CNN module; Then, the outputs of the two perceptrons are merged using element-wise summation, and the sum is normalized by the Softmax function to obtain the attention weight α of different features. N ; Secondly, because the dilation rate is used in the dilation convolution to increase the spacing between values ​​when the convolution kernel processes data, the receptive field is expanded, which is conducive to the extraction of long-distance information. Therefore, two dilation convolutions are used to extract important information from the output of the CNN module. To ensure that the output size after convolution remains unchanged, the size, moving step, and padding of the convolution kernel are the same as those of the CNN module. The number of convolution kernels is the feature dimension of the input data, and the dilation rate is 3. Then, the Softmax function is used for normalization to obtain the self-attention weight β of the input sequence. S ; Then compare it with the obtained S*α N N is multiplied to obtain running loops of different importance; 4.4 Connect the Long Short-Term Memory (LSTM) network module to the SAM module. The LSTM module has an LSTM layer with 128 neurons per gate and uses the Tanh activation function, enabling the fault diagnosis network model to promptly learn the temporal information in the data features. To reduce the prediction model's sensitivity to small changes in the data, a Dropout layer with a node output coefficient of 0.2 is added after the LSTM layer. 20% of the neurons in the LSTM layer are assigned zero weights to prevent overfitting and improve the accuracy of the intelligent fault diagnosis model. 4.5 Finally, a fully connected layer is connected after the LSTM module to perform regression analysis on the information extracted by the previous modules. Since the model has multi-scale input, the analysis results of different parts are summed and averaged as the final fault diagnosis result. The calculation formula for each neuron in the fully connected layer is as follows: in is the output of the dth neuron in the lth layer, F is the activation function, z l-1 is the number of neurons in the l-1 layer, is the weight of the cth neuron in the l-1th layer in the lth layer, is the output of the cth neuron in the l-1th layer, is the bias of the dth neuron in the lth layer.

6. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1, characterized in that: The specific steps for training the model, adjusting the hyperparameters, and obtaining the diagnostic model in step 5 are as follows: 5.1 The training set and validation set are used as inputs to the intelligent fault diagnosis model. The validation set is input to the model after the training set is completed to verify the generalization ability of the model. 5.2 The loss function during model training uses sparse classification cross entropy, and its formula is as follows: Where m is the total number of samples, k is the number of fault categories, and p ek is the true probability of the kth type of failure occurring in the eth sample, q ek is the predicted probability of the kth type of failure occurring in the eth sample; 5.3 The optimizer used for model training is Adam, and accuracy is used as the network evaluation indicator; 5.4 Compile the model and perform iterative training to determine the following hyperparameters: The structural depth of the intelligent fault diagnosis model based on deep neural networks, the number, size and step size of convolution kernels, the dropout coefficient, the number of neurons and activation function, the number of iterations, the number of batches fed into the model each time, the smoothing strength of the summand weighted smoothing process, and the width of the input data; During the training process, the loss values ​​of the test set and validation set are output for each iteration to determine whether the model is overfitting. The accuracy of each fault classification result is analyzed to determine whether it is necessary to return to step 5.4 to adjust the hyperparameters. After repeated debugging, the fault classification results are optimized.

7. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1, characterized in that: The specific steps in step 6 are as follows: Input the test set data into the preliminarily optimized intelligent fault diagnosis model to further verify the generalization ability of the model. If the classification results of the test set are not ideal and cannot meet the expected error standard acceptance criteria, it means that there are still problems with the model training, or it is underfitting or overfitting. It is necessary to return to steps 5.4 to 5.5 and retrain and debug. After the output results of the test set meet the requirements, the final optimal model is obtained and the weights of the model are saved.

8. The aircraft engine fault diagnosis method based on smart chip technology according to claim 1, characterized in that: The specific steps for hardware IP core design in step 7 are as follows: 7.1 Use the Vivado HLS tool to create project projects corresponding to the convolution computing IP, pooling computing IP, activation function IP, and fully connected computing IP, and use the C language to implement the functions of each IP; 7.2 Select the FPGA chip model, first design the convolution calculation IP core, define the convolution kernel function, declare the weight array, input array, output array, and bias array, and write the convolution algorithm code; 7.3 Design the pooling calculation IP to implement 2x2 max pooling. Declare that the cache array is used to cache the comparison results. Use three cache arrays to perform pairwise comparisons on the input data. After storing the data in two sets of cache arrays, perform a second comparison in the second clock cycle and store the final results in the third cache array. 7.4 Design the activation function IP, which declares a cache array for storing comparison results. Compare the input array elements with 0 one by one and store the results in the cache array. 7.5 Design the fully connected computing IP, declare the input array, output array, weight array, and bias array used by the fully connected layer, and write the corresponding fully connected layer algorithm code; 7.

6. Add AXI interface declaration code during code writing so that the IP core with AXI interface is automatically generated during HLS synthesis, so that the parameters of each IP core function can be transmitted using the AXI bus interface; 7.7 Add HLS preprocessing instructions to the core calculation or comparison code in each IP core code, and add array splitting instructions to the declared arrays to achieve pipeline and parallel operations of calculations during HLS synthesis.

9. The aircraft engine fault diagnosis method based on intelligent chip technology according to claim 1, characterized in that: The specific steps in step 8 are as follows: 8.1 Analyze the convolution layer loop code; the convolution operation is regarded as a multiplication and accumulation operation with 6 layers of nested for loops. The loop factors are cho, chi, row, col, kr, and kc. cho represents the output feature map channel, row and col represent the output feature map size, chi represents the input feature map size, and kr and kc represent the convolution kernel size. The three arrays involved in the operation are the three-dimensional data out[chout][R][C], the four-dimensional array weights[chout][chin][K][K], and the three-dimensional array input[chin][S*R+K][S*C+K]. 8.2 After theoretical analysis, the input feature map channel and the output feature map channel are selected as the loop expansion parameters of the convolution layer; 8.3 For the parallel calculation of the input feature map channels and output feature map channels of the convolutional layer, a multiplication-accumulation array circuit is designed to realize the parallel multiplication-accumulation operation of multiple groups of data after loop expansion; for the multiplication-accumulation processing element unit (PE), each PE unit completes the convolution operation of multiple groups of input feature map channels for one output feature map channel. If the parallel convolution operation of the output feature map channel is to be realized, a multiplication-accumulation array composed of multiple PEs is required to complete it; in the array, the storage module storing the input feature map input must simultaneously transmit the elements of multiple input channels to multiple PE units. In other words, the input feature map data received by each PE is the same, so the storage module of the input feature map is still split according to the input channel; 8.4 Analyze activation function code; Use the ReLU activation function to loop-unroll the output feature map channels; 8.5 Analyze the calculation code of the fully connected layer; since the input and output dimensions of the fully connected layer are both 1, the data input to the fully connected layer is already one-dimensional data. Therefore, the essence of the fully connected layer is to change the array size to an array that meets the requirements through matrix multiplication and finally output it. Therefore, for the fully connected layer, choose to loop expand the output feature channel; 8.6 Analyze the calculation code of the pooling layer; since the output feature map size of the pooling layer will continue to change as the pooling layer goes deeper, we choose to expand the output feature size loop; 8.7 Verification includes C code functional verification and IP core post-synthesis verification. C code verification involves writing the main verification function, namely the testbench function, which calls the IP core designed in step 7 according to the previously designed neural network model to form the corresponding model, import the fault data to be processed and the saved model parameters for verification; 8.8 After functional verification of the C code, the IP core is synthesized, followed by C&RTL joint simulation. After verification, the circuit file for chip back-end design is obtained.

10. The aircraft engine fault diagnosis method based on smart chip technology according to claim 1, characterized in that: The specific steps in step 9 are as follows: 9.1 Design for Testability (DFT) involves inserting scan chains into the circuit file in step 8, converting non-scan cells into scan cells. The software tool used is Synopsys' DFT Compiler. 9.2 Layout planning involves placing the macrocell modules required for the chip in the circuit file. This determines the overall placement of various functional circuits and directly affects the final chip area. The software tool used is Synopsys' Astro. 9.3 Clock Tree Synthesis (CTS) involves properly routing the clocks in the circuit file, ensuring that they are symmetrically connected to each register unit and that the clock delay differences are minimized when the clocks arrive at each register from the same clock source. The software tool used is Synopsys' Physical Compiler. 9.4 Place & Route is to complete the routing of common signals in the circuit file, including the routing between various standard cells. The software tool used is Synopsys' Astro. 9.5 Parasitic Parameter Extraction: The inherent resistance of the wires, the mutual inductance between adjacent wires, and the coupling capacitance can generate signal noise, crosstalk, and reflections within the chip, leading to signal voltage fluctuations and variations. Therefore, parasitic parameter extraction is necessary for further analysis and verification to resolve signal integrity issues. The software tool used is Synopsys' Star-RCXT. 9.6 Layout Physical Verification is the functional and timing verification of the completed physical layout. This includes comparison and verification between the layout and the gate-level circuit diagram after logic synthesis, design rule checking, and electrical rule checking. The software tool used is Synopsys' Hercules. 9.7 After completing the chip back-end design, the GDS II file will be handed over to the chip foundry to complete the chip manufacturing, packaging and testing.

Images