Silicon carbide ohmic contact and method of making same

Abstract

The application discloses a silicon carbide ohmic contact and a preparation method thereof, and belongs to the technical field of semiconductors. The silicon carbide ohmic contact and the preparation method thereof solve the problems of poor repeatability, weak oxidation resistance and poor surface quality of the metal or alloy layer of the silicon carbide ohmic contact in the prior art. The method comprises the following steps: forming a silicon carbide doped layer on a silicon carbide substrate; sequentially depositing a nickel layer, an aluminum layer and a titanium layer on the surface of the silicon carbide doped layer by means of magnetron sputtering or evaporation to obtain a to-be-processed silicon carbide ohmic contact; and sequentially performing two-step annealing treatment on the to-be-processed silicon carbide ohmic contact to obtain the silicon carbide ohmic contact. The silicon carbide ohmic contact and the preparation method thereof can be used for a silicon carbide device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide ohmic contact and its preparation method. Background Technology

[0002] In the information transmission process between semiconductor devices and external circuits, SiC ohmic contacts serve as signal conversion bridges, directly determining the power dissipation and switching speed of the devices.

[0003] Due to the high chemical and physical stability of silicon carbide, a high-temperature annealing process is typically required during the formation of ohmic contacts. However, high-temperature annealing can cause reactions between the contact material and the oxide layer, affecting the performance and reliability of the MOSFET.

[0004] Currently, the metal or alloy layer of silicon carbide ohmic contacts suffers from problems such as poor repeatability, weak oxidation resistance, low hardness, and poor surface quality. This makes them easily oxidized in air and susceptible to mechanical damage, reducing the reliability of the ohmic contact electrode and severely limiting its application environment and scope. Consequently, the application range and reliability of silicon carbide devices are significantly affected and restricted. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a silicon carbide ohmic contact and its preparation method, which solves the problems of poor repeatability, weak oxidation resistance and poor surface quality of the metal or alloy layer of silicon carbide ohmic contacts in the prior art.

[0006] The objective of this invention is mainly achieved through the following technical solutions:

[0007] This invention provides a method for preparing a silicon carbide ohmic contact, comprising the following steps:

[0008] Step 1: Provide a silicon carbide substrate;

[0009] Step 2: Form a silicon carbide doped layer on a silicon carbide substrate to obtain a silicon carbide epitaxial wafer;

[0010] Step 3: Deposit nickel, aluminum and titanium layers sequentially on the surface of the silicon carbide doped layer by magnetron sputtering or evaporation. The nickel, aluminum and titanium layers are used as raw materials for preparing the metal contact layer to obtain the silicon carbide ohmic contact to be treated.

[0011] Step 4: Perform two step-by-step annealing processes on the silicon carbide ohmic contacts to be processed to obtain silicon carbide ohmic contacts.

[0012] Furthermore, in step 2 above, the deposition rate of the nickel layer is 8–12 nm / min (e.g., 8 nm / min, 9 nm / min, 11 nm / min, 12 nm / min, etc.), the deposition rate of the aluminum layer is 8–12 nm / min (e.g., 8 nm / min, 9 nm / min, 11 nm / min, 12 nm / min, etc.), the deposition rate of the titanium layer is 2.5–3.0 nm / min (e.g., 2.5 nm / min, 2.7 nm / min, 2.85 nm / min, 3.0 nm / min, etc.), and the vacuum level in the magnetron sputtering cavity is 5E-6 Torr.

[0013] Furthermore, the nickel layer has a thickness of 20–40 nm (e.g., 20 nm, 26 nm, 31 nm, 35 nm, 38 nm, 40 nm, etc.), the aluminum layer has a thickness of 90–110 nm (e.g., 90 nm, 96 nm, 98 nm, 105 nm, 110 nm, etc.), and the titanium layer has a thickness of 100–110 nm (e.g., 100 nm, 102 nm, 105 nm, 108 nm, 110 nm, etc.).

[0014] Furthermore, the thickness of the silicon carbide doped layer is 0.8–1.2 μm (e.g., 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, etc.).

[0015] Furthermore, in step 4 above, the stepped two-stage annealing process includes the following steps:

[0016] Under a nitrogen or argon atmosphere, the silicon carbide ohmic contact to be treated is heated from room temperature to 400–500°C (e.g., 400°C, 415°C, 440°C, 466°C, 482°C, 500°C, etc.) at a heating rate of 20–30°C / s, and held at that temperature for 7–11 seconds (e.g., 7 seconds, 9 seconds, 10 seconds, 11 seconds, etc.) for the first annealing treatment.

[0017] The silicon carbide ohmic contacts to be treated after the first annealing are heated to 950-1000℃ (950℃, 960℃, 971℃, 983℃, 990℃, 100℃, etc.) at a heating rate of 60-100℃ / s (e.g., 60℃ / s, 72℃ / s, 85℃ / s, 90℃ / s, 96℃ / s, 100℃, etc.), held at that temperature for 2-3 min (2 min, 2.5 min, 3 min, etc.), and then subjected to a second annealing treatment.

[0018] Furthermore, the heating rate of the first annealing treatment is less than that of the second annealing treatment.

[0019] Furthermore, the holding time for the first annealing treatment is shorter than the holding time for the second annealing treatment.

[0020] Furthermore, the silicon carbide substrate material includes 4H-SiC, 3C-SiC, and 6H-SiC. N-type silicon carbide substrates are formed by doping with group V impurities such as phosphorus, arsenic, or antimony, or P-type silicon carbide substrates are formed by doping with group III elements such as boron, aluminum, and indium, with a doping concentration of 1E14cm⁻¹. -3 Up to 1E18cm -3 .

[0021] Furthermore, the following steps are included between steps 2 and 3 above:

[0022] The silicon carbide epitaxial wafer is cleaned.

[0023] Furthermore, the above cleaning includes the following steps:

[0024] First, the silicon carbide epitaxial wafer is immersed in a mixture of 98 wt% concentrated sulfuric acid and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen. Next, the silicon carbide epitaxial wafer is immersed in a mixture of 28 wt% ammonia and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen. Finally, the silicon carbide epitaxial wafer is immersed in a mixture of 10 wt% hydrochloric acid and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen.

[0025] Furthermore, an inversion layer is formed between the silicon carbide substrate and the silicon carbide doped layer, and the doping types of the silicon carbide doped layer and the inversion layer are opposite.

[0026] Furthermore, a buffer layer is formed between the silicon carbide substrate and the inversion layer.

[0027] Furthermore, the thickness of the buffer layer is 1.8–2.1 μm (e.g., 1.8 μm, 2.0 μm, 2.1 μm, etc.), and the doping concentration is 5E15cm. -3 Up to 5E18cm -3 .

[0028] Furthermore, the following steps are included between steps 2 and 3 above:

[0029] Steps are formed on the surface of the silicon carbide epitaxial wafer.

[0030] Furthermore, the above-mentioned step formation on the surface of the silicon carbide epitaxial wafer includes the following steps:

[0031] Step a: Deposit a mask layer (e.g., a SiO2 layer with a thickness of 1.0 to 2.0 μm) on the surface of a silicon carbide epitaxial wafer using methods such as physical vapor deposition (PVD), enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc.);

[0032] Step b: At 120–140°C, an adhesion layer (e.g., fumed hexamethyldisilamide HMDS) is coated on the surface of the mask layer to enhance the adhesion between the photoresist layer and the mask layer. Then, after 4–6 hours, a photoresist layer (e.g., positive photoresist, which becomes soluble after light irradiation and is removed, with a thickness of 3–6.5 μm) is spin-coated on the surface of the adhesion layer. The mask layer is used as a hard mask for step etching.

[0033] Step c: The photoresist layer is dried, photolithographically lithographic (e.g., contact lithography, stepper lithography, or electron beam lithography), rinsed, and dried with nitrogen to form a stepped cross-sectional pattern. The drying temperature is 100–120°C, and the drying time is 2–3 min. Specifically, the photolithography includes processes such as spin coating, pre-baking, exposure, development, and hardening. The exposure time for photolithography is 110–130 s, and the development time is 80–100 s.

[0034] Step d: Dry etching (e.g., inductively coupled plasma (ICP) or reactive ion (RIE)) is performed on the mask layer to etch down to the silicon carbide epitaxial wafer, so that the mask layer forms a hard mask with a stepped cross-sectional pattern. The etching gas is a mixture of CF4 and Ar, the etching temperature is room temperature, the etching time is 5-7 min, the source power of the inductively coupled plasma is 580-610 W, and the radio frequency power is 95-110 W.

[0035] Step e: Remove the photoresist and perform dry etching (e.g., inductively coupled plasma ICP) on the silicon carbide epitaxial wafer to etch through the silicon carbide doped layer, so that a step with a stepped cross-sectional pattern is formed on the surface of the silicon carbide epitaxial wafer. The etching gas is a mixture of SF6 and Ar, and the source power of the inductively coupled plasma is 580-610W, and the radio frequency power is 95-110W.

[0036] Step f: The hard mask is removed by wet etching to form a step on the surface of the silicon carbide epitaxial wafer. The depth of the step is greater than 1 μm. The etching solution is HF solution with a ratio of HF:H2O = 1:10. The etching temperature is room temperature and the etching time is 28 to 33 min.

[0037] The present invention also provides a silicon carbide ohmic contact prepared by the above-described method for preparing silicon carbide ohmic contacts.

[0038] Specifically, the silicon carbide ohmic contact comprises a silicon carbide substrate, a buffer layer, an inversion layer, a silicon carbide doped layer, and a metal contact layer stacked sequentially.

[0039] Furthermore, the specific contact resistance of the silicon carbide ohmic contact is 10 ohms. -3 ~10 -4 Ω·cm 2 .

[0040] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0041] a) The method for preparing silicon carbide ohmic contacts provided by this invention involves sequentially forming a nickel layer, an aluminum layer, and a titanium layer on a silicon carbide substrate. The titanium layer is positioned as the outermost layer, which inhibits the flow of molten aluminum, constrains the flow of molten aluminum, and improves the oxidation resistance of the alloy system. This effectively reduces the resistance of the ohmic contact and ensures a smooth and uniform surface. Thus, both n-type and p-type silicon carbide ohmic contacts can be formed simultaneously using the same ternary metal system (nickel, aluminum, and titanium) and the same process, resulting in a stable and smooth contact surface. The ohmic contact exhibits good stability, which is beneficial for improving bonding reliability and maintaining current consistency. Furthermore, for silicon carbide devices (e.g., MOSFETs, IGBTs, or BJTs), this method effectively reduces process steps, simplifies the fabrication process, and reduces costs, which is beneficial for device miniaturization and system integration.

[0042] b) The method for preparing silicon carbide ohmic contacts provided by this invention is not a simple adjustment of the deposition sequence. Since adjusting the aluminum layer between the nickel and titanium layers will reduce the adhesion between the aluminum and nickel layers, in order to compensate for this problem, this invention uses a stepped two-stage annealing process in the subsequent annealing process. The annealing temperature of the first annealing is lower than that of the second annealing, which is equivalent to a pre-annealing process. During the pre-annealing process, the aluminum layer can be appropriately softened to form a stable nickel-aluminum alloy in advance, preventing the aluminum metal from evaporating at high temperatures. This can improve the adhesion between the aluminum and nickel layers, thereby achieving the adjustment of the deposition sequence while ensuring the adhesion between each layer. In addition, during the pre-annealing process, the nickel metal can react with the silicon carbide in the silicon carbide doped layer to generate Ni2Si. The Ni2Si in the intermediate layer of the interface is a key factor in the formation of n-type ohmic contacts.

[0043] c) In the method for preparing silicon carbide ohmic contacts provided by the present invention, it is preferable that the heating rate of the first annealing treatment is lower than that of the second annealing treatment. This is because the first annealing treatment is mainly used to soften the aluminum layer. A lower heating rate can ensure that the aluminum layer is fully softened, further improving the adhesion between the nickel layer, aluminum layer and titanium layer. The second annealing treatment is mainly used to realize the reaction between the nickel layer, aluminum layer, titanium layer and silicon carbide doped layer. A rapid second annealing treatment can obtain the minimum process thermal budget by shortening the heat treatment time, which is beneficial to accelerate the reaction rate and improve the reaction efficiency.

[0044] d) In the method for preparing silicon carbide ohmic contacts provided by the present invention, it is preferable that the holding time of the first annealing treatment is shorter than that of the second annealing treatment. This is because the first annealing treatment is mainly used for softening the aluminum layer, and the holding time only needs to be sufficient to soften the aluminum layer, without being too long. The second annealing treatment is mainly used to realize the reaction between the nickel layer, aluminum layer, titanium layer and silicon carbide doped layer. Sufficient holding time can ensure that the reaction proceeds fully and improve the conversion rate.

[0045] e) In the method for preparing silicon carbide ohmic contacts provided by the present invention, organic contaminants, oxide films, and metal particles on the silicon carbide epitaxial wafer can be removed sequentially through a cleaning process. Specifically, firstly, organic contaminants on the surface of the silicon carbide epitaxial wafer are removed to prevent organic contaminants from covering part of the surface of the silicon carbide epitaxial wafer, thereby making it easier to remove contaminants such as oxide films and metal particles; then, the oxide layer is a "contamination trap" that can introduce epitaxial defects, and the oxide film can be dissolved through the cleaning process; finally, particulate metal contaminants are removed, and the surface of the silicon carbide epitaxial wafer is passivated.

[0046] f) In the method for preparing silicon carbide ohmic contacts provided by the present invention, an inversion layer may also be formed between the silicon carbide substrate and the silicon carbide doped layer. The doping types of the silicon carbide doped layer and the inversion layer are opposite, thereby enabling the formation of an inverted pn junction. In order to release stress and reduce epitaxial defects generated during the formation of the inversion layer, a buffer layer may also be formed between the silicon carbide substrate and the inversion layer.

[0047] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0048] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0049] Figure 1Surface test images of silicon carbide ohmic contacts prepared using existing methods;

[0050] Figure 2 A schematic diagram of the structure of the silicon carbide ohmic contact to be treated, prepared by the method of preparing silicon carbide ohmic contact provided by the present invention.

[0051] Figure 3 The process diagram of the two-stage heat treatment in the method for preparing silicon carbide ohmic contacts provided by the present invention;

[0052] Figure 4 The flowchart illustrates the process of forming steps on the surface of a silicon carbide epitaxial wafer in the method for preparing a silicon carbide ohmic contact provided by the present invention.

[0053] Figure 5 This is a schematic diagram of the silicon carbide ohmic contact provided by the present invention;

[0054] Figure 6 The surface test pattern of the silicon carbide ohmic contact prepared by the method of the present invention.

[0055] The attached figures are labeled as follows:

[0056] 1-Silicon carbide substrate; 2-Buffer layer; 3-Inversion layer; 4-Silicon carbide doped layer; 5-Nickel layer; 6-Aluminum layer; 7-Titanium layer; 8-Mask layer; 9-Photoresist layer; 10-Metal contact layer. Detailed Implementation

[0057] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of the present invention and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.

[0058] Existing silicon carbide ohmic contacts typically involve forming a nickel (Ni) layer, a titanium (Ti) layer, and an aluminum (Al) layer on a silicon carbide substrate as the metal contact layer. Considering the good adhesion between titanium and nickel, the titanium layer is usually placed between the nickel and aluminum layers, meaning the aluminum layer is the outermost layer. However, in this structure, during subsequent high-temperature annealing, the aluminum layer melts and flows, resulting in a very rough surface of the metal contact layer. (See [link to documentation]). Figure 1 This affects the reliability of ohmic contacts.

[0059] This invention provides a method for preparing a silicon carbide ohmic contact, see [link to relevant documentation]. Figures 2 to 4 It includes the following steps:

[0060] Step 1: Provide a silicon carbide substrate 1 (SiC substrate);

[0061] Step 2: Form a silicon carbide doped layer 4 on the silicon carbide substrate 1 to obtain a silicon carbide epitaxial wafer, wherein the doping concentration is 1E14cm⁻¹. -3 Up to 1E18cm -3 ;

[0062] Step 3: A nickel layer 5 (Ni layer), an aluminum layer 6 (Al layer), and a titanium layer 7 (Ti layer) are sequentially deposited on the surface of the silicon carbide doped layer 4 by magnetron sputtering or evaporation. The nickel layer 5, aluminum layer 6, and titanium layer 7 serve as raw materials for preparing the metal contact layer 10, thus obtaining the silicon carbide ohmic contact to be treated. The deposition rate of the nickel layer 5 is 8–12 nm / min (e.g., 8 nm / min, 9 nm / min, 11 nm / min, 12 nm / min, etc.), the deposition rate of the aluminum layer 6 is 8–12 nm / min (e.g., 8 nm / min, 9 nm / min, 11 nm / min, 12 nm / min, etc.), and the deposition rate of the titanium layer 7 is 2.5–3.0 nm / min (e.g., 2.5 nm / min, 2.7 nm / min, 2.85 nm / min, 3.0 nm / min, etc.). The vacuum level in the magnetron sputtering chamber is 5E-6 Torr.

[0063] Step 4: Perform two step-by-step annealing processes on the silicon carbide ohmic contacts to be processed to obtain silicon carbide ohmic contacts.

[0064] Compared with the prior art, the method for preparing silicon carbide ohmic contacts provided by the present invention involves sequentially forming a nickel layer 5, an aluminum layer 6, and a titanium layer 7 on a silicon carbide substrate 1. The titanium layer 7 is positioned as the outermost layer, which can inhibit the flow of molten aluminum layer 6, constrain the flow of molten aluminum, improve the oxidation resistance of the alloy system, and effectively reduce the resistance of the ohmic contact (lower than the contact resistance, controlled within 10 Ω). -3 ~10 -4 Ω·cm 2 The surface is smooth and uniform, allowing the use of the same ternary metal system (nickel, aluminum, and titanium) and the same process to simultaneously form n-type and p-type silicon carbide ohmic contacts, resulting in a stable and smooth contact surface. The ohmic contacts have good stability, which is beneficial for improving bonding reliability and maintaining current consistency. At the same time, for silicon carbide devices (e.g., MOSFETs, IGBTs, or BJTs), it can effectively reduce the number of process steps, simplify the fabrication process, reduce costs, and facilitate device miniaturization and system integration.

[0065] It is important to emphasize that this invention is not a simple adjustment of the deposition sequence. Since adjusting the aluminum layer 6 to be between the nickel layer 5 and the titanium layer 7 would reduce the adhesion between the aluminum layer 6 and the nickel layer 5, in order to compensate for this problem, this invention uses a stepped two-stage annealing process in the subsequent annealing process. The annealing temperature of the first annealing is lower than that of the second annealing, which is equivalent to a pre-annealing process. During the pre-annealing process, the aluminum layer 6 can be appropriately softened to form a stable nickel-aluminum alloy in advance, preventing the aluminum metal from evaporating at high temperatures. This improves the adhesion between the aluminum layer 6 and the nickel layer 5, thus achieving the adjustment of the deposition sequence while ensuring the adhesion between each layer. In addition, during the pre-annealing process, the nickel metal can react with the silicon carbide in the silicon carbide doped layer 4 to generate Ni2Si. The Ni2Si in the intermediate layer of the interface is a key factor in the formation of n-type ohmic contacts.

[0066] It is worth noting that the amount of nickel, aluminum, and titanium added determines the composition of the resulting metal contact layer 10. The composition of the metal contact layer 10 directly affects the final performance of the silicon carbide ohmic contact. The amount of nickel, aluminum, and titanium added can be controlled by controlling the thickness of the nickel layer 5, the aluminum layer 6, and the titanium layer 7. For example, the thickness of the nickel layer 5 is 20–40 nm (e.g., 20 nm, 26 nm, 31 nm, 35 nm, 38 nm, 40 nm, etc.), the thickness of the aluminum layer 6 is 90–110 nm (e.g., 90 nm, 96 nm, 98 nm, 105 nm, 110 nm, etc.), and the thickness of the titanium layer 7 is 100–110 nm (e.g., 100 nm, 102 nm, 105 nm, 108 nm, 110 nm, etc.).

[0067] Similarly, the thickness of the silicon carbide doped layer 4 also affects the composition of the metal contact layer 10. For example, the thickness of the silicon carbide doped layer 4 is 0.8 to 1.2 μm (e.g., 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, etc.).

[0068] Specifically, the stepped two-stage annealing process includes the following steps:

[0069] Under a nitrogen or argon atmosphere, the silicon carbide ohmic contact to be treated is heated from room temperature to 400–500°C (e.g., 400°C, 415°C, 440°C, 466°C, 482°C, 500°C, etc.) at a heating rate of 20–30°C / s, and held at that temperature for 7–11 seconds (e.g., 7 seconds, 9 seconds, 10 seconds, 11 seconds, etc.) for the first annealing treatment.

[0070] The silicon carbide ohmic contacts to be treated after the first annealing are heated to 950-1000℃ (950℃, 960℃, 971℃, 983℃, 990℃, 100℃, etc.) at a heating rate of 60-100℃ / s (e.g., 60℃ / s, 72℃ / s, 85℃ / s, 90℃ / s, 96℃ / s, 100℃, etc.), held at that temperature for 2-3 min (2 min, 2.5 min, 3 min, etc.), and then subjected to a second annealing treatment.

[0071] The heating rate of the first annealing treatment is lower than that of the second annealing treatment. This is because the first annealing treatment is mainly used to soften the aluminum layer 6. The lower heating rate can ensure that the aluminum layer 6 is fully softened, further improving the adhesion between the nickel layer 5, the aluminum layer 6, and the titanium layer 7. The second annealing treatment is mainly used to realize the reaction between the nickel layer 5, the aluminum layer 6, the titanium layer 7 and the silicon carbide doped layer 4. The rapid second annealing treatment can obtain the minimum process thermal budget by shortening the heat treatment time, which is conducive to accelerating the reaction rate and improving the reaction efficiency.

[0072] Similarly, the holding time for the first annealing treatment is shorter than that for the second annealing treatment. This is because the first annealing treatment is mainly used to soften the aluminum layer 6, and the holding time only needs to be sufficient to soften the aluminum layer 6, without being too long. The second annealing treatment is mainly used to realize the reaction between the nickel layer 5, aluminum layer 6, titanium layer 7 and silicon carbide doped layer 4. Sufficient holding time can ensure that the reaction proceeds fully and improve the conversion rate.

[0073] It should be noted that the material of the silicon carbide substrate 1 includes, but is not limited to, 4H-SiC, 3C-SiC or 6H-SiC. It can also be formed by doping with group V impurities such as phosphorus, arsenic or antimony to form an N-type silicon carbide substrate 1, or by doping with group III elements such as boron, aluminum, indium to form a P-type silicon carbide substrate 1.

[0074] To reduce the impact of impurities during the formation of silicon carbide doped layer 4 on subsequent processes, the following steps are included between steps 2 and 3:

[0075] The silicon carbide epitaxial wafer is cleaned.

[0076] In this way, the cleaning process can sequentially remove organic contaminants, oxide films, and metal particles from the silicon carbide epitaxial wafer. Specifically, firstly, organic contaminants on the surface of the silicon carbide epitaxial wafer are removed to prevent them from partially obscuring the surface, thus making it easier to remove oxide films and metal particles. Secondly, the oxide layer acts as a "contamination trap," introducing epitaxial defects; the cleaning process can dissolve the oxide film. Finally, particulate metal contaminants are removed, and the surface of the silicon carbide epitaxial wafer is passivated.

[0077] Specifically, the above cleaning includes the following steps:

[0078] First, the silicon carbide epitaxial wafer is immersed in a mixture of 98 wt% concentrated sulfuric acid and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen. Next, the silicon carbide epitaxial wafer is immersed in a mixture of 28 wt% ammonia and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen. Finally, the silicon carbide epitaxial wafer is immersed in a mixture of 10 wt% hydrochloric acid and 27 wt% hydrogen peroxide (volume ratio 1:1-2), heated in a water bath at 90-95°C for 15-18 minutes, rinsed with deionized water, and dried with nitrogen.

[0079] To prevent longitudinal current flow and form a reverse pn junction for isolation, an inversion layer 3 is also formed between the silicon carbide substrate 1 and the silicon carbide doped layer 4. The doping types of the silicon carbide doped layer 4 and the inversion layer 3 are opposite, thereby enabling the formation of a reverse pn junction.

[0080] To relieve stress and reduce epitaxial defects generated during the formation of the inversion layer 3, a buffer layer 2 is also formed between the silicon carbide substrate 1 and the inversion layer 3. For the thickness and doping concentration of the buffer layer 2, exemplarily, the thickness of the buffer layer 2 is 1.8–2.1 μm (e.g., 1.8 μm, 2.0 μm, 2.1 μm, etc.), and the doping concentration is 5E15cm⁻¹. -3 Up to 5E18cm -3 .

[0081] To facilitate subsequent contact resistance testing and isolate the influence of lateral current, the following steps are included between steps 2 and 3 above:

[0082] Steps are formed on the surface of the silicon carbide epitaxial wafer.

[0083] Specifically, the above-mentioned steps for forming steps on the surface of silicon carbide epitaxial wafers include the following steps:

[0084] Step a: Deposit a mask layer 8 (e.g., a SiO2 layer with a thickness of 1.0 to 2.0 μm) on the surface of a silicon carbide epitaxial wafer using methods such as physical vapor deposition (PVD), enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc.);

[0085] Step b: At 120–140°C, an adhesion layer (e.g., fumed hexamethyldisilamide HMDS) is coated on the surface of the mask layer 8 to enhance the adhesion between the photoresist layer 9 and the mask layer 8. Then, after 4–6 hours, the photoresist layer 9 (e.g., positive photoresist, which becomes soluble after light irradiation and is removed, with a thickness of 3–6.5 μm) is spin-coated on the surface of the adhesion layer. The mask layer 8 is used as a hard mask for step etching.

[0086] Step c: The photoresist layer 9 is dried, photolithographically etched (e.g., contact lithography, stepper lithography, or electron beam lithography), rinsed, and dried with nitrogen to form a stepped cross-sectional pattern. The drying temperature is 100–120°C, and the drying time is 2–3 min. Specifically, the photolithography includes processes such as spin coating, pre-baking, exposure, development, and hardening. The exposure time for photolithography is 110–130 s, and the development time is 80–100 s.

[0087] Step d: Dry etching (e.g., inductively coupled plasma (ICP) or reactive ion (RIE)) is performed on the mask layer 8 to etch down to the silicon carbide epitaxial wafer, so that the mask layer 8 forms a hard mask with a stepped cross-sectional pattern. The etching gas is a mixture of CF4 and Ar, the etching temperature is room temperature, the etching time is 5 to 7 minutes, the source power of the inductively coupled plasma is 580 to 610 W, and the radio frequency power is 95 to 110 W.

[0088] Step e: Remove the photoresist and perform dry etching (e.g., inductively coupled plasma ICP) on the silicon carbide epitaxial wafer to etch through the silicon carbide doped layer 4, so that a step with a stepped cross-sectional pattern is formed on the surface of the silicon carbide epitaxial wafer. The etching gas is a mixture of SF6 and Ar, and the source power of the inductively coupled plasma is 580-610W, and the radio frequency power is 95-110W.

[0089] Step f: The hard mask is removed by wet etching to form a step on the surface of the silicon carbide epitaxial wafer. The depth of the step is greater than 1 μm. The etching solution is HF solution with a ratio of HF:H2O = 1:10. The etching temperature is room temperature and the etching time is 28 to 33 min.

[0090] The present invention also provides a silicon carbide ohmic contact, see [link to relevant documentation]. Figure 5 It was prepared using the above-described method for preparing silicon carbide ohmic contacts.

[0091] Compared with the prior art, the beneficial effects of the silicon carbide ohmic contact provided by the present invention are basically the same as the beneficial effects of the above-mentioned silicon carbide ohmic contact preparation method, and will not be elaborated here.

[0092] Specifically, the silicon carbide ohmic contact comprises a silicon carbide substrate 1, a buffer layer 2, an inversion layer 3, a silicon carbide doped layer 4, and a metal contact layer 10 stacked sequentially, with a specific contact resistance of 10 Ω·cm. -3 ~10 -4 Ω·cm 2 .

[0093] Example 1

[0094] This embodiment provides a silicon carbide ohmic contact and its preparation method, including the following steps:

[0095] Step A: A buffer layer, an inversion layer, and a silicon carbide doped layer are sequentially formed on a 4H-SiC substrate to obtain a silicon carbide epitaxial wafer. The buffer layer has a thickness of 1.8 μm and a doping concentration of 5E15cm⁻¹. -3 The silicon carbide doped layer has a thickness of 1.0 μm and a doping concentration of 1E14 cm⁻¹. -3 ;

[0096] Step B: Deposit a SiO2 layer with a thickness of 1.0 μm on the surface of the silicon carbide epitaxial wafer using physical vapor deposition;

[0097] Step C: At 120°C, a vapor phase hexamethyldisilimide layer is coated on the surface of the SiO2 layer. After 6 hours, a positive photoresist layer with a thickness of 6.5 μm is spin-coated on the surface of the vapor phase hexamethyldisilimide layer.

[0098] Step D: The photoresist layer is dried at 100°C for 3 minutes, and then photolithography is performed. The photolithography exposure time is 130 seconds and the development time is 100 seconds.

[0099] Step E: The SiO2 layer is etched by inductively coupled plasma dry etching down to the silicon carbide epitaxial wafer, so that the mask layer forms a hard mask with a stepped cross-sectional pattern. The etching gas is a mixture of CF4 and Ar, the etching temperature is room temperature, the etching time is 5 min, the source power of the inductively coupled plasma is 600 W, and the radio frequency power is 100 W.

[0100] Step F: Remove the photoresist and perform inductively coupled plasma dry etching on the silicon carbide epitaxial wafer to etch through the silicon carbide doped layer, so that a step with a stepped cross-sectional pattern is formed on the surface of the silicon carbide epitaxial wafer. The etching gas is a mixture of SF6 and Ar, the source power of the inductively coupled plasma is 600W, and the radio frequency power is 100W.

[0101] Step G: The hard mask is removed by wet etching to form a step on the surface of the silicon carbide epitaxial wafer. The depth of the step is 1.1 μm. The etching solution is HF solution with a ratio of HF:H2O = 1:10. The etching temperature is room temperature and the etching time is 30 min.

[0102] Step H: Immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; then, immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 28wt% ammonia and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; finally, immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2.

[0103] Step I: A nickel layer, an aluminum layer, and a titanium layer are sequentially deposited on the surface of the silicon carbide doped layer by magnetron sputtering. The nickel, aluminum, and titanium layers are used as raw materials for preparing the metal contact layer to obtain the silicon carbide ohmic contact to be treated. The thickness of the nickel layer is 26 nm, the thickness of the aluminum layer is 90 nm, and the thickness of the titanium layer is 105 nm. The deposition rate of the nickel layer is 8 nm / min, the deposition rate of the aluminum layer is 11 nm / min, and the deposition rate of the titanium layer is 2.7 nm / min. The vacuum degree in the magnetron sputtering chamber is 5E-6 Torr.

[0104] Step J: Under a nitrogen or argon atmosphere, the silicon carbide ohmic contact to be treated is heated from room temperature to 415°C at a heating rate of 20°C / s, held at that temperature for 10s, and subjected to the first annealing treatment.

[0105] Step K: The silicon carbide ohmic contact to be treated after the first annealing is heated to 1000℃ at a heating rate of 60℃ / s, held for 2.5 min, and then subjected to a second annealing treatment to obtain the silicon carbide ohmic contact.

[0106] The silicon carbide ohmic contact prepared in Example 1 was subjected to specific contact resistance and surface morphology tests, and the specific contact resistance was measured to be 10. -3 Ω·cm 2 .

[0107] pass Figure 1 and Figure 6 In comparison, it is clear that the silicon carbide ohmic contact in Example 1 effectively reduces the surface roughness of the ohmic contact, resulting in a uniform and stable surface.

[0108] Example 2

[0109] This embodiment provides a silicon carbide ohmic contact and its preparation method, including the following steps:

[0110] Step A: A buffer layer, an inversion layer, and a silicon carbide doped layer are sequentially formed on a 6H-SiC substrate to obtain a silicon carbide epitaxial wafer. The buffer layer has a thickness of 2.0 μm and a doping concentration of 5E18 cm⁻¹. -3 The silicon carbide doped layer has a thickness of 1.2 μm and a doping concentration of 1E18 cm⁻¹. -3 ;

[0111] Step B: A SiO2 layer with a thickness of 1.8 μm is deposited on the surface of the silicon carbide epitaxial wafer using enhanced chemical vapor deposition;

[0112] Step C: At 135°C, a vapor phase hexamethyldisilimide layer is coated on the surface of the SiO2 layer. After 4 hours, a positive photoresist layer with a thickness of 3.5 μm is spin-coated on the surface of the vapor phase hexamethyldisilimide layer.

[0113] Step D: The photoresist layer is dried at 120°C for 2 minutes, and then photolithography is performed. The photolithography exposure time is 120 seconds and the development time is 90 seconds.

[0114] Step E: The SiO2 layer is etched by inductively coupled plasma dry etching down to the silicon carbide epitaxial wafer, so that the mask layer forms a hard mask with a stepped cross-sectional pattern. The etching gas is a mixture of CF4 and Ar, the etching temperature is room temperature, the etching time is 6 min, the source power of the inductively coupled plasma is 580 W, and the radio frequency power is 108 W.

[0115] Step F: Remove the photoresist and perform inductively coupled plasma dry etching on the silicon carbide epitaxial wafer to etch through the silicon carbide doped layer, so that a step with a stepped cross-sectional pattern is formed on the surface of the silicon carbide epitaxial wafer. The etching gas is a mixture of SF6 and Ar, the source power of the inductively coupled plasma is 580W, and the radio frequency power is 108W.

[0116] Step G: The hard mask is removed by wet etching to form a step on the surface of the silicon carbide epitaxial wafer. The depth of the step is 1.0 μm. The etching solution is HF solution with a ratio of HF:H2O = 1:10. The etching temperature is room temperature and the etching time is 28 min.

[0117] Step H: Immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; then, immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 28wt% ammonia and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; finally, immerse the silicon carbide epitaxial wafer in a 1:1 mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2.

[0118] Step I: A nickel layer, an aluminum layer, and a titanium layer are sequentially deposited on the surface of the silicon carbide doped layer by magnetron sputtering. The nickel, aluminum, and titanium layers are used as raw materials for preparing the metal contact layer to obtain the silicon carbide ohmic contact to be treated. The thickness of the nickel layer is 38 nm, the thickness of the aluminum layer is 105 nm, and the thickness of the titanium layer is 110 nm. The deposition rate of the nickel layer is 10 nm / min, the deposition rate of the aluminum layer is 8 nm / min, and the deposition rate of the titanium layer is 3.0 nm / min. The vacuum degree in the magnetron sputtering chamber is 5E-6 Torr.

[0119] Step J: Under a nitrogen or argon atmosphere, the silicon carbide ohmic contact to be treated is heated from room temperature to 500°C at a heating rate of 28°C / s, held at that temperature for 7s, and then subjected to the first annealing treatment.

[0120] Step K: The silicon carbide ohmic contact to be treated after the first annealing is heated to 960°C at a heating rate of 96°C / s, held for 3.0 min, and then subjected to a second annealing treatment to obtain the silicon carbide ohmic contact.

[0121] The silicon carbide ohmic contact prepared in Example 2 was subjected to a specific contact resistance test, and the specific contact resistance was measured to be 10. -4 Ω·cm 2 .

[0122] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a silicon carbide ohmic contact, characterized in that, Includes the following steps: Step 1: Provide a silicon carbide substrate; Step 2: Form a silicon carbide doped layer on a silicon carbide substrate to obtain a silicon carbide epitaxial wafer; Step 3: Sequentially deposit a nickel layer, an aluminum layer, and a titanium layer on the surface of the silicon carbide doped layer. The nickel layer, aluminum layer, and titanium layer are used as raw materials for preparing the metal contact layer to obtain the silicon carbide ohmic contact to be treated. Step 4: Perform two step-by-step annealing processes on the silicon carbide ohmic contacts to be processed to obtain silicon carbide ohmic contacts; An inversion layer is also formed between the silicon carbide substrate and the silicon carbide doped layer, and the doping types of the silicon carbide doped layer and the inversion layer are opposite. The steps between steps 2 and 3 include the following: Step a: Depositing a mask layer on the surface of the silicon carbide epitaxial wafer; Step b: Coating an adhesion layer on the surface of the mask layer to enhance the adhesion between the photoresist layer and the mask layer, and then spin-coating a photoresist layer on the surface of the adhesion layer. The mask layer serves as a hard mask for step etching; Step c: Drying, photolithographic rinsing, and nitrogen blowing of the photoresist layer to form a step cross-sectional pattern; Step d: Dry etching of the mask layer down to the silicon carbide epitaxial wafer, so that the mask layer forms a hard mask with a step cross-sectional pattern; Step e: Removing the photoresist and dry etching the silicon carbide epitaxial wafer to penetrate the silicon carbide doped layer, so that a step with a step cross-sectional pattern is formed on the surface of the silicon carbide epitaxial wafer; Step f: Removing the hard mask using wet etching to form a step on the surface of the silicon carbide epitaxial wafer.

2. The method for preparing a silicon carbide ohmic contact according to claim 1, characterized in that, The nickel layer has a thickness of 20-40 nm, the aluminum layer has a thickness of 90-110 nm, and the titanium layer has a thickness of 100-110 nm.

3. The method for preparing a silicon carbide ohmic contact according to claim 1 or 2, characterized in that, The thickness of the silicon carbide doped layer is 0.8~1.2 µm.

4. The method for preparing a silicon carbide ohmic contact according to claim 1 or 2, characterized in that, In step 4, the stepped two-stage annealing process includes the following steps: The silicon carbide ohmic contacts to be treated are subjected to a first annealing treatment and a second annealing treatment in sequence; The heating rate of the first annealing treatment is less than the heating rate of the second annealing treatment; The holding time for the first annealing treatment is shorter than the holding time for the second annealing treatment.

5. The method for preparing a silicon carbide ohmic contact according to claim 4, characterized in that, In step 4, the stepped two-stage annealing process includes the following steps: Under a nitrogen or argon atmosphere, the silicon carbide ohmic contact to be treated is heated from room temperature to 400-500 ℃ at a heating rate of 20-30 ℃ / s and held for 7-11 s for the first annealing treatment. After the first annealing, the silicon carbide ohmic contact to be treated is heated to 950-1000 ℃ at a heating rate of 60-100 ℃ / s, held for 2-3 min, and then subjected to a second annealing treatment.

6. The method for preparing a silicon carbide ohmic contact according to claim 1, characterized in that, The following steps are also included between step 2 and step 3: The silicon carbide epitaxial wafer is cleaned.

7. The method for preparing a silicon carbide ohmic contact according to claim 1, characterized in that, A buffer layer is also formed between the silicon carbide substrate and the inversion layer.

8. A silicon carbide ohmic contact, characterized in that, The silicon carbide ohmic contact is prepared by the method for preparing silicon carbide ohmic contacts as described in any one of claims 1 to 7.

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