A novel nano-wall NWaFET fabrication and verification method

Abstract

The patent of the present invention relates to the field of integrated circuit technology, and in particular refers to a method for making and verifying a new type of nano-wall NWaFET. The manufacturing method includes the following steps: S1 epitaxial growth: first, an epitaxial layer with a certain thickness is grown in sequence on a P-type substrate by epitaxial growth technology; S2 etching: etching away the excess part of the epitaxial layer; S3 thermal oxidation: growing SiO2 by thermal oxidation process; S4 ion implantation: doping is performed on the intrinsic silicon implantation layer by ion implantation process; S5 re-etching: further etching of annular grooves and rectangular grooves; S6 metal deposition; the verification method includes the following steps: S7 layout design and tape-out: designing devices with corresponding width-to-length ratios, and performing sampling tests; S8 packaging: PCB packaging of the designed chip with radiation-resistant structural devices; S9 irradiation: subjecting the device to irradiation testing. This method can effectively suppress the threshold voltage V th Drift and shutdown current I off The increase in the number of cells can improve the ability to resist TID effects.

Description

Technical Field

[0001] The invention patent relates to the field of integrated circuit technology, and in particular to a method for manufacturing and verifying a new type of nano-wall NWaFET. Background Art

[0002] Strictly speaking, the total dose effect, also known as the "Total Ionizing Dose" (TID), occurs when a large number of radiation particles enter the interior of semiconductor device materials, ionizing the material's extranuclear electrons and generating additional charge. This charge then accumulates in the device's oxide layer or induces interface states at the Si / SiO2 interface, leading to gradual degradation and eventual loss of device performance. The TID effect can cause a variety of adverse phenomena in transistor devices, including threshold voltage drift, increased leakage current, and decreased mobility, degrading chip performance and rendering it inoperable.

[0003] For example, while the gate-all-around structure prevents direct contact between the channel and STI, thereby suppressing the formation of STI parasitic channels, in practical applications, its design flexibility is limited by the need for the gate to wrap around the entire circuit. For example, at its smallest size, the minimum aspect ratio achievable by a gate-all-around is only 8:1. Furthermore, the gate-all-around structure consumes a significant amount of chip area, making it unsuitable for large-scale integration. Summary of the Invention

[0004] (1) Problems to be solved

[0005] It is mainly used to solve the influence of TID effect, and then solve many adverse phenomena such as threshold voltage drift, leakage current increase, mobility decrease and so on of transistor devices caused by TID effect, prevent chip performance degradation, and provide a new nano-wall NWaFET production and verification method.

[0006] (2) Technical solution

[0007] According to a first aspect of the present invention, a method for fabricating a novel nanowall NWaFET is provided, the method comprising the following steps:

[0008] S1 epitaxial growth: First, epitaxial layers of a certain thickness are grown on a P-type substrate using epitaxial growth technology. The epitaxial layers are N+ epitaxial layer and N- epitaxial layer, P+ epitaxial layer, and intrinsic silicon layer from bottom to top.

[0009] S2 etching: Etch away the excess part of the epitaxial layer, and the remaining part is used as the N-drain region, channel P+ region, and intrinsic silicon injection layer;

[0010] S3 thermal oxidation: The etched part is subjected to a thermal oxidation process to grow a SiO2 layer;

[0011] S4 ion implantation: On the intrinsic silicon implantation layer, an N-source region is formed by ion implantation, and then an N+ source region and a channel P+ region are doped in the N-source region by ion implantation.

[0012] S5 further etching: further etching to obtain annular grooves and rectangular grooves;

[0013] S6 metal deposition: metal is deposited in the annular groove and the rectangular groove.

[0014] As a preferred technical solution, the N-drain region, the channel P+ region, the N-source region and the N+ source region together constitute an active region.

[0015] As a preferred technical solution, in step S5, both the annular groove and the rectangular groove need to be etched to above the N+ epitaxial layer. The annular groove is etched with the active area as the center. A certain thickness of SiO2 isolation layer is left at the bottom of the annular groove, and a certain thickness of SiO2 gate oxide layer is left on the side of the annular groove. The SiO2 in the rectangular groove should be completely etched.

[0016] According to a second aspect of the present invention, a verification method for a novel nanowall NWaFET is provided, the verification method comprising the following steps:

[0017] S7 layout design and tape-out: Design devices with corresponding aspect ratios, set up comparison reference groups, and conduct sampling tests;

[0018] S8 packaging: PCB packaging of the designed chip with radiation-resistant structural devices;

[0019] S9 irradiation: subject the device to irradiation test.

[0020] As a preferred technical solution, in step S7, devices with five width-to-length ratios, namely 2:0.2, 2:0.6, 10:3, 30:3 and 30:9, are sampled and tested on the chips at the same time.

[0021] As a preferred technical solution, the instruments used for sampling testing are a probe station and a semiconductor parameter tester 4155B.

[0022] As a preferred technical solution, in step S8, the rectangle where the sample chip is packaged is 4 mm long and 3 mm wide. The entire board is 31 mm long and 30 mm wide, with a total of 24 pins. The PIN hole spacing is 2.54 mm, the hole spacing between P1 and P2 is 15 mm, and the words "DIP24" are on the right. All samples are welded with 2.54 mm pin headers, and a locking seat is used in the experiment to fix the irradiated chip.

[0023] As a preferred technical solution, step S9 is mainly divided into two parts. In the first part, some samples are irradiated, and the irradiation is stopped at the 200krad (Si) dose point and a displacement test is performed; in the second part, some samples are irradiated, and displacement tests are performed at the 300krad (Si), 600krad (Si), 900krad (Si), 1200krad (Si), 1500krad (Si), and 1800krad (Si) dose points respectively.

[0024] As a preferred technical solution, the test equipment is the institute's Keithley 4200-SCS / F semiconductor parameter test system. The sample to be tested is placed in a test box equipped with the 4200, and the ambient temperature during the test is room temperature.

[0025] (3) Beneficial effects

[0026] The beneficial effects of the present invention are:

[0027] (1) NWaFET is a new type of nano-wall longitudinal structure, which consists of N+ source region, N- source region, P+ channel region, N- drain region, N+ drain region and substrate from top to bottom, surrounded by metal gate. This structure can separate the channel from STI. After irradiation, it is only affected by the fixed holes in the gate oxide layer, thus effectively improving the ability to resist TID effect.

[0028] (2) Since the channel of the NWaFET device is heavily doped, it can effectively suppress the attraction of fixed holes inside the gate oxide layer and at the interface to electrons, thereby suppressing the threshold voltage V th Drift and shutdown current I off The increase in , inhibited the TID effect.

[0029] (3) During the layout design and tape-out for radiation verification, smaller devices are selected to verify the radiation resistance of the structure designed at a small size, and other sizes are designed for comparison. In the layout, the pins of each device are connected separately to avoid mutual influence between devices when applying stimulation.

[0030] (4) A locking seat was used in the experiment to fix the irradiated chip. This can save a lot of time in fixing and removing the chip and avoid errors in the test results due to annealing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 It is a structural schematic diagram of the present invention;

[0033] Figure 2 It is a flow chart of the production method of the present invention;

[0034] Figure 3 It is a flow chart of the verification method of the present invention;

[0035] Figure 4 is a transfer characteristic curve diagram of the present invention;

[0036] Figure 5 is an output characteristic curve diagram of the present invention;

[0037] Figure 6 2 is the transfer characteristic curve of the present invention under different TIDs;

[0038] Figure 7 is the threshold voltage variation ΔV of the present invention under different TIDs th ;

[0039] Figure 8 The turn-off current I of the present invention under different TID off ;

[0040] Figure 9 is the transfer characteristic curve of the present invention at different TIDs in a specified channel doping concentration;

[0041] Figure 10 The threshold voltage variation ΔV of the present invention under different channel doping concentrations and different TIDs is th ;

[0042] Figure 11 The turn-off current I of the present invention is off .

[0043] 1-P-type substrate; 2-epitaxial layer; 3-N+ epitaxial layer; 4-N-epitaxial layer; 5-P+ epitaxial layer; 6-intrinsic silicon layer; 7-N-drain region; 8-channel P+ region; 9-intrinsic silicon injection layer; 10-N-source region; 11-N+ source region; 12-annular groove; 13-rectangular groove; 14-active region; 15-SiO2 isolation layer; 16-SiO2 gate oxide layer; 17-SiO2 layer. DETAILED DESCRIPTION

[0044] The preparation and verification method of a novel nano-wall NWaFET of the present invention will be further described with reference to the accompanying drawings.

[0045] As shown in the accompanying drawings, a method for manufacturing a novel nano-wall NWaFET is provided, comprising the following steps:

[0046] S1 epitaxial growth: First, an epitaxial layer 2 of a certain thickness is grown on a P-type substrate 1 by epitaxial growth technology. The epitaxial layer 2 is composed of an N+ epitaxial layer 3 and an N- epitaxial layer 4, a P+ epitaxial layer 5, and an intrinsic silicon layer 6 from bottom to top.

[0047] S2 etching: etching away the excess portion of the epitaxial layer 2, and the remaining portion serves as the N-drain region 7, the channel P+ region 8, and the intrinsic silicon implantation layer 9;

[0048] S3 thermal oxidation: The etched part is subjected to a thermal oxidation process to grow a SiO2 layer 17;

[0049] S4 ion implantation: On the intrinsic silicon implantation layer 9, an N-source region 10 is formed by an ion implantation process, and an N+ source region 11 and a channel P+ region 8 are doped in the N-source region 10 by ion implantation;

[0050] S5: further etching to obtain the annular groove 12 and the rectangular groove 13;

[0051] S6 metal deposition: metal is deposited in the annular groove 12 and the rectangular groove 13 .

[0052] Furthermore, the N− drain region 7 , the channel P+ region 8 , the N− source region 10 and the N+ source region 11 together constitute an active region 14 .

[0053] Furthermore, in step S5, both the annular groove 12 and the rectangular groove 13 need to be etched to above the N+ epitaxial layer 3. The annular groove 12 is etched with the active area 14 as the center. A SiO2 isolation layer 15 of a certain thickness is left at the bottom of the annular groove 12, and a SiO2 gate oxide layer 16 of a certain thickness is left on the side of the annular groove 12. The SiO2 in the rectangular groove 13 should be completely etched.

[0054] As shown in the attached figure, a verification method for a novel nano-wall NWaFET is provided, which includes the following steps:

[0055] S7 layout design and tape-out: Design devices with corresponding aspect ratios, set up comparison reference groups, and conduct sampling tests;

[0056] S8 packaging: PCB packaging of the designed chip with radiation-resistant structural devices;

[0057] S9 irradiation: subject the device to irradiation test.

[0058] Furthermore, in step S7, the chips were sampled and tested at the same time for devices with five aspect ratios: 2:0.2, 2:0.6, 10:3, 30:3, and 30:9 μm.

[0059] Furthermore, the instruments used for the sampling test were a probe station and a semiconductor parameter tester 4155B.

[0060] Furthermore, in step S8, the rectangle where the sample chip is packaged is 4mm long and 3mm wide. The entire board is 31mm long and 30mm wide, with a total of 24 pins. The PIN hole spacing is 2.54mm, the hole spacing between P1 and P2 is 15mm, and the words "DIP24" are on the right. All samples are welded with 2.54mm pin headers, and a locking seat is used in the experiment to fix the chip to be irradiated.

[0061] Furthermore, step S9 is mainly divided into two parts. In the first part, some samples are irradiated, and the irradiation is stopped at the 200krad (Si) dose point and a shift test is performed; in the second part, some samples are irradiated, and a shift test is performed at the 300krad (Si), 600krad (Si), 900krad (Si), 1200krad (Si), 1500krad (Si), and 1800krad (Si) dose points respectively.

[0062] Furthermore, the test equipment is the institute's Keithley 4200-SCS / F semiconductor parameter test system. The sample to be tested is placed in a test box equipped with the 4200, and the ambient temperature during the test is room temperature.

[0063] The present invention aims to enhance the device's resistance to TID effects. The basic principles are as follows:

[0064] (1) The thinner the gate oxide layer, the stronger the device's resistance to TID effect.

[0065] (2) The higher the doping concentration, the stronger the device's anti-TID effect.

[0066] The novel nano-wall field effect transistor (NWaFET) device structure designed by the present invention is a vertical device with a heavily doped channel. From top to bottom, it consists of an N+ source region, an N- source region, a P+ channel region, an N- drain region, an N+ drain region, and a substrate. It is surrounded by a metal gate, and the drain is led out by grooves and metal deposition. Because the channel of the NWaFET device is heavily doped, it can effectively suppress the attraction of fixed holes in the gate oxide layer and at the interface to electrons, thereby suppressing the threshold voltage V th Drift and shutdown current Ioff In addition, since the gate surrounds the channel, the contact between the channel and the STI is eliminated. After irradiation, it is only affected by the fixed holes in the gate oxide layer, which can effectively improve the ability to resist the TID effect.

[0067] To verify the effectiveness of the novel nanowall NWaFET device in resisting the TID effect, the present invention designed layouts based on conventional PES-NMOS transistors and novel nanowall NWaFET transistors, respectively, and used a 0.18 μm process for tapeout. After successful tapeout, two irradiation experiments were conducted.

[0068] (1) After the initial test, 30 conventional PES-NMOS devices of each aspect ratio and 3 new nano-wall NWaFET devices of each aspect ratio were selected and placed on the irradiation plate. The "P1" marking on the sample was aligned with the position of the locking rod. The samples were then placed vertically in a 60Co-γ ray irradiation chamber for the first part of the irradiation experiment. The radiation dose rate during the experiment was 99.41 rad(Si) / s, the distance from the source center was 25 cm, the temperature was 20°C, and the humidity was 40% RH.

[0069] During the irradiation process, the device is biased to the ON state, that is, the gate voltage V g is 1.8V, the source voltage V s and drain voltage V d All are 0V, the VDD terminal of the irradiated board is connected to 1.8V voltage, and the GND terminal is grounded. When the radiation dose accumulates to 196.83krad(Si), the irradiation is stopped and the power is turned off, for a total of 33 minutes. After the irradiation is stopped, the transfer characteristics of all irradiated devices are tested. The test condition is drain voltage V d When the gate voltage V is 0.1V and 1.8V respectively, g Sweep from -0.3V to 1.8V with a step size of 0.02V.

[0070] (2) Similarly, 30 conventional PES-NMOS devices (three devices of each aspect ratio) and 3 new nano-wall NWaFET devices (three devices of each aspect ratio) were placed on the irradiation plate and vertically placed in the 60Co-γ ray irradiation chamber for the second part of the irradiation experiment. The radiation dose rate in the experiment was 254.063 rad(Si) / s, the distance from the center of the source was 25 cm, the temperature was 21°C, and the humidity was 40% RH.

[0071] Similarly, during the irradiation process, the device is biased to the ON state, that is, the gate voltage V g is 1.8V, the source voltage V s and drain voltage V dAll are 0V, the VDD terminal of the irradiated board is connected to 1.8V voltage, and the GND terminal is grounded. When the radiation dose accumulates to 300krad(Si), 600krad(Si), 900krad(Si), 1200krad(Si), 1500krad(Si) and 1800krad(Si), the irradiation is stopped, and the transfer characteristic shift test is performed on all irradiated devices. The test condition is drain voltage V d When the gate voltage V is 0.1V and 1.8V respectively, g The voltage was scanned from -0.3 V to 1.8 V with a step size of 0.1 V. After the test was completed, the device was placed back into the irradiation chamber and irradiated until the experiment was completed.

[0072] To better demonstrate the superiority of the present invention, see the following experimental data for details:

[0073] a. Static characteristics simulation

[0074] To verify the feasibility of the established NWaFET device, its transfer characteristic curve and output characteristic curve were first simulated. When simulating the transfer characteristic curve, the drain voltage was 1.8V and the gate voltage was swept from 0V to 1.8V; when simulating the output characteristic curve, the gate voltage was first swept to several fixed voltages, and then the drain voltage was swept from 0V to 1.8V. The simulation results are shown in the attached figure. Figure 4-5 .

[0075] Using the fixed current method, the threshold voltage V can be obtained from the transfer characteristic curve of NWaFET. th is 0.737V, the shutdown current I off is 8.556×10 -15 A.

[0076] b. TID effect simulation

[0077] After calculation and adding fixed holes inside the oxide and at the interface, the transfer characteristic curves of the NWaFET device under different TIDs were obtained by simulation, as shown in the attached figure. Figure 6 shown.

[0078] As can be seen from the figure above, the leakage current of the NWaFET device under different TID conditions does not increase significantly compared to the non-irradiated state, indicating that the NWaFET has excellent resistance to TID effects. Specific parameters of the simulation results are shown in the table below.

[0079] NWaFET static characteristics under different TIDs

[0080]

[0081] It can be seen that when TID is equal to 100krad(Si), the threshold voltage V this 0.713V, the shutdown current I off is 7.435×10 -15 A, compared with the unirradiated state, the threshold voltage drifted negatively by 0.024V, and the off-state current decreased by about 13.1%. When TID is equal to 200krad(Si), the threshold voltage V th is 0.689V, the shutdown current I off is 6.924×10 -15 A, compared with the unirradiated state, the threshold voltage drifted negatively by 0.048V, and the off-state current decreased by about 19.1%. When TID is equal to 300krad(Si), the threshold voltage V th is 0.666V, the shutdown current I off is 7.851×10 -15 A, compared with the unirradiated state, the threshold voltage drifted negatively by 0.071V, and the off-state current decreased by about 8.2%. When TID is equal to 400krad(Si), the threshold voltage V th is 0.640V, the shutdown current I off 1.140×10 -14 A, compared with the non-irradiated state, the threshold voltage drifted negatively by 0.097V, and the off-state current was 1.33 times that of the non-irradiated state. When TID is equal to 500krad(Si), the threshold voltage V th is 0.619V, the shutdown current I off is 1.879×10 -14 A, compared with the non-irradiated state, the threshold voltage drifted in the negative direction by 0.118V, and the turn-off current was 2.20 times that of the non-irradiated state.

[0082] Attachment Figure 7-8 is the threshold voltage change of NWaFET ΔV th The relationship curve between TID and NWaFET’s off-state current I off The relationship curve between ΔTID and NWaFET is shown in Figure 2. The results show that NWaFET has a good ability to strengthen the TID effect.

[0083] c. Influence of channel doping concentration on TID effect

[0084] In order to study the effect of the channel doping concentration on the TID effect of NWaFET, the other parameters were kept unchanged and only the doping concentration of the channel region was changed to 1×10 19 cm -3 , and adjust the threshold voltage. The TID effect under this doping concentration is simulated, as shown in the attached figure. Figure 9 shown.

[0085] As can be seen from the figure above, increasing the channel doping concentration can reduce the off-state current I of NWaFET off , improve the ability of PES-NMOS to resist TID effect. The key parameters are extracted from the simulation results, as shown in the following table

[0086] The channel doping concentration is 1×10 19 cm -3 Static characteristics of PES-NMOS under different TIDs

[0087]

[0088] Comparing the above table, it can be seen that when the channel doping concentration is increased, the threshold voltage change of NWaFET ΔV th and the shutdown current I off It is basically unchanged, indicating that NWaFET has a good ability to resist TID effect, and increasing the channel doping concentration has little effect on it. Figure 10-11 is the threshold voltage change of NWaFET under different channel doping concentrations ΔV th The relationship curves of TID and NWaFET are the turn-off current I under different channel doping concentrations. off Relationship curve with TID.

[0089] The embodiments described above are merely descriptions of preferred implementations of the present invention and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary persons in this field should fall within the scope of protection of the present invention. The technical contents for which protection is sought in the present invention have all been recorded in the claims.

Claims

1. A method for manufacturing a novel nano-wall NWaFET, characterized in that: The production method comprises the following steps: S1 epitaxial growth: first, epitaxial layers (2) having a certain thickness are grown in sequence on a P-type substrate (1) by epitaxial growth technology, wherein the epitaxial layers (2) are, from bottom to top, an N+ epitaxial layer (3), an N- epitaxial layer (4), a P+ epitaxial layer (5), and an intrinsic silicon layer (6); S2 etching: etching away the excess portion of the epitaxial layer (2), and the remaining portion serves as the N-drain region (7), the channel P+ region (8), and the intrinsic silicon injection layer (9); S3 thermal oxidation: The etched part is subjected to a thermal oxidation process to grow a SiO2 layer (17); S4 ion implantation: forming an N-source region (10) on the intrinsic silicon implantation layer (9) by an ion implantation process, and then forming an N+ source region (11) and a channel P+ region doped by ion implantation in the N-source region (10); S5: further etching to obtain an annular groove (12) and a rectangular groove (13); S6: depositing metal: depositing metal in the annular groove (12) and the rectangular groove (13).

2. The method for fabricating a novel nano-wall NWaFET according to claim 1, characterized in that: The N-drain region (7), the channel P+ region (8), the N-source region (10) and the N+ source region (11) together form an active region (14).

3. The method for fabricating a novel nano-wall NWaFET according to claim 2, characterized in that: In step S5, the annular groove (12) and the rectangular groove (13) are both required to be etched to above the N+ epitaxial layer (3), the annular groove (12) is obtained by etching with the active area (14) as the center, a SiO2 isolation layer (15) of a certain thickness is left at the bottom of the annular groove (12), a SiO2 gate oxide layer (16) of a certain thickness is left on the side of the annular groove (12), and the SiO2 in the rectangular groove (13) should be completely etched.

4. A method for verifying the novel nano-wall NWaFET according to any one of claims 1 to 3, characterized in that: The verification method comprises the following steps: S7 layout design and tape-out: Design devices with corresponding aspect ratios, set up comparison reference groups, and conduct sampling tests; S8 packaging: PCB packaging of the designed chip with radiation-resistant structural devices; S9 irradiation: subject the device to irradiation test.

5. The method for verifying a novel nano-wall NWaFET according to claim 4, characterized in that: In step S7, devices with five aspect ratios, namely 2:0.2, 2:0.6, 10:3, 30:3 and 30:9 (um), were sampled and tested at the same time.

6. The method for verifying a novel nano-wall NWaFET according to claim 5, characterized in that: The instruments used for sampling test are probe station and semiconductor parameter tester 4155B.

7. The method for verifying a novel nano-wall NWaFET according to claim 4, characterized in that: In step S8, the rectangle where the sample chip is packaged is 4mm long and 3mm wide. The entire board is 31mm long and 30mm wide, with a total of 24 pins. The PIN hole spacing is 2.54mm, and the hole spacing between P1 and P2 is 15mm. The words "DIP24" are on the right. All samples are soldered with 2.54mm pin headers, and a locking seat is used in the experiment to fix the irradiated chip.

8. The method for verifying a novel nano-wall NWaFET according to claim 4, characterized in that: In step S9, it is mainly divided into two parts. In the first part, some samples are irradiated, and the irradiation is stopped at the 200krad (Si) dose point and a displacement test is performed; in the second part, some samples are irradiated, and a displacement test is performed at the 300krad (Si), 600krad (Si), 900krad (Si), 1200krad (Si), 1500krad (Si), and 1800krad (Si) dose points respectively.

9. The method for verifying a novel nano-wall NWaFET according to claim 8, characterized in that: The test equipment is the institute's Keithley 4200-SCS / F semiconductor parameter test system. The sample to be tested is placed in a test box equipped with the 4200, and the ambient temperature during the test is room temperature.

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