A shallow trench isolation region and DRAM and a method for manufacturing the same.

Abstract

The present application relates to a kind of shallow trench isolation region and DRAM and its manufacturing method, belong to semiconductor technical field, solve the problem such as process complexity caused by using different etching equipment in existing process.The method includes: providing semiconductor substrate;Form lower mask layer, polysilicon mask layer, upper mask layer, spin-on hard mask layer and photoetching mask layer pattern in sequence above semiconductor substrate;Photoetching mask layer pattern is transferred to upper mask layer and polysilicon mask layer via spin-on hard mask layer to form aligned upper mask layer pattern and polysilicon mask layer pattern;With aligned upper mask layer pattern and polysilicon mask layer pattern as mask, lower mask layer and semiconductor substrate are etched in sequence in the same chamber to form the trench of shallow trench isolation region;And form dielectric layer in the trench to form shallow trench isolation region.In situ etching of lower mask layer and semiconductor substrate in the same chamber is realized, and process complexity is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a shallow trench isolation region and DRAM and a method for manufacturing the same. Background Technology

[0002] In DRAM manufacturing processes, the STI (Shallow Trench Isolation) regions that provide electrical insulation between active regions are formed using a hard mask created by photolithography and then etched using the hard mask in three separate steps: 1. Oxide etching / polysilicon etching; 2. Oxide etching; and 3. STI trench etching.

[0003] The formation of the STI region involves performing the above three etching steps using various different etching equipment, such as silicon etching equipment and dielectric etching equipment. Therefore, the increase in process steps leads to process complexity. Through the stacking of different stages, including managing CD target values, process complexity arises, along with difficulties in tracing the root causes. Summary of the Invention

[0004] Based on the above analysis, the embodiments of the present invention aim to provide a shallow trench isolation region and DRAM and a method for manufacturing the same, in order to solve the problems caused by the complexity of the existing STI region formation process due to the use of various different etching equipment.

[0005] On one hand, embodiments of the present invention provide a method for manufacturing a shallow trench isolation region, comprising: providing a semiconductor substrate; sequentially forming a lower mask layer, a polysilicon mask layer, an upper mask layer, a spin-coated hard mask layer, and a photolithographic mask layer pattern over the semiconductor substrate; transferring the photolithographic mask layer pattern via the spin-coated hard mask layer to the upper mask layer and the polysilicon mask layer to form aligned upper mask layer patterns and polysilicon mask layer patterns; using the aligned upper mask layer patterns and polysilicon mask layer patterns as masks, sequentially etching the lower mask layer and the semiconductor substrate in the same chamber to form trenches for the shallow trench isolation region; and forming a dielectric layer in the trenches to form the shallow trench isolation region.

[0006] The beneficial effects of the above technical solution are as follows: According to the shallow trench isolation region provided by the embodiment of the present invention, the lower mask layer and the semiconductor substrate are sequentially etched in situ in the same chamber (same etching equipment) to form the trench of the shallow trench isolation region, which omits the transfer step of the processing components, reduces the process complexity and manufacturing cost, and improves production efficiency, etc.

[0007] Based on a further improvement of the above method, after forming the spin-coated hard mask layer, the method further includes: sequentially forming an anti-reflection layer and a photomask layer on top of the spin-coated hard mask layer; and performing photolithography on the photomask layer to form a photomask layer pattern.

[0008] A further improvement to the above method, transferring the photolithographic mask layer pattern to the upper mask layer and the polysilicon mask layer via the spin-coated hard mask layer to form aligned upper mask layer patterns and polysilicon mask layer patterns, further includes: etching the spin-coated hard mask layer using the photolithographic mask layer pattern as a mask to form a spin-coated hard mask layer pattern; removing the photolithographic mask layer pattern located above the spin-coated hard mask layer pattern; etching the upper mask layer using the spin-coated hard mask layer pattern as a mask to form the upper mask layer pattern; etching the polysilicon mask layer using the aligned spin-coated hard mask layer pattern and upper mask layer pattern as masks to form the polysilicon mask layer pattern; and removing the spin-coated hard mask layer pattern.

[0009] Based on a further improvement of the above method, before etching the spin-coated hard mask layer, the method further includes: using the photolithography mask layer pattern as a mask to etch the anti-reflection layer to form an anti-reflection layer pattern; and after removing the photolithography mask layer pattern, removing the anti-reflection layer pattern.

[0010] Based on a further improvement of the above method, etching the lower mask layer further includes: etching the lower mask layer using the aligned upper mask layer pattern and polysilicon mask layer pattern as masks to form a lower mask layer pattern; etching the native oxide at the interface between the lower mask layer and the semiconductor substrate; and removing the aligned upper mask layer pattern and polysilicon mask layer pattern.

[0011] Further improvements to the above method include etching the semiconductor substrate to form the trench of the shallow trench isolation region, which further comprises: performing a first etching step on the upper part of the semiconductor substrate using the lower mask layer pattern as a mask to form the upper trench and rounding the top of the upper trench; performing a second etching step on the semiconductor substrate at the bottom of the upper trench using the lower mask layer pattern as a mask to form a lower trench with inclined sidewalls, wherein the lower trench is located below the upper trench; and performing a third etching step on the semiconductor substrate at the bottom of the lower trench using the lower mask layer pattern as a mask and rounding the bottom of the lower trench.

[0012] Based on a further improvement of the above method, in the second etching step, the tilt angle of the tilted sidewall is adjusted by changing the gas flow rate of Cl2 in the etching gas.

[0013] Based on a further improvement of the above method, in the second etching step, a mixed gas of Cl2, HBr and He is used, wherein the gas flow rate of HBr is 160 to 320 sccm and the gas flow rate of He is 400 to 600 sccm. When the gas flow rate of Cl2 is 280 to 400 sccm, an inclined sidewall with a first tilt angle is formed; and when the gas flow rate of Cl2 is 250 to 450 sccm, an inclined sidewall with a second tilt angle is formed, wherein the first tilt angle is smaller than the second tilt angle.

[0014] Based on further improvements to the above method, in the first etching step, the atmospheric pressure is 5 to 20 mT, the power supply is 300 to 600 W, the bias power is 300 to 500 W, the etching time is 5 to 15 seconds, the Cl2 gas flow rate is 300 to 500 sccm, the HBr gas flow rate is 150 to 300 sccm, and the He gas flow rate is 400 to 500 sccm. In the third etching step, the atmospheric pressure is 3 to 10 mT, the power supply is 100 to 300 W, the bias power is 15 to 30 W, the etching time is 3 to 10 seconds, the CHF3 gas flow rate is 200 to 300 sccm, the Ar gas flow rate is 200 to 300 sccm, and the O2 gas flow rate is 20 to 30 sccm.

[0015] Based on a further improvement of the above method, during the process of rounding the top of the upper trench and the bottom of the lower trench, O2 is used to locally oxidize the silicon at the top or bottom of the trench to form a rounded top and a rounded bottom, respectively.

[0016] Based on a further improvement of the above method, during the process of locally oxidizing the silicon at the top or bottom of the trench using O2, N2 or Ar is selectively added. Specifically, when locally oxidizing the silicon at the top of the trench, the atmospheric pressure is 5 to 20 mT, the power supply is 1000 to 2000 W, the etching time is 5 to 15 seconds, and the O2 gas flow rate is 160 to 320 sccm; and when locally oxidizing the silicon at the bottom of the trench, the atmospheric pressure is 3 to 10 mT, the power supply is 1200 to 1400 W, the etching time is 4 to 10 seconds, the Ar gas flow rate is 200 to 300 sccm, and the O2 gas flow rate is 20 to 30 sccm.

[0017] On the other hand, embodiments of the present invention provide a method for manufacturing DRAM, comprising: forming the shallow trench isolation region using the shallow trench isolation region manufacturing method described in the above embodiments.

[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0019] 1. In-situ etching of the lower mask layer and semiconductor substrate is performed sequentially in the same chamber (same etching equipment) to form trenches for shallow trench isolation regions. This eliminates the need for transfer steps of the processed components, reduces process complexity and manufacturing costs, and improves production efficiency.

[0020] 2. This application minimizes and integrates the equipment used in a single process, maximizing equipment operational compatibility. By simplifying the processing technology, the management of process parameters and target values ​​becomes easier, ensuring process reproducibility. Ultimately, this results in a manageable and streamlined process, ensuring the required process characteristics of the equipment, guaranteeing device margins, and enabling the manufacture of more stable devices.

[0021] 3. Rounding the top of the upper trench effectively suppresses stress and thus edge leakage current. Adjusting the tilt angle of the trench's inclined sidewalls by changing the Cl2 gas flow rate in the etching gas effectively reduces leakage current. Rounding the bottom of the lower trench improves device performance.

[0022] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0023] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0024] Figure 1 This is a cross-sectional view of an intermediate stage in a method for manufacturing a shallow trench isolation region according to an embodiment of the present invention.

[0025] Figure 2 This is a cross-sectional view of an intermediate stage in a method for manufacturing a shallow trench isolation region according to an embodiment of the present invention.

[0026] Figure 3 This is a cross-sectional view of an intermediate stage in a method for manufacturing a shallow trench isolation region according to an embodiment of the present invention.

[0027] Figure 4 This is a cross-sectional view of an intermediate stage in a method for manufacturing a shallow trench isolation region according to an embodiment of the present invention.

[0028] Figure 5This is a cross-sectional view of the trench after etching and rounding of the semiconductor substrate according to an embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of the in-situ etching formula in the manufacturing method of the shallow trench isolation region according to an embodiment of the present invention.

[0030] Figure label:

[0031] 100 - Semiconductor substrate; 102 - Lower mask layer; 104 - Polysilicon mask layer; 106 - Upper mask layer; 108 - Spin-coated hard mask layer; 110 - Anti-reflective layer; 112 - Photolithography mask layer pattern; 114 - Polysilicon mask layer pattern; 116 - Upper mask layer pattern; 118 - Trench; 120 - Lower mask layer pattern; 122 - Trench Detailed Implementation

[0032] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0033] One specific embodiment of the present invention discloses a method for manufacturing a shallow trench isolation region. Hereinafter, reference will be made to... Figures 1 to 4 The manufacturing process of the shallow trench isolation area is described in detail for each step.

[0034] refer to Figure 1 First, a semiconductor substrate 100 is provided. In this embodiment, the material of the semiconductor substrate 100 is silicon (Si).

[0035] refer to Figure 1 and Figure 2A lower mask layer 102, a polysilicon mask layer 104, an upper mask layer 106, a spin-on hard mask layer 108, and a photolithographic mask layer pattern 112 are sequentially formed above a semiconductor substrate 100. Specifically, the lower mask layer 102, polysilicon mask layer 104, upper mask layer 106, spin-on hard mask (SOH) layer 108, anti-reflection layer 110, and photolithographic mask layer are sequentially formed above the semiconductor substrate 100. Optionally, a spin-on hard mask layer 108 may also be included above the upper mask layer 106, and the photolithographic mask layer pattern 112 is formed on the spin-on hard mask layer 108. In an embodiment, the photolithographic mask layer is photolithographically etched to form the photolithographic mask layer pattern 112. In an embodiment, the material of the lower mask layer 102 may be pad oxide, for example, silicon oxide (SiO2). The material of the upper mask layer 106 can be an oxide produced by atomic layer deposition (ALD). The material of the anti-reflective layer 110 includes SiON. Spin-coated hard masks include spin-coated carbon, spin-coated silicon oxide, spin-coated silicon, etc.

[0036] refer to Figure 2 and Figure 3 The photolithographic mask layer pattern is transferred to the upper mask layer 106 and the polysilicon mask layer 104 via a spin-coated hard mask layer 108 to form an aligned upper mask layer pattern 116 and a polysilicon mask layer pattern 114. Specifically, transferring the photolithographic mask layer pattern 112 to the upper mask layer 106 and the polysilicon mask layer 104 via a spin-coated hard mask layer 108 to form an aligned upper mask layer pattern 116 and a polysilicon mask layer pattern 114 further includes: using the photolithographic mask layer pattern 112 as a mask, etching the antireflective layer 110 and the spin-coated hard mask layer 108 to form an aligned antireflective layer pattern and a spin-coated hard mask layer pattern; removing the photolithographic mask layer pattern 112 and the antireflective layer pattern located above the spin-coated hard mask layer pattern; and using the spin-coated hard mask... Using the layer pattern as a mask, the upper mask layer 106 is etched to form an upper mask layer pattern 116 aligned with the spin-coated hard mask layer pattern; the polysilicon mask layer 104 is etched using the aligned spin-coated hard mask layer pattern and the upper mask layer pattern 116 as masks to form a polysilicon mask layer pattern 114 and trenches 118 between adjacent polysilicon mask layer patterns 114; and the spin-coated hard mask layer pattern is removed, leaving the remaining upper mask layer pattern 116 and polysilicon mask layer pattern 114 as etching masks for subsequent steps.

[0037] refer to Figure 4Using aligned upper mask layer pattern 116 and polysilicon mask layer pattern 114 as masks, the lower mask layer 102 and semiconductor substrate 100 are sequentially etched in the same chamber to form trenches 122 for shallow trench isolation regions. Specifically, etching the lower mask layer 102 further includes etching the lower mask layer 102 using aligned upper mask layer pattern 116 and polysilicon mask layer pattern 114 as masks to form a lower mask layer pattern 120. For example, the atmospheric pressure is 10 to 50 mT, the power supply is 700 to 1100 W, the bias power is 500 to 900 W, the etching time is 10 to 50 seconds, the gas flow rate of C4H6 is 5 to 20 sccm, the gas flow rate of O2 is 10 to 20 sccm, the gas flow rate of Ar is 400 to 600 sccm, and the gas flow rate of He is 10 to 30 T. The native oxide at the interface between the lower mask layer 102 and the semiconductor substrate 100 is etched. For example, the atmospheric pressure is 5 to 20 mT, the power supply is 100 to 300 W, the bias power is 50 to 250 W, the etching time is 5 to 15 seconds, the CHF3 gas flow rate is 60 to 180 sccm, and the Ar gas flow rate is 120 to 360 sccm to remove the aligned upper mask layer pattern 116 and polysilicon mask layer pattern 114. Etching the semiconductor substrate 100 to form trenches for shallow trench isolation regions further includes the first to third etching steps described below. Hereinafter, reference is made to... Figure 5 The first to third etching steps are described in detail.

[0038] refer to Figure 5 Using the lower mask layer pattern 120 as a mask, a first etching step is performed on the upper part of the semiconductor substrate 100 to form an upper trench, and the top of the upper trench is rounded. Specifically, in the first etching step, the atmospheric pressure is 5 to 20 mT, the power supply is 300 to 600 W, the bias power is 300 to 500 W, the etching time is 5 to 15 seconds, the Cl2 gas flow rate is 300 to 500 sccm, the HBr gas flow rate is 150 to 300 sccm, and the He gas flow rate is 400 to 500 sccm. Then, during the rounding process of the top of the upper trench, O2 is used to locally oxidize the silicon at the top of the trench to form a rounded top. During the local oxidation of the silicon at the top of the trench using O2, N2 or Ar is selectively added. For example, when performing localized oxidation of silicon at the top of the trench, the atmospheric pressure is 5 to 20 mT, the power supply is 1000 to 2000 W, the etching time is 5 to 15 seconds, and the O2 gas flow rate is 160 to 320 sccm.

[0039] Compared with existing technologies, rounding the top of the upper trench can effectively suppress stress and thus effectively suppress edge leakage.

[0040] refer to Figure 5 A second etching step is performed on the semiconductor substrate 100 at the bottom of the upper trench using the lower mask layer pattern 120 as a mask to form a lower trench with sloping sidewalls, wherein the lower trench is located below the upper trench. Specifically, in the second etching step, the sloping angle of the sloping sidewalls is adjusted by changing the gas flow rate of Cl2 in the etching gas. In the second etching step, a mixed gas of Cl2, HBr, and He is used, wherein the gas flow rate of HBr is 160 to 320 sccm and the gas flow rate of He is 400 to 600 sccm. In an embodiment, when the gas flow rate of Cl2 is 280 to 400 sccm, a sloping sidewall with a first sloping angle is formed. When the gas flow rate of Cl2 is 250 to 450 sccm, a sloping sidewall with a second sloping angle is formed, wherein the first sloping angle is smaller than the second sloping angle. For example, when forming the inclined sidewall with a first tilt angle, the atmospheric pressure is 4 to 10 mT, the power supply is 800 to 1200 W, the bias power is 300 to 500 W (100 Hz / 50%), the Cl2 gas flow rate is 280 to 400 sccm, the He gas flow rate is 400 to 600 sccm, the HBr gas flow rate is 160 to 320 sccm, the temperature is 40 °C, and the etching time is 10 to 50 seconds. When forming the inclined sidewalls with the second tilt angle, the atmospheric pressure is 4 to 10 mT, the power supply is 800 to 1200 W, the bias power is 300 to 500 W (100 Hz / 30%), the Cl2 gas flow rate is 250 to 450 sccm, the He gas flow rate is 400 to 600 sccm, the HBr gas flow rate is 160 to 320 sccm, the temperature is 40 °C, and the etching time is 10 to 50 seconds.

[0041] Compared with existing technologies, the tilt angle of the inclined sidewall of the trench can be effectively reduced by changing the gas flow rate of Cl2 in the etching gas.

[0042] refer to Figure 5Using the lower mask layer pattern 120 as a mask, a third etching step is performed on the semiconductor substrate 100 at the bottom of the lower trench, and the bottom of the lower trench is rounded. In the third etching step, the atmospheric pressure is 3 to 10 mT, the power supply is 100 to 300 W, the bias power is 15 to 30 W, the etching time is 3 to 10 seconds, the CHF3 gas flow rate is 200 to 300 sccm, the Ar gas flow rate is 200 to 300 sccm, and the O2 gas flow rate is 20 to 30 sccm. Then, during the rounding process at the bottom of the lower trench, O2 is used to locally oxidize the silicon at the bottom of the trench to form a rounded bottom. During the local oxidation of the silicon at the bottom of the trench using O2, N2 or Ar is selectively added. For example, when performing localized oxidation of silicon at the bottom of the trench, the atmospheric pressure is 3 to 10 mT, the power supply is 1200 to 1400 W, the etching time is 4 to 10 seconds, the Ar gas flow rate is 200 to 300 sccm, and the O2 gas flow rate is 20 to 30 sccm.

[0043] Compared with existing technologies, rounding the bottom of the lower trench can improve the performance of the device.

[0044] A dielectric layer is formed in the trench to create a shallow trench isolation region. Specifically, a dielectric material layer is formed in the trench and planarized to create the shallow trench isolation region.

[0045] Compared with the prior art, the shallow trench isolation region manufacturing method provided in this embodiment sequentially etches the lower mask layer and the semiconductor substrate in the same chamber (same etching equipment) to form the trench of the shallow trench isolation region, omitting the transfer step of the processing components, reducing process complexity and manufacturing cost, and improving production efficiency.

[0046] The manufacturing method of shallow trench isolation areas will be described in detail below with specific examples.

[0047] After the photolithography process and the first etching step, using a recipe that combines the second etching step (oxide etching) and the third etching step (trench etching) into one step can effectively meet the target.

[0048] Figure 6 The recipes shown are implemented using a process apparatus, and the process parameters included in each recipe can be varied according to the target critical dimension (CD).

[0049] The process parameters include power supply, bias power, pressure, gas type, gas flow rate, and time. (Reference) Figure 6ME is the main etching process, BT (Break through) generally refers to the through etching of the natural oxide layer on the film surface, ME1 and OX1 are used to round the top corners of the STI trench structure, and BT2 and OX2 are used to round the bottom corners of the STI trench structure.

[0050] Additionally, this formulation may include an O2Flash Step to ensure engineering reproducibility by removing the resulting polymer. The polymer includes fluorocarbon polymers, such as CF2.

[0051] To simplify the STI process, instead of using different processing equipment for each material, a single processing unit is used to perform etching processes on multiple materials. This involves preparing etching formulas suitable for each material using a single unit and applying those formulas sequentially.

[0052] Compared with existing process solutions, the in-situ etching process of this application simplifies the process steps and reduces the overall process size. The proposed in-situ process solution minimizes and integrates the equipment used in a single process unit, maximizing equipment operational compatibility. Simplifying the processing technology simplifies the management of process parameters and target values, ensuring process reproducibility. Ultimately, this results in a manageable and streamlined process, ensuring the required process characteristics of the equipment, guaranteeing device margins, and enabling the manufacture of more stable devices.

[0053] Another specific embodiment of the present invention discloses a method for manufacturing DRAM, comprising: forming a shallow trench isolation region by the above-described method for manufacturing a shallow trench isolation region.

[0054] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0055] 1. In-situ etching of the lower mask layer and semiconductor substrate is performed sequentially in the same chamber (same etching equipment) to form trenches for shallow trench isolation regions. This eliminates the need for transfer steps of the processed components, reduces process complexity and manufacturing costs, and improves production efficiency.

[0056] 2. This application minimizes and integrates the equipment used in a single process, maximizing equipment operational compatibility. By simplifying the processing technology, the management of process parameters and target values ​​becomes easier, ensuring process reproducibility. Ultimately, this results in a manageable and streamlined process, ensuring the required process characteristics of the equipment, guaranteeing device margins, and enabling the manufacture of more stable devices.

[0057] 3. Rounding the top of the upper trench effectively suppresses stress and thus edge leakage current. Adjusting the tilt angle of the trench's inclined sidewalls by changing the Cl2 gas flow rate in the etching gas effectively reduces leakage current. Rounding the bottom of the lower trench improves device performance.

[0058] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0059] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of manufacturing a shallow trench isolation region, characterized by, Comprising: providing a semiconductor substrate; forming a lower mask layer, a polysilicon mask layer, an upper mask layer, a spin-on hard mask layer, and a photoresist mask layer pattern sequentially over the semiconductor substrate; transferring the photoresist mask layer pattern to the upper mask layer and the polysilicon mask layer via the spin-on hard mask layer to form an aligned upper mask layer pattern and polysilicon mask layer pattern; masking with the aligned upper mask layer pattern and polysilicon mask layer pattern, omitting the transferring step, in-situ etching the lower mask layer and the semiconductor substrate sequentially in the same chamber to form a trench of the shallow trench isolation region, wherein etching the lower mask layer further comprises: etching the lower mask layer to form a lower mask layer pattern, etching a native oxide at an interface between the lower mask layer and the semiconductor substrate, and removing the aligned upper mask layer pattern and polysilicon mask layer pattern; etching the semiconductor substrate to form the trench of the shallow trench isolation region further comprises: first etching an upper portion of the semiconductor substrate to form an upper trench and rounding a top of the upper trench with the lower mask layer pattern as a mask; second etching the semiconductor substrate at a bottom of the upper trench to form a lower trench with a slanted sidewall with the lower mask layer pattern as a mask, wherein a slanting angle of the slanted sidewall is adjusted by changing a gas flow of Cl2 in an etching gas, the lower trench is below the upper trench; and third etching the semiconductor substrate at a bottom of the lower trench and rounding the bottom of the lower trench with the lower mask layer pattern as a mask; and forming a dielectric layer in the trench to form the shallow trench isolation region.

2. The method of manufacturing a shallow trench isolation region according to claim 1, wherein, Further comprising, after forming the spin-on hard mask layer: forming an anti-reflective layer and a photoresist mask layer sequentially over the spin-on hard mask layer; and photolithographing the photoresist mask layer to form a photoresist mask layer pattern.

3. The method of manufacturing a shallow trench isolation region according to claim 2, wherein Transferring the photoresist mask layer pattern to the upper mask layer and the polysilicon mask layer via the spin-on hard mask layer to form an aligned upper mask layer pattern and polysilicon mask layer pattern further comprises: etching the spin-on hard mask layer to form a spin-on hard mask layer pattern with the photoresist mask layer pattern as a mask; removing the photoresist mask layer pattern over the spin-on hard mask layer pattern; etching the upper mask layer to form the upper mask layer pattern with the spin-on hard mask layer pattern as a mask; etching the polysilicon mask layer to form the polysilicon mask layer pattern with the aligned spin-on hard mask layer pattern and upper mask layer pattern as a mask; and removing the spin-on hard mask layer pattern.

4. The method of manufacturing a shallow trench isolation region according to claim 3, wherein Further comprising, before etching the spin-on hard mask layer: etching the anti-reflective layer to form an anti-reflective layer pattern with the photoresist mask layer pattern as a mask; and After the photoetching mask layer pattern is removed, the anti-reflection layer pattern is removed.

5. The method of manufacturing a shallow trench isolation region according to claim 1, wherein In the second etching step, a mixed gas of Cl2, HBr and He is used, wherein the gas flow rate of HBr is 160 to 320 sccm and the gas flow rate of He is 400 to 600 sccm, when the gas flow rate of Cl2 is 280 to 400 sccm, a tilted sidewall having a first tilt angle is formed; and when the gas flow rate of Cl2 is 250 to 450 sccm, a tilted sidewall having a second tilt angle is formed, wherein the first tilt angle is smaller than the second tilt angle.

6. The manufacturing method of a shallow trench isolation region according to claim 1, wherein, in the first etching step, the atmospheric pressure is 5 to 20 mT, the power supply power is 300 to 600 W, the bias power is 300 to 500 W, the etching time is 5 to 15 seconds, the gas flow rate of Cl2 is 300 to 500 sccm, the gas flow rate of HBr is 150 to 300 sccm and the gas flow rate of He is 400 to 500 sccm, and in the third etching step, the atmospheric pressure is 3 to 10 mT, the power supply power is 100 to 300 W, the bias power is 15 to 30 W, the etching time is 3 to 10 seconds, the gas flow rate of CHF3 is 200 to 300 sccm, the gas flow rate of Ar is 200 to 300 sccm and the gas flow rate of O2 is 20 to 30 sccm.

7. The method of manufacturing a shallow trench isolation region according to claim 1, wherein In the process of rounding the top of the upper trench and rounding the bottom of the lower trench, the silicon at the top or bottom of the trench is locally oxidized using O2 to form a rounded top and a rounded bottom, respectively.

8. The method of manufacturing a shallow trench isolation region according to claim 7, wherein, In the process of locally oxidizing the silicon at the top or bottom of the trench using O2, N2 or Ar is selectively added, wherein, when the silicon at the top of the trench is locally oxidized, the atmospheric pressure is 5 to 20 mT, the power supply power is 1000 to 2000 W, the etching time is 5 to 15 seconds and the gas flow rate of O2 is 160 to 320 sccm; and when the silicon at the bottom of the trench is locally oxidized, the atmospheric pressure is 3 to 10 mT, the power supply power is 1200 to 1400 W, the etching time is 4 to 10 seconds, the gas flow rate of Ar is 200 to 300 sccm and the gas flow rate of O2 is 20 to 30 sccm.

9. A method of manufacturing a DRAM, characterized by, comprising: forming the shallow trench isolation region using the manufacturing method of a shallow trench isolation region according to any one of claims 1 to 8.

Images