A lateral trench MOSFET device and a method of manufacturing the same

Abstract

The present application relates to a kind of transverse trench type MOSFET device and its manufacturing method.The present application is provided with first conductive type epitaxial layer on first conductive type substrate, longitudinal trench is provided in first conductive type epitaxial layer, gate is provided in longitudinal trench, second conductive type body region is provided on the surface of first conductive type epitaxial layer, the depth of second conductive type body region in first conductive type epitaxial layer is greater than the depth of longitudinal trench, first conductive type source and second conductive type source are provided in second conductive type body region, first conductive type source and longitudinal trench are connected, first conductive type drain adjacent to longitudinal trench is also provided in second conductive type body region.The transverse trench type MOSFET device and its manufacturing method provided by the present application and the manufacturing method of conventional longitudinal trench type MOSFET device are completely compatible, can realize transverse device without additional photoetching plate, without additional process step, facilitate the integration between devices.

Description

Technical Field

[0001] This invention relates to a semiconductor device and its manufacturing method, particularly a lateral trench MOSFET device and its manufacturing method. Background Technology

[0002] Semiconductor manufacturing processes are the means by which integrated circuits are realized and the foundation of integrated circuit design. Typically, for integrated circuits or digital circuits, a single process flow can be used to manufacture many devices. For example, the common BCD process can realize devices such as bipolar transistors, CMOS (complementary metal-oxide-semiconductor, usually including NMOS and PMOS), and DMOS (double-diffused metal-oxide-semiconductor field-effect transistor, usually LDMOS). Circuit designers can flexibly use these devices to design circuits. Due to the wide selection of devices, circuits implemented using this process have more functions and higher complexity.

[0003] For the fabrication of vertical power devices, since the high-voltage side of the manufactured vertical power device is on the back of the chip, it is difficult to interconnect multiple different types of devices. Therefore, this process can generally only manufacture a single device.

[0004] To realize power devices with driving or protection functions, there are generally two ways: one is to use two different processes to manufacture two chips, the integrated circuit and the power device, and then package these two chips into one chip to achieve integrated functions; the other is to use a process that can integrate vertical power devices and horizontal devices together, and manufacture vertical power devices and horizontal integrated circuits at the same time, so as to realize power devices with complex functions.

[0005] For a process method that can realize both vertical power devices and horizontal devices, it is required to minimize the number of photomasks (i.e., mask windows), because the number of photomasks is directly related to the production cost. The fewer the number of photomasks, the lower the production cost. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a lateral trench MOSFET device and its fabrication method, which is fully compatible with the manufacturing process of traditional vertical trench power MOSFET devices and facilitates the integration of vertical power devices and lateral devices.

[0007] To achieve the above technical objectives, the technical solution of the present invention is as follows: a lateral trench MOSFET device, comprising a substrate metal, a first conductivity type substrate disposed on the substrate metal, a first conductivity type epitaxial layer disposed on the first conductivity type substrate, a longitudinal trench composed of silicon dioxide insulating material disposed in the first conductivity type epitaxial layer, a gate composed of polysilicon material disposed in the longitudinal trench, a second conductivity type body region disposed on the surface of the first conductivity type epitaxial layer, the depth of the second conductivity type body region in the first conductivity type epitaxial layer being greater than the depth of the longitudinal trench, a heavily doped first conductivity type source and a second conductivity type source disposed on the surface of the second conductivity type body region, one side of the heavily doped first conductivity type source being connected to the longitudinal trench, the other side of the heavily doped first conductivity type source being connected to the heavily doped second conductivity type source, and a first conductivity type drain disposed on the surface of the first conductivity type epitaxial layer in the direction of horizontal extension of the longitudinal trench, the first conductivity type drain being connected to the longitudinal trench.

[0008] In one embodiment of the present invention, the first conductive type epitaxial layer and the surface of the longitudinal trench are further provided with an insulating medium, and the surface of the insulating medium is further provided with a source metal and a drain metal.

[0009] In one embodiment of the present invention, the source metal passes through an insulating medium and is connected to a heavily doped first conductivity type source and a second conductivity type source, and the drain metal passes through an insulating medium and is connected to a heavily doped first conductivity type drain.

[0010] In one embodiment of the present invention, for an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0011] A method for fabricating a lateral trench MOSFET device includes the following steps:

[0012] Step 1: Select a substrate material of the first conductivity type and epitaxially grow an epitaxial layer of the first conductivity type on its surface;

[0013] Step 2: Using a mask window, selectively etch longitudinal trenches on the upper surface of the first conductivity type epitaxial layer;

[0014] Step 3: Grow an oxide layer composed of silicon dioxide in the longitudinal trench, fill the longitudinal trench with polysilicon up to the surface of the first conductivity type epitaxial layer to form a gate, and remove the excess polysilicon;

[0015] Step 4: Implant ions of the second conductivity type onto the surface of the first conductivity type epitaxial layer, and form the second conductivity type body region by high-temperature annealing;

[0016] Step 5: Using a mask window, high concentrations of first and second conductivity type ions are implanted onto the surface of the second conductivity type body region, respectively. After high-temperature annealing, a heavily doped first conductivity type source, a first conductivity type drain, and a second conductivity type source are formed.

[0017] Step 6: Deposit an insulating dielectric on the surface of the first conductivity type epitaxial layer and the surface of the longitudinal trench, then selectively etch through holes on the insulating dielectric, then deposit metal and selectively etch the metal to form source metal, gate metal and drain metal, and deposit metal under the first conductivity type substrate to form substrate metal.

[0018] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: Based on the original vertical trench power MOSFET device manufacturing method, by adjusting the device layout, the manufacturing of lateral power MOSFET devices can be realized without increasing the number of mask windows, realizing the integration of vertical power devices and lateral devices, facilitating the expansion of more functions of power devices through the lateral circuit part, and improving the chip integration. Attached Figure Description

[0019] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein...

[0020] Figure 1 This is a three-dimensional structural diagram of the device structure of the present invention after removing the insulating medium and surface metal.

[0021] Figure 2 This is a three-dimensional structural diagram of the device structure of the present invention.

[0022] Figure 3 A three-dimensional structural diagram of a traditional trench power MOSFET device structure after removing the insulating dielectric and surface metal.

[0023] Figure 4 This is a three-dimensional structural diagram of a traditional trench power MOSFET device.

[0024] Figure 5 This is a cross-sectional view of the trench depth of longitudinal trenches of different widths within the same reaction time. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0029] Example 1

[0030] A lateral trench MOSFET device, wherein when the device is an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; and when the device is a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. This embodiment uses an N-type MOSFET device as an example. Figure 1 and Figure 2As shown, the system includes a substrate metal 101, an N-type substrate 102 on the substrate metal 101, an N-type epitaxial layer 103 on the N-type substrate 102, a longitudinal trench 105 composed of silicon dioxide insulating material in the N-type epitaxial layer 103, a gate 108 composed of polysilicon material in the longitudinal trench 105, a P-type body region 104 on the surface of the N-type epitaxial layer 103, the depth of the P-type body region 104 in the N-type epitaxial layer 103 being greater than the depth of the longitudinal trench 105, and heavily doped N-type source 107 and P-type source 109 on the surface of the P-type body region 104, one side of the heavily doped N-type source 107 being adjacent to the longitudinal trench 105. The heavily doped N-type source 107 is connected to the heavily doped P-type source 109 on the other side. In the direction of the horizontal extension of the longitudinal trench 105, an N-type drain 110 is also provided on the surface of the N-type epitaxial layer 103. The N-type drain 110 is connected to the longitudinal trench 105. An insulating medium 111 is also provided on the surface of the N-type epitaxial layer 103 and the longitudinal trench 105. A source metal 112 and a drain metal 113 are also provided on the surface of the insulating medium 111. The source metal 112 passes through the insulating medium 111 and is connected to the heavily doped N-type source 107 and the P-type source 109. The drain metal 113 passes through the insulating medium 111 and is connected to the heavily doped N-type drain 110.

[0031] In this embodiment, the drain is located on the device surface, facilitating device integration. The depth of the longitudinal trench in this invention is less than the depth of the P-type body region. When the device is turned on, a longitudinal current path from the N-type source to the N-type epitaxial layer will not be formed, and current will not flow into the N-type substrate located on the back of the device. Conversely, the P-type body regions on both sides of the gate are inverted into N-type channels, forming a current path from the N-type source to the N-type drain on the device surface.

[0032] Traditional vertical trench power MOSFET devices, such as Figure 3 , Figure 4As shown, the device includes a drain metal 201, an N-type substrate 202 on the drain metal 201, an N-type epitaxial layer 203 on the N-type substrate 202, a vertical trench 205 composed of silicon dioxide insulating material in the N-type epitaxial layer 203, a gate 208 composed of polysilicon material in the vertical trench 205, and a P-type body region 204 on the surface of the N-type epitaxial layer 203. The depth of the P-type body region 204 in the N-type epitaxial layer 203 is less than the depth of the vertical trench 205. The surface of region 204 is also provided with heavily doped N-type source 207 and P-type source 209. One side of the heavily doped N-type source 207 is connected to the longitudinal trench 205, and the other side of the heavily doped N-type source 207 is connected to the heavily doped P-type source 209. The surface of the N-type epitaxial layer 203 and the longitudinal trench 205 is also provided with an insulating medium 210. The surface of the insulating medium 210 is also provided with a source metal 211. The source metal 211 passes through the insulating medium 210 and is connected to the heavily doped N-type source 207 and P-type source 209.

[0033] From the perspective of device structure, the difference between the lateral trench MOSFET device provided by this invention and the traditional trench power MOSFET device is mainly reflected in two aspects: First, the longitudinal trench depth of the structure of this invention is smaller than that of the traditional structure, which is to ensure that the lateral trench MOSFET device provided by this invention will not form a longitudinal channel; Second, compared with the traditional longitudinal structure, the structure of this invention has an additional N-type drain and drain metal on the surface.

[0034] The above two differences can be achieved by adjusting the device layout (i.e., design drawing) without adding an additional photomask. Specifically, this will be analyzed in detail through the manufacturing method of the present invention.

[0035] The manufacturing method based on this embodiment includes the following steps:

[0036] Step 1: Select an N-type substrate 102 and epitaxially grow an N-type epitaxial layer 103 on its surface;

[0037] Step 2: Using a mask window, longitudinal trenches 105 are selectively etched on the upper surface of the N-type epitaxial layer 103;

[0038] Step 3: An oxide layer composed of silicon dioxide is grown in the longitudinal trench 105, and polysilicon is filled into the longitudinal trench to the surface of the N-type epitaxial layer to form the gate 108, and the excess polysilicon is removed.

[0039] Step 4: P-type ions are implanted onto the surface of the N-type epitaxial layer 103, and then the P-type body region 104 is formed by high-temperature annealing;

[0040] Step Five: Using a mask window, high-concentration N-type ions and P-type ions are respectively implanted on the surface of the P-type body region 104. After high-temperature annealing, heavily doped N-type source 107, N-type drain 110, and P-type source 109 are formed.

[0041] Step Six: An insulating dielectric 111 is deposited on the surface of the N-type epitaxial layer 103 and the surface of the longitudinal trench 105. Then, vias are selectively etched in the insulating dielectric 111. Subsequently, metal is deposited and selectively etched to form source metal 112, gate metal, and drain metal 113. Metal is deposited below the N-type substrate 102 to form substrate metal 101.

[0042] When implementing the longitudinal trench process, a dry etching process is usually used. First, lithography masks (mask windows) are used to achieve longitudinal trench windows of different widths. Then, plasma is used to bombard the wafer surface. For wider longitudinal trenches, the reaction area between the plasma and the wafer surface is larger. For narrower longitudinal trenches, the reaction area between the plasma and the wafer surface is smaller. This results in a smaller etched depth for the narrower longitudinal trenches within the same reaction time. Figure 5 is the trench depth of longitudinal trenches with different widths within the same reaction time. As can be seen from the figure, the larger the trench width, the deeper the depth. Therefore, longitudinal trenches with different depths can be fabricated using the same lithography mask.

[0043] For the lateral trench type MOSFET device and the traditional trench type power MOSFET device provided by the present invention, as Figure 1 and 3 shown, as long as w1 < w2 is ensured during device design, in the finally formed device, the trench depth of the lateral trench type MOSFET device will be smaller than that of the traditional trench type power MOSFET device. By adjusting the implantation conditions and annealing conditions of the P-type body region, it can be ensured that in the lateral trench type MOSFET device, the depth of the longitudinal trench is less than the depth of the P-type body region.

[0044] The N-type drain and drain metal are fabricated on the device surface. Since the N-type drain and N-type source can be formed using the same lithography mask, only the implantation window of the N-type drain needs to be drawn in the layout. For the formation of the drain metal, the same lithography mask as that of the source metal is used. Therefore, only the area where the drain metal needs to be retained needs to be drawn in the layout to be realized in the process.

[0045] In summary, the manufacturing method of the lateral trench MOSFET device provided by the present invention is fully compatible with the manufacturing method of the traditional trench power MOSFET device. It can form the lateral trench MOSFET device without adding an additional photomask or additional process steps, which facilitates the integration between lateral devices and forms a circuit with certain functions to protect or drive the vertical power MOSFET device.

[0046] The present invention and its embodiments have been described above. This description is not restrictive, and the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for fabricating a lateral trench MOSFET device, characterized in that, A lateral trench MOSFET device includes a substrate metal, on which a first conductivity type substrate is disposed, and on the first conductivity type substrate a first conductivity type epitaxial layer is disposed. A longitudinal trench composed of silicon dioxide insulating material is disposed in the first conductivity type epitaxial layer, and a gate composed of polysilicon material is disposed within the longitudinal trench. A second conductivity type body region is also disposed on the surface of the first conductivity type epitaxial layer. The depth of the second conductivity type body region in the first conductivity type epitaxial layer is greater than the depth of the longitudinal trench. A heavily doped first conductivity type source and a second conductivity type source are also disposed on the surface of the second conductivity type body region. One side of the heavily doped first conductivity type source is connected to the longitudinal trench, and the other side of the heavily doped first conductivity type source is connected to the heavily doped second conductivity type source. A first conductivity type drain is also disposed on the surface of the first conductivity type epitaxial layer in the direction of the horizontal extension of the longitudinal trench, and the first conductivity type drain is connected to the longitudinal trench. The first type of conductive epitaxial layer and the surface of the longitudinal trench are further provided with an insulating medium, and the surface of the insulating medium is further provided with a source metal and a drain metal; The source metal passes through the insulating medium and is connected to the heavily doped first conductivity type source and the second conductivity type source; the drain metal passes through the insulating medium and is connected to the heavily doped first conductivity type drain. The production method includes the following steps: Step 1: Select a substrate material of the first conductivity type and epitaxially grow an epitaxial layer of the first conductivity type on its surface; Step 2: Using a mask window, selectively etch longitudinal trenches on the upper surface of the first conductivity type epitaxial layer; Step 3: Grow an oxide layer composed of silicon dioxide in the longitudinal trench, fill the longitudinal trench with polysilicon up to the surface of the first conductivity type epitaxial layer to form a gate, and remove the excess polysilicon; Step 4: Implant ions of the second conductivity type onto the surface of the first conductivity type epitaxial layer, and form the second conductivity type body region by high-temperature annealing; Step 5: Using a mask window, high concentrations of first and second conductivity type ions are implanted onto the surface of the second conductivity type body region, respectively. After high-temperature annealing, a heavily doped first conductivity type source, a first conductivity type drain, and a second conductivity type source are formed. Step 6: Deposit an insulating dielectric on the surface of the first conductivity type epitaxial layer and the surface of the longitudinal trench, then selectively etch through holes on the insulating dielectric, then deposit metal and selectively etch the metal to form source metal, gate metal and drain metal, and deposit metal under the first conductivity type substrate to form substrate metal.

2. The method for fabricating a lateral trench MOSFET device according to claim 1, characterized in that, For N-type power semiconductor devices, the first conductivity type is N-type and the second conductivity type is P-type; for P-type power semiconductor devices, the first conductivity type is P-type and the second conductivity type is N-type.

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