Semiconductor epitaxial wafer

Abstract

A semiconductor epitaxial wafer comprises a substrate, a first epitaxial stacking structure, a first ohmic contact layer and a second epitaxial stacking structure. The ohmic contact layer is characterized in that a compound with a low nitrogen content is used, and the ohmic contact layer does not generate significant stress during the crystal growth process. In this way, the second epitaxial stacking structure formed on the ohmic contact layer can have good epitaxial quality. Thus, a high-quality semiconductor epitaxial wafer for manufacturing GaAs integrated circuits or InP integrated circuits is provided, while the ohmic contact characteristics of the ohmic contact layer are not affected and the reactants generated during the dry etching process are reduced.

Description

Technical Field

[0001] A semiconductor epitaxial wafer, in particular a semiconductor epitaxial wafer capable of manufacturing GaAs integrated circuits or InP integrated circuits, does not use a GaN material system, wherein an ohmic contact layer with low nitrogen content and no significant stress relative to a substrate is provided between two semiconductor components, wherein the two semiconductor components are in a vertically stacked relative relationship. Background Art

[0002] In the semiconductor field, whether it is the study of semiconductor physics and material properties or the production of semiconductor components, the contact between metal and semiconductor plays an extremely important role, and the quality of contact performance directly affects the quality of semiconductor components. Metal-semiconductor contacts are generally divided into two categories: one is the Schottky contact with rectification effect; the other is the ohmic contact without rectification effect. Usually, semiconductor components use ohmic contact for electrical connection. The quality of ohmic contact, the size of contact resistance and heat dissipation will affect the efficiency, RF characteristics, optoelectronic characteristics, noise, gain or switching speed of semiconductor components. Generally speaking, the smaller the ohmic contact resistance between the metal and semiconductor layers, the better, which requires good ohmic contact. The better the ohmic contact performance, the lower the ohmic contact resistance.

[0003] See also Figure 1 , Figure 1 This is a schematic diagram of a prior art heterojunction bipolar transistor (HBT). The emitter ohmic contact layer generally uses indium gallium arsenide (InGaAs). In the case of U.S. Patent Publication No. 2003 / 0025128 A1, it is disclosed that the emitter ohmic contact layer is indium gallium arsenide antimonide (InGaAsSb). It can be seen that the existing ohmic contact layer uses a material containing indium to reduce the resistance of the emitter ohmic contact layer.

[0004] InGaAs or InGaAsSb ohmic contact layers are usually formed on GaAs or AlGaAs. Taking the InGaAs ohmic contact layer and GaAs as an example, because the lattice constant of InGaAs is greater than the lattice constant of GaAs, InGaAs will produce compressive stress during the epitaxial growth of InGaAs. When the thickness of the InGaAs layer exceeds its critical thickness, defects or dislocations are easily generated in the InGaAs layer. Therefore, when a multi-layer epitaxial layer is formed on the defective or dislocated InGaAs ohmic contact layer, the multi-layer epitaxial layer on the InGaAs ohmic contact layer is also prone to defects, dislocations or poor surface morphology. As a result, the quality of the epitaxial layer on the InGaAs ohmic contact layer is poor. Due to this limitation, it is difficult to produce another semiconductor component of good quality on the InGaAs layer or the InGaAsSb ohmic contact layer. It is also difficult to achieve highly integrated or high-quality GaAs (gallium arsenide) integrated circuits.

[0005] Generally, to form a good ohmic contact, the ohmic contact layer needs to use a material with a smaller energy gap. For InGaAs and InGaAsSb, by increasing the indium (In) content, the energy gap of InGaAs and InGaAsSb can be made smaller. However, increasing the In content will produce more reactants in the dry etching process because of the increase in In. Therefore, it is necessary to frequently remove the reactants remaining in the chamber and exhaust system. In other words, it directly affects the production capacity, yield or increases the cost.

[0006] In addition, when the substrate and the ohmic contact layer are GaAs and InGaAs (Sb) respectively, there will be a large lattice mismatch between the GaAs substrate and the InGaAs (Sb) ohmic contact layer, resulting in significant stress in the InGaAs (Sb) ohmic contact layer, which is prone to defects, dislocation or poor surface morphology; when the ohmic contact layer is GaAs and the substrate is GaAs, although the lattice constant of the GaAs ohmic contact layer is the same as that of the substrate, the energy gap of the GaAs ohmic contact layer is too large and the ohmic contact characteristics are poor. Although the energy gap of the InGaAs (Sb) ohmic contact layer can be reduced by increasing the In content, it has the disadvantages mentioned above. Summary of the invention

[0007] The object of the present invention is to solve the shortcomings and limitations of the prior art and provide a GaAs integrated circuit or InP integrated circuit with good epitaxial quality while not affecting the ohmic contact characteristics of the ohmic contact layer and reducing the reactants generated during the dry etching process.

[0008] In one embodiment, a semiconductor epitaxial wafer includes a substrate, a first epitaxial stack structure, an ohmic contact layer, and a second epitaxial stack structure. The characteristic is that the ohmic contact layer uses a compound with a low nitrogen content, and the lattice mismatch between the ohmic contact layer and the substrate is controlled so that the ohmic contact layer does not have obvious stress relative to the GaAs substrate during the crystal growth process, so the ohmic contact layer has fewer defects and dislocations or has a better surface morphology. In this way, a second epitaxial stack structure with a sufficient number of layers and good crystal quality can continue to be formed on the ohmic contact layer. In addition, although the ohmic contact layer uses a compound with a low nitrogen content, it does not significantly increase the contact resistance of the ohmic contact layer.

[0009] In one embodiment, an ohmic contact layer with a low nitrogen content is further disposed between the substrate and the first epitaxial stack structure or within the first epitaxial stack structure.

[0010] In one embodiment, the low nitrogen content material of the “ohmic contact layer” may be GaAsN, GaAsNSb, GaAsNBi, GaAsNSbBi, InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi.

[0011] Provided is a semiconductor epitaxial wafer capable of producing GaAs integrated circuits or InP integrated circuits with good epitaxial quality. The so-called GaAs integrated circuit or InP integrated circuit means that the substrate uses a GaAs substrate, a Ge substrate or an InP substrate, and the first and second epitaxial stacking structures use a GaAs material system or an InP material system according to the type of substrate. It is worth noting that the first and second epitaxial stacking structures do not use a GaN material system.

[0012] In one embodiment, the first epitaxial stack structure further includes a semiconductor layer, which is in direct or indirect contact with the ohmic contact layer. When the epitaxial wafer is used to make a GaAs integrated circuit, the substrate can be a Ge substrate or a GaAs substrate, and the semiconductor layer can be GaAs, AlGaAs, InAlAs, InGaP or InGaAs, and the first and second epitaxial stack structures use a GaAs material system (GaAs-based material). When the epitaxial wafer is used to make an InP integrated circuit, it means that the substrate is an InP substrate, the semiconductor layer can be InAlAs, InGaP, InP, InAlGaAs and InGaAsP, and the first and second epitaxial stack structures use an InP material system (InP-based material). The GaAs integrated circuit or InP integrated circuit referred to herein refers to a plurality of semiconductor components in a vertical stacking relationship (relative relationship) in an epitaxial wafer.

[0013] Compared to the prior art, because the ohmic contact layer is a low-nitrogen material such as "GaAsN", "InGaAsN", etc., the carrier barrier between the "N-type ohmic contact layer" and the "N-type ohmic contact metal" will decrease (compared to the prior art InGaAs), so the ohmic contact characteristics of the "N-type ohmic contact layer" and the "N-type ohmic contact metal" are better. Similarly, compared to the prior art, when the ohmic contact layer is (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi, because the ohmic contact layer contains Sb or Bi, the carrier barrier between the "P-type ohmic contact layer" and the "P-type ohmic contact metal" will decrease (compared to InGaAs), so the ohmic contact characteristics of the "P-type ohmic contact layer" and the "P-type ohmic contact metal" may be better.

[0014] On the other hand, the energy gap of InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi is lower than that of InGaAs (InGaAsSb), so the In content in InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi can be reduced. Therefore, the reactants generated in each dry etching process become less, which will extend the cleaning and maintenance cycle of the equipment and reduce the frequency of equipment cleaning and maintenance, which is beneficial to improving production capacity, yield or reducing costs.

[0015] Preferably, the lattice mismatch between "ohmic contact layer and Ge", "ohmic contact layer and GaAs" or "ohmic contact layer and InP" needs to be less than about ±10000ppm. By making the lattice constant of the ohmic contact layer close to the lattice constant of the substrate, the ohmic contact layer will not cause obvious stress during crystal growth, so the critical thickness of the ohmic contact layer can be thicker. In other words, the ohmic contact layer is not prone to defects, dislocation or surface morphology degradation. In this way, it is easy to epitaxially grow one or more epitaxial layers of good quality on the ohmic contact layer.

[0016] In one embodiment, a “band gap gradient layer” is further disposed between the ohmic contact layer and the semiconductor layer adjacent thereto, wherein the “band gap gradient layer” can help electrons to cross a higher electron barrier.

[0017] The "ohmic contact layer" using GaAsN, GaAsNSb, GaAsNBi, GaAsNSbBi, InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi can form an ohmic contact with most metal materials used for ohmic contact. The energy gap of the material of the low nitrogen ohmic contact layer is smaller, and a better ohmic contact can be achieved.

[0018] In one embodiment, a semiconductor epitaxial wafer includes a substrate, a first epitaxial stack structure, and an ohmic contact layer with a low nitrogen content. The ohmic contact layer with a low nitrogen content is disposed between the substrate and the first epitaxial stack structure, in the first epitaxial stack structure, or includes both. The implementation method of the ohmic contact layer is the same as the above-mentioned ohmic contact layer.

[0019] The first epitaxial stack structure and the second epitaxial stack structure can form a first semiconductor component and a second semiconductor component. According to different application purposes, the first semiconductor component and the second semiconductor component can be the same or different semiconductor components. The first semiconductor component or the second semiconductor component can be a field effect transistor (FET), a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (PHEMT), a bipolar junction transistor (BJT), a bipolar field effect transistor (BiFET), a bipolar high-electron mobility transistor (BiHEMT), a photodiode (PD), a laser diode (LD), an edge emitting laser diode (EEL), a vertical cavity surface emitting laser diode (VCSEL), a variable capacitor (varactor), a (pnpn) resistor, a light emitting diode (LED), a solar cell (Solar) or a light emitting diode (LED). Cell, SC). BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a heterojunction bipolar transistor (HBT) of the prior art, wherein the ohmic contact layer and the emitter cap layer are InGaAs and GaAs respectively.

[0021] Figure 2 FIG. 1 is a schematic diagram of a HBT according to a first embodiment of the present disclosure, wherein an ohmic contact layer is located on the top of the HBT.

[0022] Figure 3 is a schematic diagram of an HBT according to a second embodiment of this specification.

[0023] Figure 4 FIG. 4 is a schematic diagram of a VCSEL according to the third embodiment of the present specification.

[0024] Figure 5 It is a schematic diagram of an EEL according to the fourth embodiment of this specification.

[0025] Figure 6 It is a schematic diagram of an embodiment of the metal electrode of this specification.

[0026] Figure 7 It is a schematic diagram of an embodiment of a gallium arsenide (GaAs) integrated circuit of this specification.

[0027] Figure 8 FIG. 2 is a schematic diagram of another embodiment of a gallium arsenide (GaAs) integrated circuit of the present specification.

[0028] Figure 9a is Figure 2 Schematic diagram of forming multiple epitaxial layers on the first ohmic contact layer (InGaAsN).

[0029] Figure 9b is Figure 1 Schematic diagram of forming multiple epitaxial layers on the ohmic contact layer (InGaAs).

[0030] Fig.10a and Fig.10b Photographed with an optical microscope Figure 9a and Figure 9b Image of the surface morphology on top of an epitaxial wafer.

[0031] Fig.11 This is a schematic diagram of the measurement results of TLM resistance.

[0032] Main component symbols

[0033] 1' base plate

[0034] 2' sub-collector layer

[0035] 3' Collector layer

[0036] 4' Base layer

[0037] 5' emitter layer

[0038] 6' emitter cap

[0039] 7' Ohmic contact layer

[0040] 10 substrate

[0041] 20 collector layers

[0042] 30 Collector layer

[0043] 40 Base layer

[0044] 50 emitter layer

[0045] 60 Emitter cap layer

[0046] 71 First Ohmic Contact Layer

[0047] 72 Second ohmic contact layer

[0048] 80 Metal

[0049] 1 substrate

[0050] 2 Buffer layer

[0051] 3 Lower distributed Bragg reflector layer

[0052] 4 Lower compartment

[0053] 5 Active Layer

[0054] 6 Upper spacer

[0055] 7 Upper Distributed Bragg Reflector Layer

[0056] 73 Third ohmic contact layer

[0057] 100 substrates

[0058] 200 Buffer layer

[0059] 300 Lower cladding layer

[0060] 400 Lower compartment

[0061] 500 Active Layer

[0062] 600 Upper compartment

[0063] 700 Upper coating

[0064] 74 Fourth ohmic contact layer

[0065] L1 InGaP layer

[0066] L2 C-GaAs layer

[0067] L3 Si-GaAs layer

[0068] L4 i-GaAs layer

[0069] L5 C-GaAs layer

[0070] S1 Top

[0071] S2 top surface. DETAILED DESCRIPTION

[0072] The following is a more detailed description of the embodiments of the present invention with reference to the accompanying drawings and component symbols, so that those skilled in the art can implement the embodiments according to the embodiments after reading the specification.

[0073] The following describes specific examples of components and their arrangement to simplify the present invention. Of course, these are only examples and should not be used to limit the scope of the present invention. For example, when a layer is mentioned on top of another layer in the description, it may include an embodiment in which the layer is in direct contact with the other layer, and it may also include an embodiment in which there are other components or epitaxial layers formed between the two without direct contact. In addition, repeated numbers and / or symbols may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments, and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0074] In addition, spatially related terms may be used, such as "below", "below", "lower", "above", "upper" and similar terms, which are used to facilitate the description of the relationship between one (some) component or feature and another (some) component or feature in the drawings. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the drawings.

[0075] The present specification provides different embodiments to illustrate the technical features of different implementation methods. For example, "some embodiments" referred to in the full specification means that a specific feature, structure, or characteristic described in the embodiment is included in at least one embodiment. Therefore, the phrase "in some embodiments" appearing in different places in the full specification does not necessarily refer to the same embodiment.

[0076] In addition, specific features, structures, or characteristics can be combined in one or more embodiments by any suitable method. Further, for the terms "including", "having", "having", "wherein" or the aforementioned changes used herein, these meanings are similar to the term "comprising" to include corresponding features.

[0077] In addition, a “layer” may be a single layer or may include multiple layers; and a “part” of an epitaxial layer may be a single layer or multiple adjacent layers of the epitaxial layer.

[0078] Figure 2 is a schematic diagram of the HBT according to the first embodiment of this specification.

[0079] like Figure 2 As shown in FIG. 1 , the first embodiment is an exemplary structure of an HBT. Figure 2 As shown, the semiconductor device is described by taking HBT as an example; according to the first embodiment, the HBT includes a substrate 10, a sub-collector layer 20, a collector layer 30, a base layer 40, an emitter layer 50, an emitter cap layer 60 and a first ohmic contact layer 71. Figure 2 As shown, the first ohmic contact layer 71 is formed on the emitter cap layer 60 , and a metal (emitter) electrode (not shown) is formed on the first ohmic contact layer 71 .

[0080] In some embodiments, the emitter layer 50 is the top layer of the HBT, and the first ohmic contact layer 71 is in ohmic contact with the emitter layer 50. The actual location and method of the first ohmic contact layer 71 depend on the requirements, as long as it is set between the semiconductor layer and the metal material.

[0081] Figure 3 Schematic diagram of the HBT of the second embodiment of this specification. Figure 3 As shown, compared with the first embodiment, the second embodiment further comprises a second ohmic contact layer 72. The second ohmic contact layer 72 is disposed between the substrate 10 and the sub-collector layer 20. Alternatively, the second ohmic contact layer 72 is disposed on the base layer or a suitable epitaxial layer.

[0082] The following content takes a laser diode as an example. The laser diode can be selectively provided with a buffer layer according to actual needs, and in some examples, the buffer layer and the substrate can be made of the same material. Whether or not a buffer layer is provided has no substantial relevance to the technical features and effects to be provided in the following embodiments. Therefore, for the sake of simplicity, the following embodiments only use a laser diode with a buffer layer as an example for illustration, and do not further describe a laser diode without a buffer layer. That is, the following embodiments can also be applied in an integrated manner by replacing a laser diode without a buffer layer.

[0083] Figure 4 FIG. 4 is a schematic diagram of a VCSEL according to the third embodiment of the present specification. Figure 4 This shows the structure of a surface-emitting laser diode. Figure 4 The VCSEL shown includes a substrate 1 , a buffer layer 2 , a lower distributed Bragg reflector (DBR) layer 3 , a lower spacer layer 4 , an active layer 5 , an upper spacer layer 6 , an upper distributed Bragg reflector (DBR) layer 7 and a third ohmic contact layer 73 .

[0084] In one embodiment, another third ohmic contact layer 73 is further included. The third ohmic contact layer 73 can be disposed on Figure 4 The buffer layer 2 of the VCSEL, wherein part or all of the buffer layer 2 is a third ohmic contact layer; or, Figure 4 The VCSEL can include a plurality of third ohmic contact layers 73 , so the third ohmic contact layer 73 can be formed in or on the buffer layer 2 , and the third ohmic contact layer 73 can be formed on the upper DBR layer 7 .

[0085] In one embodiment, a portion of the lower DBR layer 3, the lower spacer layer 4, the upper spacer layer 6 or the upper DBR layer 7 includes an ohmic contact layer having a low nitrogen content.

[0086] Figure 5 It is a schematic diagram of an EEL according to the fourth embodiment of this specification. Figure 5 This shows the structure of an edge-emitting laser diode. Figure 5 The EEL shown includes a substrate 100 , a buffer layer 200 , a lower cladding layer 300 , a lower spacer layer 400 , an active layer 500 , an upper spacer layer 600 , an upper cladding layer 700 , and a fourth ohmic contact layer 74 .

[0087] In each of the above embodiments, the substrate 10 can be a Ge substrate, a GaAs substrate or an InP substrate according to the required characteristics of the semiconductor device. The characteristics generally include electrical or optical characteristics.

[0088] Any of the first to fourth ohmic contact layers 71 to 74 may use (In)GaAsN, (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi. To simplify the description, the term "ohmic contact layer" is used herein to represent the first ohmic contact layer 71 , the second ohmic contact layer 72 , the third ohmic contact layer 73 or the fourth ohmic contact layer 74 .

[0089] The Ge substrate can be used in combination with the ohmic contact layer material (In)GaAsN, (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi (i.e., GaAsN, GaAsNSb, GaAsNBi, GaAsNSbBi, InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi); the GaAs substrate can be used in combination with the ohmic contact layer material (In)GaAsN, (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi; or, the InP substrate can be used in combination with the ohmic contact layer material (In)GaAsN, (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi.

[0090] The lattice mismatch between "the ohmic contact layer and Ge", "the ohmic contact layer and GaAs" or "the ohmic contact layer and InP" is approximately between 0 and 10000 ppm. The lattice mismatch refers to the difference between the lattice constant of the substrate and the lattice constant of the ohmic contact layer. In other words, the substrate has a first lattice constant X1, the ohmic contact layer has a second lattice constant X2, and the lattice mismatch is X1-X2. Among them, the lattice mismatch can be ±300, ±1000, ±1500, ±2000, ±2500, ±3000, ±4000 or ±5000 ppm, etc. The "+" sign represents compressive stress, and the "-" sign represents tensile stress.

[0091] In x Ga 1-x As y N 1-y 、In x Ga 1-x As y N z Sb 1-y-z 、In x Ga 1-x As y N z Bi 1-y-z or In x Ga 1- x As y N z Sb w Bi 1-y-z-w , where x is 0 to 1, for example, x can be: 0, 0.05, 0.10, 0.15, 0.20, 0.25, 0.30, 0.35, 0.50, 0.55, 0.60, 0.65, 0.70, or 0.75. Preferably, when the substrate is GaAs or Ge, the value of x is about 0.05 to 0.3. When the substrate is InP, the value of x is about 0.5 to 0.75. And y, z, w are 0.001 to 0.2, where y, z or w can be: 0.005, 0.010, 0.015, 0.020, 0.021, 0.03, 0.04 or 0.05.

[0092] The thickness of the ohmic contact layer is approximately between 5 nm and 1000 nm. The thickness of the ohmic contact layer may be 50, 100, 200, 400, 500, 700 or 900 nm.

[0093] Taking the (In)GaAsN ohmic contact layer as a representative example, since the lattice constant of the (In)GaAsN ohmic contact layer is close to that of Ge, GaAs or AlGaAs, the ohmic contact layer will not have obvious stress during the crystal growth process. In this way, a multi-layer epitaxial layer with good crystal quality can continue to be formed on the ohmic contact layer. In other words, another component can be formed on the (In)GaAsN ohmic contact layer. Based on this, an integrated circuit is provided. Figure 7 and Figure 8 Two different gallium arsenide (GaAs) integrated circuits are shown, wherein the GaAs integrated circuit includes at least two semiconductor devices.

[0094] The prior art uses an ohmic contact layer of (In)GaAs or (In)GaAsSb. Compared to the prior art, because the ohmic contact layer is a low-nitrogen material such as (In)GaAsN, the carrier barrier between the "N-type ohmic contact layer" and the "N-type ohmic contact metal" will be reduced (compared to the prior art InGaAs), so the ohmic contact characteristics of the "N-type ohmic contact layer" and the "N-type ohmic contact metal" may be better.

[0095] Similarly, compared to the prior art, when the ohmic contact layer is (In)GaAsNSb, (In)GaAsNBi or (In)GaAsNSbBi, because the ohmic contact layer contains Sb or Bi, the carrier barrier between the "P-type ohmic contact layer" and the "P-type ohmic contact metal" will be reduced (compared to the InGaAs ohmic contact layer), so the ohmic contact characteristics of the "P-type ohmic contact layer" and the "P-type ohmic contact metal" may be better.

[0096] When the ohmic contact layer is InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi, since the energy gap of the ohmic contact layer is lower than that of the prior art, the In content in InGaAsN, InGaAsNSb, InGaAsNBi or InGaAsNSbBi can be reduced, so that during each dry etching process, the generated reactants become less, which can extend the cleaning and maintenance cycle or reduce the frequency of cleaning and maintenance, which is beneficial to improving production capacity or reducing costs. In particular, when the ohmic contact layer is GaAsN, GaAsNSb, GaAsNBi or GaAsNSbBi, since it does not contain In, during the dry etching process, the generated reactants will be very small, which can extend the cleaning and maintenance cycle or reduce the frequency of cleaning and maintenance, which is beneficial to improving production capacity or reducing costs.

[0097] In some embodiments, the ohmic contact layer is further doped with a doping material, and the doping material includes Te, Se, Si, Sn, Ge, S, C, Zn or Cd. Generally speaking, C, Zn and Cd can be doped in the ohmic contact layer alone, but two or three of the above can also be doped in the ohmic contact layer. Te, Se, Si, Sn, Ge or S can also be doped in the ohmic contact layer alone, or any two or more of the above can also be doped in the ohmic contact layer.

[0098] In each of the above embodiments, the ohmic contact layer includes an N-type III-V semiconductor or a P-type III-V semiconductor.

[0099] The various embodiments described above can be used in conjunction with each other according to the required characteristics of the semiconductor device.

[0100] In addition to being used in HBT, VCSEL, and EEL, the ohmic contact layer can also be used in semiconductor components that require ohmic contact, such as FET, HEMT, PHEMT, BJT, BiFET, BiHEMT, PD, APD, LD, LED, and SC. For example, Figure 6 The gallium arsenide (GaAs) integrated circuit includes HBT and PD; Figure 7 The gallium arsenide (GaAs) integrated circuit includes HBT and LD.

[0101] In some embodiments, an "ohmic contact layer" of (In)GaAsN, (In)GaAsNSb, (In)GaAsNBi, or (In)GaAsNSbBi can form an ohmic contact with most metal materials used for ohmic contact. Figure 8 A metal electrode 80 is further formed on the first ohmic contact layer 71 , and the metal electrode 80 can be made of a P-type metal material or an N-type metal material.

[0102] In some embodiments, when the metal electrode 80 uses a P-type metal material, the P-type metal material contains at least one of the metals Al, Ti, Au, Pt, Be, Zn, W or has at least one compound, or the compound has at least one of the above metals. For example, the P-type metal material is a layered structure or alloy of Ti / Au, Ti / Pt / Au, AuBe, AuZn.

[0103] In some embodiments, when the metal electrode 80 uses an N-type metal material, the N-type metal material includes at least one of metals Al, Ti, Au, Pt, Ge, Ni, and W, or has at least one compound, or the compound has at least one of the above metals. For example, the N-type metal material is a layered structure or alloy of Ti / Au, Ti / Pt / Au, Au / Ge / Ni, Au / Ge, Al / Ge, or Al / Ge / Ni.

[0104] Figure 9a is Figure 2 Schematic diagram of forming multiple epitaxial layers on the first ohmic contact layer (InGaAsN). Figure 9b is Figure 1 Schematic diagram of forming multiple epitaxial layers on the ohmic contact layer (InGaAs). Figure 9a and Figure 9b Both are GaAs material system HBTs grown epitaxially on GaAs substrates. Figure 9a and Figure 9b The difference lies in: the compound material of the ohmic contact layer.

[0105] Figure 9a The first ohmic contact layer is In doped with Te (tellurium) x Ga 1-x As 1-y N y , the doping concentration of Te is about 2×10 19 cm -3 , the total thickness of the first ohmic contact layer is about Figure 9a The first ohmic contact layer includes a composition gradient layer with a thickness of about 500 angstroms and a composition uniform layer with a thickness of about 500 angstroms. The composition gradient layer is closer to the GaAs substrate than the composition uniform layer. The content of indium (In) and nitrogen (N) in the composition gradient layer increases as it is farther away from the substrate. The In content and nitrogen content gradually increase to about 10% and 3.5% respectively. Therefore, the composition uniform layer is about In. 0.1 Ga 0.9 As 0.965 N 0.035 .

[0106] Figure 9b The ohmic contact layer is In doped with Te (tellurium) x Ga 1-x The doping concentration of As and Te is about 2×10 19 cm -3 , the total thickness of the ohmic contact layer is about 1000 angstroms. Figure 9b The ohmic contact layer also includes a composition gradient layer with a thickness of about 500 angstroms and a composition uniform layer with a thickness of about 500 angstroms. The composition gradient layer is closer to the GaAs substrate than the composition uniform layer. The indium (In) content of the composition gradient layer increases as it moves away from the substrate. The In content gradually increases to 60%, so the composition uniform layer is about In. 0.6 Ga 0.4 As.

[0107] Figure 9a and Figure 9b The emitter cap layer is GaAs doped with silicon (Si). In addition, the same multiple epitaxial layers are grown on the ohmic contact layer. Figure 9a and Figure 9b As shown, an InGaP layer L1 with a thickness of 200 angstroms, a GaAs layer L2 with a thickness of 900 angstroms and doped with carbon, a GaAs layer L3 with a thickness of 5000 angstroms and doped with silicon, a GaAs layer L4 with a thickness of 12000 angstroms and intrinsically doped, and a GaAs layer L5 with a thickness of 800 angstroms and doped with carbon are sequentially formed on the first ohmic contact layer 71 or the ohmic contact layer 7'.

[0108] Fig.10a and Fig.10b Photographed with an optical microscope Figure 9a and Figure 9b Image of the surface morphology on top of the epitaxial wafer. Fig.10a As shown, Figure 9a The surface morphology of the top surface S1 of the epitaxial chip is quite flat. Figure 9a The first ohmic contact layer and the multi-layer epitaxial layer have few defects, and the multi-layer epitaxial layer has good epitaxial quality. Fig.10b As shown, Figure 9b The surface morphology of the top surface S2 of the epitaxial chip is rough. Figure 9b The first ohmic contact layer and the multi-layer epitaxial layer have serious dislocations and defects.

[0109] In addition, the Transmission Line Method (TLM) was used to evaluate Figure 9a The contact resistance of the first ohmic contact layer is Figure 9b The contact resistance of the ohmic contact layer, the measurement results are shown in Fig.11 Schematic diagram of the measurement results of TLM resistance. Figure 9a The contact resistance is 3.37×10 -7 Ω-cm 2 , Figure 9b The contact resistance is 3.24×10 -7 Ω-cm 2 It can be seen from this that the nitrogen-containing ohmic contact layer does not increase the contact resistance too much.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the embodiments of the present application. Those skilled in the art should understand that they can easily use the present application as a basis for designing or changing other processes and structures, which are used to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present application; and those skilled in the art can make various changes, substitutions or modifications without departing from the spirit and scope of the present application.

Claims

1. A semiconductor epitaxial wafer, comprising: A substrate having a first lattice constant X1, the substrate being a Ge substrate, a GaAs substrate or an InP substrate; A first epitaxial stacking structure, wherein the epitaxial growth is on the substrate; A first ohmic contact layer, epitaxially grown on the first epitaxial stack structure, has a second lattice constant X2, and the first ohmic contact layer is selected from In x Ga 1-x As y N 1-y 、In x Ga 1-x As y N z Sb 1-y-z 、In x Ga 1-x As y N z Bi 1-y-z and x Ga 1-x As y N z Sb w Bi 1-y-z-w At least one material of the group consisting of When the substrate is the GaAs substrate or the Ge substrate, the x value is 0.05 to 0.3, and y, z, and w are 0.001 to 0.2; when the substrate is the InP substrate, x is 0.5 to 0.75, and y, z, and w are 0.001 to 0.2; as well as a second epitaxial stack structure, wherein the epitaxial layer is grown on the first ohmic contact layer; Wherein, X1-X2 is less than or equal to ±10000 ppm; The first epitaxial stacking structure and the second epitaxial stacking structure respectively constitute a first semiconductor component and a second semiconductor component, and the first semiconductor component and the second semiconductor component are constituted as an integrated circuit through the first ohmic contact layer.

2. The semiconductor epitaxial wafer according to claim 1, wherein: When the substrate is the Ge substrate or the GaAs substrate, the first epitaxial stacking structure and the second epitaxial stacking structure use GaAs series materials.

3. The semiconductor epitaxial wafer according to claim 1, wherein: When the substrate is the InP substrate, the first epitaxial stacking structure and the second epitaxial stacking structure use InP series materials.

4. The semiconductor epitaxial wafer as described in claim 1, wherein the first epitaxial stack structure further comprises a semiconductor layer, the semiconductor layer is in contact with or adjacent to the first ohmic contact layer, and when the substrate is the GaAs substrate, the semiconductor layer is selected from at least one material of the group consisting of GaAs, AlGaAs, InAlAs, InGaP and InGaAs.

5. The semiconductor epitaxial wafer according to claim 1, wherein: The first epitaxial stack structure further includes a semiconductor layer, which is in contact with or adjacent to the first ohmic contact layer. When the substrate is an InP substrate, the semiconductor layer is selected from at least one material of the group consisting of InAlAs, InGaP, InP, InAlGaAs and InGaAsP.

6. The semiconductor epitaxial wafer according to claim 4 or 5, wherein: The invention further comprises a bandgap gradient layer, wherein the bandgap gradient layer is arranged between the semiconductor layer and the first ohmic contact layer.

7. The semiconductor epitaxial wafer according to claim 1, wherein: The invention further comprises a second ohmic contact layer, wherein the second ohmic contact layer is disposed between the substrate and the first epitaxial stack structure.

8. The semiconductor epitaxial wafer according to claim 1, wherein: The first ohmic contact layer is further doped with a doping material, and the doping material is at least one material selected from the group consisting of Te, Se, Si, Sn, Ge, S, C, Zn and Cd.

9. The semiconductor epitaxial wafer according to claim 1, wherein: A metal electrode is further formed, the material of the metal electrode is a P-type metal material or an N-type metal material, wherein the P-type metal material is at least one material selected from the group consisting of Al, Ti, Au, Pt, Be, Zn and W, and the N-type metal material is at least one material selected from the group consisting of Al, Ti, Au, Pt, Ge, Ni and W.

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