Gate contact structure for trench power mosfets with split gate configuration

Abstract

Embodiments of the present disclosure relate to gate contact structures for trench power MOSFETs with split gate configurations. An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body, and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and through the first and second doped regions. An insulating gate region within the trench encloses a multi-oxide region, which can have a void inclusion. The gate region is formed by a first gate salient and a second gate salient on opposite sides of the multi-oxide region. A gate contact pair is provided at each trench. The gate contact pair includes a first gate contact extending into the first gate salient at a location laterally offset from the void, and a second gate contact extending into the second gate salient at a location laterally offset from the void.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 171,163, filed April 6, 2021, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments herein generally relate to metal oxide semiconductor field effect transistor (MOSFET) devices, and in particular to gate contact structures for trench-type power MOSFETs having a split gate configuration comprising a pair of polysilicon gate salients laterally spaced apart by a multi-oxide region and electrically coupled by a polysilicon gate bridge. BACKGROUND

[0004] REFERENCE Figure 1 , Figure 1 A cross-section of a power metal oxide semiconductor field effect transistor (MOSFET) device 10 is shown. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 12 doped with n-type dopants, which provides the drain of the transistor 10. The substrate 12 has a front side 14 and a back side 16. A plurality of trenches 18 extend from the front side 14 into the substrate 12 along a depth. The trenches 18 extend parallel to each other along a length direction (i.e., longitudinally) along a direction perpendicular to the cross-section (i.e., into and out of the illustrated page), and form a strip (this type of transistor device is commonly referred to in the art as a strip FET type transistor).

[0005] A region 24 doped with p-type dopants is buried in the substrate 12 at a depth offset (i.e., below) from the front side 14, and is positioned to extend parallel to the front side 14 on opposite sides of each trench 18. The doped region 24 forms a body (channel) region of the transistor, with the trenches 18 passing completely through the doped body region 24 and into the substrate 12 below the doped body region 24. Surface implant regions 26 heavily doped with n-type dopants are provided at the front side 14 of the substrate 12, and are positioned to extend parallel to the front side 14 on opposite sides of each trench 18, and in contact with the top of the doped body region 24. The doped regions 26 form the source of the transistor, with the trenches 18 passing completely through the doped source regions 26, and as noted above, further extending through the doped body region 24 into the substrate 12 below the doped body region 24.

[0006] The sidewalls and bottom of each trench 18 are lined with an insulating layer 20. For example, the insulating layer 20 can include an oxide layer (in an embodiment, which is thermally grown in each trench 18 from the exposed surface of the substrate 12). Each trench 18 is filled with a polysilicon material 22, which is insulated from the substrate 12 by the insulating layer 20. The polysilicon material 22 forms the gates of the transistors 10 (referred to as a polygate), and the insulating layer 20 is a gate oxide layer.

[0007] A stack 30 of layers is formed over the upper surface of the substrate. The stack 30 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 32 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 34. If desired, the stack 30 can also include additional insulating and / or barrier layers.

[0008] Referring to the left side of Figure 1 , the source metal contacts 40 extend through the layers of the stack 30, positioned between the locations of adjacent trenches 18, to make electrical contact with the doped source regions 26. Each source metal contact 40 extends into the substrate along the depth to pass through the doped source regions 26 and partially into the doped body regions 24 (thereby providing body contacts for the transistors 10 tied to the sources). A source metal layer 42 extends over both the stack 30 and the source metal contacts 40 to provide electrical connections to and between all of the source metal contacts 40. The layers of the stack 30 insulate both the source metal layer 42 and the source metal contacts 40 from the polygate (the polysilicon regions 22).

[0009] Referring now to the right side of Figure 1 , the gate metal contacts 46 extend through the stack layers 30, positioned in alignment with the locations of the trenches 18, to make electrical contact with the polysilicon regions 22 in each trench 18. Although not explicitly illustrated, it is to be understood that the gate metal contacts 46 can extend at least partially along the depth into the polysilicon regions 22. A gate metal layer 48 extends over both the stack 30 and the gate metal contacts 46 to provide electrical connections to and between all of the gate metal contacts 46. The stack layers 30 insulate both the gate metal layer 48 and the gate metal contacts 46 from the source metal contacts and source regions.

[0010] In practice, Figure 1 the cross sections of the left and right sides of are actually longitudinally offset from each other in a direction perpendicular to the cross sections (i.e., into and out of the illustrated page). In this configuration, an insulating separation is provided between the source metal layer 42 and the gate metal layer 48.

[0011] A drain metal layer 44 extends over the backside 16 of the substrate 12 to provide a metal connection to the drains.

[0012] The transistor 10 can alternatively be a pMOS type transistor, in which both the substrate 12 and the doped source region 16 are p-type doped and the body region 14 is n-type doped.

[0013] Reference is now made to Figure 2 , Figure 2 A cross-section of a power metal-oxide-semiconductor field-effect transistor (MOSFET) device 50 is shown. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 52 doped with n-type dopants, which provides the drain of the transistor 50. The substrate 52 has a front side 54 and a back side 56. A plurality of trenches 58 extend from the front side 54 into the substrate 52 along a depth. The trenches 58 extend parallel to each other (i.e., longitudinally) along a direction perpendicular to the cross-section (i.e., into and out of the illustrated page), and form a strip (this type of transistor device is commonly referred to in the art as a strip-FET type transistor).

[0014] Regions 64 doped with p-type dopants are buried in the substrate 52 at a depth offset (i.e., below) from the front side 54, and are positioned on opposite sides of each trench 58 extending parallel to the front side 54. The doped regions 64 form the body (channel) regions of the transistor, with the trenches 58 passing completely through the doped body regions 64 and into the substrate 52 below the doped body regions 64. Regions 66 doped with n-type dopants are provided on the front side 54 of the substrate 52, and are positioned on opposite sides of each trench 58 extending parallel to the front side 54, and in contact with the top of the doped body regions 64. The doped regions 66 form the source of the transistor, with the trenches 58 passing completely through the doped source regions 66, and as noted above, further extending through the doped body regions 64 into the substrate 52 below the doped body regions 64.

[0015] The sidewalls and bottom of each trench 58 are lined with a first (thick) insulating layer 60a. For example, the insulating layer 60a can comprise a thick oxide layer. The trenches 58 are then filled with a first polysilicon material 62a, with the insulating layer 60a insulating the first polysilicon material 62a from the substrate 52. The polysilicon material 62a is a heavily n-type doped polysilicon material (e.g., phosphorous doped, with a doping concentration of 5 x 1019at / cm 20 at / cm 3 During the process for manufacturing the transistor 50, an upper portion of the insulating layer 60a (which will be adjacent to both the doped body regions 64 and the doped regions 66) is removed from the trenches 58 to expose a corresponding upper portion 61 of the polysilicon material 62a (see Figure 3A). This exposed upper portion 61 of the polysilicon material 62a is then converted (e.g., using a thermal oxidation process) to form a polyoxide region 68 that is vertically aligned with the remaining (lower) portion 63 of the polysilicon material 62a in the trench 58 (see Figure 3B ). This remaining lower portion 63 of the polysilicon material 62a forms the field plate electrode of the transistor 50 (also referred to as a poly-source region, as it is typically electrically shorted to the source region 66 - this electrical connection is not explicitly shown in the figures). The sidewalls and bottom of the upper portion of each trench 58 are then lined with a second (thin) insulating layer 60b (see Figure 3C ). For example, the insulating layer 60b can include a thermally grown thin oxide layer. The upper portion of each trench 58 is then filled with a second polysilicon material 62b, with the insulating layer 60b insulating the second polysilicon material 62b from the substrate 52 (including regions 64 and 66). The second polysilicon material 62b forms the gate of the transistor 50 (also referred to as a poly-gate region), and includes a first (e.g., left) gate lobe 621 and a second (e.g., right) gate lobe 622 that extend on opposite sides of the polyoxide region 68. The first and second gate lobes are electrically coupled by a gate bridge portion 623 that extends over the polyoxide region 68. The insulating layer 60b forms a gate oxide layer.

[0016] A stack 70 of layers is formed over the upper surface of the substrate. The stack 70 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 72 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 74. If desired, the stack 70 can also include additional insulating and / or barrier layers.

[0017] Referring to Figure 2 the left side, source metal contacts 80 extend through the layers of the stack 70, positioned between the locations of adjacent trenches 58, to make electrical contact with the doped source regions 66. Each source metal contact 80 extends into the substrate along the depth to pass through the doped source regions 66 and partially into the doped body regions 64 (thereby providing body contacts for the transistors 50 that are tied to the sources). A source metal layer 82 extends over both the stack 70 and the source metal contacts 80 to provide electrical connections to and between all of the source metal contacts 80. The layers of the stack 70 insulate both the source metal layer 82 and the source metal contacts 80 from the poly-gate (second polysilicon region 62b).

[0018] Referring now to Figure 2On the right side of the transistor 50, a gate metal contact 86 extends through the layers of the stack 70, positioned to align with the location of the trench 58 to make electrical contact with the second polysilicon region 62b in each trench 58 (e.g., by contacting at the location of the bridging portion 623). Note that the gate metal contact 86 preferably extends at least partially along the depth into the fill trench, e.g., into at least an upper portion of the bridging portion 623 (and possibly fully through the bridging portion). A gate metal layer 88 extends over both the stack 70 and the gate metal contact 86 to provide electrical connections to and between all of the gate metal contacts 86. The layers of the stack 70 insulate both the gate metal layer 88 and the gate metal contacts 86 from the source metal contacts and source regions. The multi-oxide region 68 insulates the multi-source region 62a from the gate metal contact 86.

[0019] In practice, Figure 2 The cross sections on the left and right side of the transistor 50 are actually longitudinally offset from each other in a direction perpendicular to the cross section (i.e., into and out of the illustrated page). In this configuration, insulating separation is provided between the source metal layer 82 and the gate metal layer 88.

[0020] A drain metal layer 84 extends over the backside 56 of the substrate 52 to provide a metal connection to the drain.

[0021] The transistor 50 can alternatively be a pMOS type transistor, in which both the substrate 52 and the doped source region 56 are p-type doped and the body region 54 is n-type doped.

[0022] Figure 4A A scanning electron micrograph (SEM) cross section image of a single cell of the transistor 50 is shown corresponding to Figure 2 The left side of the transistor 50.

[0023] During formation of the multi-oxide region 68 (see Figure 3B ), there is lateral and vertical material expansion as the polysilicon material 62a is converted to the multi-oxide region 68. This expansion causes tension that can create voids (or seams or cavities) within the multi-oxide material. The presence and location of such voids in the multi-oxide region 68 is unpredictable. Figure 4B A scanning electron micrograph (SEM) cross section image focused on the region where the trench 58 is located is shown to illustrate by example the presence of such voids (see also Figure 3B ). Depending on the width of the trench 58 and the size of the multi-gate formed by the convex corners 621, 622 and the bridge 623, the voids in the multi-oxide region 68 can extend to near the inner surface of the multi-gate (see Figure 3C), and this can have an impact on the formation of the gate contact 86, and as will be discussed below, increases the risk of a short circuit to the source through the multi-source region 62a.

[0024] The process for forming the gate contact 86 uses a mask having a mask opening aligned with the center of the trench 58. The etching performed using this mask creates a gate opening that extends through the stack 70 and at least partially into (if not fully through) the bridge 623 forming the second polysilicon region 62b of the multi-gate. This etching can include multiple discrete etching steps, including a first etch that removes layers of the stack 70 and a second etch that extends to a desired depth into the bridge 623. The size of the mask opening and the corresponding gate opening is generally designed to be about (more preferably less than) one-half the size (width) of the trench 58, and is generally preferred to be aligned with the center of the trench. A barrier layer 92 formed of titanium-titanium nitride (Ti-TiN) material is then conformally deposited into the etched gate opening, which is then filled with a plug made of a conductive material (such as, for example, tungsten) to form the gate contact 86. Figure 4C A scanning electron micrograph (SEM) cross-sectional image focused on the gate contact 86 is shown, and it is illustrated that the gate opening has fully passed through the gate bridge 623 to reach the multi-oxide region 68.

[0025] Control over the depth of the second etch is difficult to ensure, and the possible existence and location of the void in the multi-oxide region 68 is difficult to predict. There is therefore a non-negligible risk that the second etch will fully pass through the bridge 623, with the gate opening partially extending into the multi-oxide region 68 to reach the void. The conformally deposited Ti-TiN barrier layer can not sufficiently cover this location, as the topology presented by the void in combination with the gate opening is difficult, and thus the conductive material deposited in the gate opening for the plug can intrude into the void and can short the multi-gate to the multi-source provided by the field plate (which is electrically connected to the source region, as mentioned above).

[0026] There is a need to address the foregoing issues in power MOSFET devices, and to provide a better solution for electrically contacting a split-gate configuration including a pair of polysilicon gate salient corners laterally spaced apart by a polysilicon region and electrically coupled by a polysilicon gate bridge. SUMMARY

[0027] In an embodiment, an integrated circuit transistor device includes: a semiconductor substrate providing a drain; a first doped region buried in the semiconductor substrate providing a body; a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent to the first doped region; a trench extending into the semiconductor substrate and through the first doped region and the second doped region; a poly-oxide region within the trench; a poly-gate region within the trench, the poly-gate region including: a first gate salient on a first side of the poly-oxide region and a second gate salient on a second side of the poly-oxide region opposite the first side; an insulating layer extending over the first doped region and the trench; and a gate contact pair for the trench. The gate contact pair includes: a first gate contact extending through the insulating layer and into the first gate salient; and a second gate contact extending through the insulating layer and into the second gate salient.

[0028] In an embodiment, an integrated circuit transistor device includes: a semiconductor substrate providing a drain; a first doped region buried in the semiconductor substrate providing a body; a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent to the first doped region; a trench extending into the semiconductor substrate and through the first doped region and the second doped region; an insulating poly-source region within the trench; a poly-oxide region within the trench and aligned with the insulating poly-source region, wherein the poly-oxide region includes a void; a first insulating gate salient of a first side of the poly-oxide region; a second insulating gate salient of a second side of the poly-oxide region opposite the first side; a first gate contact extending into the first gate salient, the first gate contact laterally offset from a longitudinal center of the trench such that a depth of the first gate contact does not reach the void; and a second gate contact extending into the second gate salient, the second gate contact laterally offset from the longitudinal center of the trench such that a depth of the second gate contact does not reach the void. BRIEF DESCRIPTION OF DRAWINGS

[0029] For a better understanding of embodiments, reference will now be made, purely by way of example, to the accompanying drawings in which:

[0030] Figure 1 is a cross-section of a power metal-oxide-semiconductor field-effect transistor (MOSFET) device;

[0031] Figure 2 is a cross-section of a power MOSFET device;

[0032] Figures 3A to 3C shows Figure 2 process steps in the manufacture of a power MOSFET device of

[0033] Figures 4A to 4C is Figure 2a scanning electron micrograph image of a cross-section of a power MOSFET device of

[0034] Figure 5 is a cross-section of a power MOSFET device;

[0035] Figure 6A and Figure 6B respectively illustrate Figure 2 and Figure 5 gate contact layout configurations of power MOSFET devices of

[0036] Figure 7 is a cross-section of a power MOSFET device;

[0037] Figures 8A to 8B is a scanning electron micrograph image of a cross-section of a power MOSFET device of Figure 7

[0038] Figure 9A and Figure 9B respectively illustrate Figure 5 and Figure 7 gate contact layout configurations of power MOSFET devices of DETAILED DESCRIPTION

[0039] For the discussion herein, it is noted that the term "longitudinal" refers to a first direction that extends, for example, along a length of a trench, and the term "lateral" refers to a second direction that extends, for example, along a width of a trench. The longitudinal and lateral directions are perpendicular to each other and extend parallel to an upper surface of a semiconductor substrate.

[0040] Reference is now made to Figure 5 , Figure 5 shows a lateral cross-section of a power metal-oxide-semiconductor field-effect transistor (MOSFET) device 110. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 112 doped with n-type dopants, which provides a drain of the transistor 110. The substrate 112 has a front side 114 and a back side 116. A plurality of trenches 118 extend from the front side 114 into the substrate 112 along a depth. The trenches 118 extend parallel to each other along a direction perpendicular to the cross-section (i.e., into and out of the illustrated page) for a desired length and form a strip (this type of transistor device is often referred to in the art as a strip-FET type transistor).

[0041] ​The region 124 doped with p-type dopants is buried in the substrate 112 at a depth offset (i.e., below) the front surface 114 and is positioned to extend laterally parallel to the front surface 114 on opposite sides of each trench 118. The doped region 124 forms the body (channel) region of the transistor, with the trench 118 extending completely through the doped body region 124 and into the substrate 112 below the doped body region 124. A surface implant region 126 doped with n-type dopants is provided at the front surface 114 of the substrate 112 and is positioned to extend parallel to the front surface 114 on opposite sides of each trench 118 and in contact with the top of the doped body region 124. The doped region 126 forms the source of the transistor, with the trench 118 extending completely through the doped source region 126 and, as noted above, further through the doped body region 124 to reach into the substrate 112 below the doped body region 124.

[0042] The sidewalls and bottom of each trench 118 are lined with a first insulating layer 120a. For example, the insulating layer 120a can include a thick oxide layer. The trench 118 is then filled with a first polysilicon material 122a, with the insulating layer 120a insulating the first polysilicon material 122a from the substrate 112. The first polysilicon material 122a is a heavily n-type doped polysilicon material (e.g., phosphorous doped, with a doping concentration of 5 x 1019atoms / cm3). 20 at / cm 3). During the process of fabricating the transistor 110, the upper portion of the insulating layer 120a, which will be adjacent to both the doped body region 124 and the doped region 126, is removed from the trench 118 to expose the corresponding upper portion of the first polysilicon material 122a. This exposed upper portion of the first polysilicon material 122a is then converted (e.g., using a thermal oxidation process) to form a polyoxide region 128 that is vertically aligned in the trench 118 with the remaining (lower) portion of the first polysilicon material 122a. This remaining lower portion of the first polysilicon material 122a forms the field plate electrode of the transistor 110 (also referred to as a poly-source region, as it is typically electrically shorted to the source region 126 - this electrical connection is not explicitly shown in the figures). The upper portion of the sidewalls and the bottom of each trench 118 is then lined with a second insulating layer 120b. For example, the insulating layer 120b can comprise a thermally grown oxide layer. The upper portion of each trench 118 is then filled with a second polysilicon material 122b, with the insulating layer 120b insulating the second polysilicon material 122b from the substrate 112, including the regions 124 and 126. The second polysilicon material 122b forms the gate (also referred to as a poly-gate region) of the transistor 110, and includes a first (e.g., left) gate salient 621 and a second (e.g., right) gate salient 622 that extend longitudinally in the trench on opposite sides of the polyoxide region 128. The first and second gate salients are connected by a gate bridge portion 623 that extends laterally over the polyoxide region 128. The insulating layer 120b forms a gate oxide layer.

[0043] A layer stack 130 is formed over the upper surface of the substrate. The stack 130 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 132 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 134. If desired, the stack 130 can also include additional insulating and / or barrier layers.

[0044] Referring to Figure 5 The source metal contacts 140 extend through the layers of the stack 130, positioned between the locations of adjacent trenches 118 to make electrical contact with the doped source regions 126. Each source metal contact 140 extends into the substrate along the depth to pass through the doped source regions 136 and partially into the doped body regions 134 (thereby providing body contacts for the transistors 110 that are tied to the sources). A source metal layer 142 extends over both the stack 130 and the source metal contacts 140 to provide electrical connections to and between all of the source metal contacts 140. The layers of the stack 130 insulate both the source metal layer 142 and the source metal contacts 140 from the poly-gate (second polysilicon region 122b).

[0045] Referring now to Figure 5on the right side, each multi-gate's gate metal contact is formed by a pair of contacts 861 and 862, where each contact 861, 862 extends through the layers of the stack 130, positioned vertically aligned with the location of the corresponding cusp 621, 622 (respectively) of the multi-gate to make electrical contact with the respective cusp of the second polysilicon region 122b in each trench 118. In the preferred embodiment, each gate metal contact 861, 862 extends at least partially along the depth into the upper portion of the corresponding cusp 621, 622 on either side of the bridge 623. The gate metal layer 148 extends over both the stack 130 and the gate metal contacts 861, 862 to provide electrical connections to and between all of the gate metal contacts 861, 862. The layers of the stack 130 insulate the gate metal layer 148 and the gate metal contacts 861, 862 from the source metal contacts and source regions. Note that a portion of the stack is used to laterally insulate the contact 861 from the contact 862 at the level of the layers within the stack.

[0046] In practice, Figure 5 The cross-sections on the left and right side are actually longitudinally offset from each other in the direction perpendicular to the cross-section (i.e., into and out of the illustrated page). In this configuration, insulating separation is provided between the source metal layer 142 and the gate metal layer 148.

[0047] The drain metal layer 144 extends over the backside 116 of the substrate 112 to provide a metal connection to the drain.

[0048] The transistor 110 can alternatively be a pMOS type transistor, where both the substrate 112 and the doped source region 126 are p-type doped and the body region 124 is n-type doped.

[0049] Figure 6A and Figure 6B is a plan view (i.e., looking down at the front surface of the substrate) for comparing the layouts of the transistors 50 and 110, with particular focus on the relative locations of the contacts 86 and the pairs of contacts 861 and 862. The dashed lines indicate the centerlines of each longitudinally extending trench, and the dash-dot lines indicate the approximate locations of the longitudinal centers of each cusp of the multi-gate. Figure 6A corresponds generally to the embodiment shown on the Figure 2 corresponds generally to the embodiment shown on the Figure 6B corresponds generally to the embodiment shown on the Figure 5 corresponds generally to the embodiment shown on the right side. While only a pair of contacts 861 and 862 per trench is shown in Figure 6B , it is understood that this is merely an example, and more than one pair of contacts per trench can be used if desired.

[0050] The use of a pair of side-by-side arranged contacts 861 and 862 in Figure 5The illustrated gate contact structure addresses concerns arising from the potential inclusion of voids in the multi-oxide region 148. The combined size of the pair of contacts 861 and 862 is preferably substantially equal to... Figure 2 The size of the gate contact 86 shown will therefore provide essentially the same performance in terms of gate resistance. Separating each gate contact into two parts (contacts 861 and 862) and vertically aligning each part with the corresponding convex corners 621, 622 of the multi-gate avoids multi-gate contact with the central portion of the trench (i.e., at the location of the gate bridge region), thereby minimizing the risk of the etching used to form the contact opening reaching the void location.

[0051] In Figure 5 In the embodiments, each contact 861, 862 may have a length dimension (in the longitudinal direction) between 0.1 μm and 10 μm and a width dimension (perpendicular to the length dimension in the transverse direction) between 0.1 μm and 1 μm.

[0052] It is important to note that, in Figure 5 In the illustrated embodiment, with a pair of contacts 861, 862 arranged laterally side-by-side, the cross-section at a given location extends longitudinally through the two contacts 861, 862 along the length of the trench. Manufacturing a device with this embodiment requires the gate mask to include a very thin resist portion aligned with the spacing between adjacent contacts at the given location. This very thin resist portion may peel off during manufacturing and adversely affect the accuracy of the etching operation forming the gate contact openings. For example, distorted openings may occur for each gate contact, or merged openings may appear, merging two separate openings of a side-by-side pair of contacts into one large opening. The solution to this concern is to design the gate mask such that the respective mask openings for generating contacts 861, 862 are longitudinally offset from each other in a direction perpendicular to the cross-section (i.e., in and out of the illustrated page).

[0053] The transistor 110' structure produced by this arrangement of mask openings is as follows: Figure 7 As shown. Figure 7 The same reference numerals in the figures refer to those that are the same as those in the figures below. Figure 5 The same or similar parts. Figure 7 The left side corresponds to Figure 5 On the left side. Figure 7 The middle and right portions of the diagram illustrate gate contacts 861 and 862 with a given trench longitudinal offset, caused by the corresponding longitudinal offset of the mask opening. Specifically, Figure 7 The middle portion shows a cross-section at the location where the mask opening for forming the first gate contact 861 has been utilized to make electrical contact with the corresponding first (left) convex angle 621 of the multigate.Figure 7 The right portion of FIG. 8B shows a cross-section at a location where a mask opening for forming the second gate contact 862 has been utilized in order to make electrical contact with the corresponding second (right) salient corner 622 of the multi-gate. Although there is a longitudinal offset of the individual gate openings, note that each gate contact of the multi-gate within the trench is still formed by a pair of contacts 861 and 862.

[0054] In this Figure 7 embodiment, each contact 861, 862 can have a length dimension (in the longitudinal direction) between 0.1 pm and 10 pm and a width dimension (in the transverse direction perpendicular to the length dimension) between 0.1 pm and 1 pm. Note that due to the longitudinal offset of the contacts 861, 862 in FIG. 8B, each individual contact can be fabricated to have a wider width than the corresponding contact of the embodiment of FIG. 8A. Figure 7 In this Figure 5 embodiment, each contact 861, 862 can have a length dimension (in the longitudinal direction) between 0.1 pm and 10 pm and a width dimension (in the transverse direction perpendicular to the length dimension) between 0.1 pm and 1 pm. Note that due to the longitudinal offset of the contacts 861, 862 in FIG. 8B, each individual contact can be fabricated to have a wider width than the corresponding contact of the embodiment of FIG. 8A.

[0055] Figure 8A shows a scanning electron micrograph (SEM) cross-sectional image of a single cell of the transistor 110', corresponding to the middle portion of FIG. 8B, and focused on the gate contact 861 for the salient corner 621 of the multi-gate. Figure 7

[0056] Figure 8B shows a scanning electron micrograph (SEM) cross-sectional image of a single cell of the transistor 110', corresponding to the right portion of FIG. 8B, and focused on the gate contact 862 for the salient corner 622 of the multi-gate. Figure 7

[0057] Figure 9A and Figure 9B is a plan view (i.e., looking down at the front surface of the substrate) for comparing the layouts of the transistors 110 and 110', with a specific focus on the relative positions of the contact pairs 861 and 862. The dashed lines indicate the centerlines of each longitudinally extending trench, and the dash-dot lines indicate the approximate locations of the centers of each salient corner of the multi-gate. Note that the longitudinal center of each contact 861, 862 is located between the longitudinal center of the corresponding gate salient corner and the longitudinal center of the trench. This ensures that the placement of the contacts does not risk bridging across the gate oxide and shorting the multi-gate to the doped source region. Figure 9A corresponds generally to the embodiment shown in the left portion of FIG. 8B, while Figure 7 corresponds generally to the embodiment shown in the right portion of FIG. 8B. Although only a pair of contacts 861 and 862 per trench is shown in FIG. 8B, it is to be understood that the same principles apply to the other portions of the multi-gate. Figure 9B corresponds generally to the embodiment shown in the middle portion of FIG. 8B, while Figure 7 corresponds generally to the embodiment shown in the right portion of FIG. 8B. Although only a pair of contacts 861 and 862 per trench is shown in FIG. 8B, it is to be understood that the same principles apply to the other portions of the multi-gate. Figure 9A and 9B ​​As shown in FIG. 8, it is to be understood that this is merely an example, and more than one pair of contacts can be used for each trench, if desired. By way of example, a first pair of contacts 861 and 862 can be used for a first trench 850, and a second pair of contacts 871 and 872 can be used for a second trench 860. The first pair of contacts 861 and 862 and the second pair of contacts 871 and 872 can be longitudinally offset from each other, as shown in FIG. 8. It is to be understood that the longitudinal offset of the pair of contacts 861 and 862 for a given trench is such that no cross-section of the trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact. This is achieved by providing a sufficient longitudinal offset distance D between the end of the first gate contact and the adjacent end of the second gate contact in the longitudinal direction of the trench. Figure 9B It is to be noted that the longitudinal offset of the pair of contacts 861 and 862 for a given trench is such that no cross-section of the trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact. This is achieved by providing a sufficient longitudinal offset distance D between the end of the first gate contact and the adjacent end of the second gate contact in the longitudinal direction of the trench.

[0058] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed application, from an study of the drawings, the disclosure, and the appended claims.

Claims

1. An integrated circuit transistor device, comprising: a semiconductor substrate providing a drain; a first doped region buried in the semiconductor substrate providing a body; a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent to the first doped region; a trench extending into the semiconductor substrate and through the first doped region and the second doped region; a polysilicon oxide region within the trench; a multi-gate region within the trench, the multi-gate region comprising a first gate lobe on a first side of the polysilicon oxide region and a second gate lobe on a second side of the polysilicon oxide region opposite the first side; an insulating layer extending over the first doped region and trench; and a gate contact pair for the trench, the gate contact pair comprising: a first gate contact extending through the insulating layer and into the first gate lobe, wherein the first gate contact has a first length and a first width, the first length extending parallel to a longitudinal direction of the trench, and the first length is greater than the first width perpendicular to the first length; and a second gate contact extending through the insulating layer and into the second gate lobe, wherein the second gate contact has a second length and a second width, the second length extending parallel to the longitudinal direction of the trench, and the second length is greater than the second width perpendicular to the second length.

2. The integrated circuit transistor device of claim 1, wherein the first gate contact and the second gate contact are in a lateral side-by-side arrangement.

3. The integrated circuit transistor device of claim 1, wherein the first gate contact and the second gate contact are offset from each other in a longitudinal direction of the trench.

4. The integrated circuit transistor device of claim 3, wherein no cross-section of the trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact.

5. The integrated circuit transistor device of claim 1, wherein the multi-gate region further comprises a bridging region extending over the polysilicon oxide region and electrically coupling the first gate lobe to the second gate lobe.

6. The integrated circuit transistor device of claim 5, wherein a portion of the bridging region extends laterally between the first gate contact and the second gate contact.

7. The integrated circuit transistor device of claim 1, wherein the polysilicon oxide region comprises a void, and wherein each of the first gate contact and the second gate contact is offset relative to the void in a lateral direction of the trench.

8. The integrated circuit transistor device of claim 1, wherein the polysilicon oxide region is aligned with a center of the trench, and wherein a center of each of the first gate contact and the second gate contact is between a center of the corresponding first gate lobe and second gate lobe and the center of the trench.

9. The integrated circuit transistor device of claim 1, further comprising: a metal layer extending above the insulating layer and electrically connecting the first gate contact and the second gate contact.

10. The integrated circuit transistor device of claim 1, further comprising: a gate insulator layer along a wall of the trench and positioned between each of the first and second gate cusp and the semiconductor substrate.

11. The integrated circuit transistor device of claim 1, further comprising: a multi-source region within the trench, wherein the multi-source region is longitudinally aligned with the polysilicon oxide region.

12. The integrated circuit transistor device of claim 11, wherein the polysilicon oxide region is an oxidized portion of the multi-source region.

13. The integrated circuit transistor device of claim 1, wherein each of the first and second gate contacts comprises a titanium-titanium nitride barrier layer and a tungsten plug.

14. An integrated circuit transistor device, comprising: a semiconductor substrate providing a drain; a first doped region buried in the semiconductor substrate providing a body; a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent to the first doped region; a trench extending into the semiconductor substrate and through the first and second doped regions; an insulating multi-source region within the trench and formed of a polysilicon material; a polysilicon oxide region within the trench and aligned with the insulating multi-source region, wherein the polysilicon oxide region comprises a void, and the polysilicon oxide region is formed by converting the polysilicon material; a first insulating gate cusp on a first side of the polysilicon oxide region; a second insulating gate cusp on a second side of the polysilicon oxide region opposite the first side; a first gate contact extending into the first insulating gate cusp, the first gate contact being laterally offset relative to a longitudinal center of the trench such that a depth of the first gate contact does not reach the void, wherein the first gate contact has a first length extending parallel to a longitudinal direction of the trench and a first width perpendicular to the first length, the first length being greater than the first width; and a second gate contact extending into the second insulating gate cusp, the second gate contact being laterally offset relative to the longitudinal center of the trench such that a depth of the second gate contact does not reach the void, wherein the second gate contact has a second length extending parallel to the longitudinal direction of the trench and a second width perpendicular to the second length, the second length being greater than the second width.

15. The integrated circuit transistor device of claim 14, further comprising: an insulating layer extending above the first doped region and trench, wherein the first and second gate contacts extend through the insulating layer and are laterally insulated from each other at a level of the insulating layer by a portion of the insulating layer.

16. The integrated circuit transistor device of claim 14, wherein the first and second gate contacts are in a lateral side-by-side arrangement.

17. The integrated circuit transistor device of claim 14, wherein the first gate contact and the second gate contact are offset from one another in a longitudinal direction of the trench.

18. The integrated circuit transistor device of claim 15, further comprising: a bridging region extending over the polysilicon oxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe.

19. The integrated circuit transistor device of claim 18, wherein the bridging region extends laterally between the first gate contact and the second gate contact.

20. The integrated circuit transistor device of claim 14, wherein the polysilicon oxide region is an oxidized portion of the insulated multi-source region.

21. An integrated circuit transistor device, comprising: a semiconductor substrate providing a drain; a first doped region buried in the semiconductor substrate providing a body; a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent to the first doped region; a trench extending into the semiconductor substrate and through the first doped region and the second doped region; a polysilicon oxide region within the trench, wherein the polysilicon oxide region is formed by converting a polysilicon material; a multi-gate region within the trench, the multi-gate region including a first insulated gate lobe on a first side of the polysilicon oxide region, a second insulated gate lobe on a second side of the polysilicon oxide region opposite the first side, and a bridging region extending over the polysilicon oxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe; an insulating layer extending over the first doped region and the trench; and a gate contact extending through the insulating layer and into the first insulated gate lobe of the trench, and wherein the bridging region extends laterally away from the gate contact, wherein the gate contact has a length and a width, the length extending parallel to a longitudinal direction of the trench, and the length is greater than the width perpendicular to the length.

22. The integrated circuit transistor device of claim 21, wherein the polysilicon oxide region includes a void, and wherein the gate contact is offset from the void in a lateral direction of the trench.

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