A MOSFET structure and a manufacturing method thereof

Abstract

The present invention provides a MOSFET structure and a manufacturing method thereof. The structure includes a substrate, a first active region and a second active region, at least two third active regions, a gate structure, a sidewall structure, a source region and a drain region, a source contact portion and a drain contact portion. Among them, the first and second active regions are arranged at intervals along the X direction, at least two third active regions are arranged at intervals along the Y direction, and both ends of the third active region along the X direction are respectively connected to the first and second active regions. The sidewall structure includes a first sidewall and a second sidewall located at both ends of the gate structure along the X direction, and includes a third sidewall located at one end of the gate structure along the Y direction. The source-drain contact portions are all located on the side of the third sidewall away from the gate structure along the Y direction and are not in the same section as the channel, thereby reducing the contact-polysilicon pitch and being beneficial to the improvement of the transistor density. The manufacturing method of the MOSFET structure of the present invention uses a sidewall patterning process to obtain the above sidewall structure, and the process is simple.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and relates to a MOSFET structure and a manufacturing method thereof. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor, abbreviated as a metal-oxide-semiconductor field-effect transistor (MOSFET), is a field-effect transistor that can be widely used in analog circuits and digital circuits. MOSFETs can be divided into two types, "N-type" and "P-type", according to the polarity of their "channels" (working carriers), and are usually also called NMOSFETs and PMOSFETs. Other abbreviations include NMOS, PMOS, etc.

[0003] The manufacturing method of the existing MOSFET structure uses a self-aligned spacer process. The contact of the active region (AA CT) and the channel are located in the same longitudinal section. A spacer with a certain thickness (Lsp≈0.2 - 0.3*Lg, where Lsp is the spacer thickness and Lg is the gate width) must be used to isolate the contact from the gate polysilicon. The contact-polysilicon pitch (Contact Poly Pitch, abbreviated as CPP) is large, reducing the transistor density. Among them, CPP = Lg + 2Lsp + Lcnt, and Lcnt is the width of the contact.

[0004] Therefore, how to improve the MOSFET structure and its manufacturing process to increase the transistor density has become an important technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a MOSFET structure and a manufacturing method thereof, which are used to solve the problem that the MOSFET transistors in the prior art occupy a large area.

[0006] To achieve the above purpose and other related purposes, the present invention provides a MOSFET structure, including:

[0007] A substrate;

[0008] A first active region and a second active region, located in the substrate and spaced apart along the X direction, the X direction being parallel to the plane of the substrate;

[0009] At least two third active regions, located in the substrate and spaced apart along the Y direction, the third active regions being connected to the first active region and the second active region at both ends along the X direction, the Y direction being parallel to the plane of the substrate, and the Y direction being perpendicular to the X direction;

[0010] A gate structure is located on the third active region and extends in the Y direction. A first end of the gate structure in the Y direction protrudes beyond a first end of the first active region and the second active region in the Y direction. A second end of the gate structure in the Y direction is spaced apart from a second end of the first active region and the second active region in the Y direction by a preset distance.

[0011] A sidewall structure includes a first sidewall located at a first end of the gate structure in the X direction, a second sidewall located at a second end of the gate structure in the X direction, and a third sidewall located at a second end of the gate structure in the Y direction.

[0012] A source region and a drain region, the source region is located in the first active region, and the drain region is located in the second active region.

[0013] A source contact portion and a drain contact portion, the source contact portion is located above the source region and on a side of the third sidewall away from the gate structure in the Y direction, and the drain contact portion is located above the drain region and on a side of the third sidewall away from the gate structure in the Y direction.

[0014] Optionally, the third sidewall protrudes in the X direction beyond a side of the first sidewall away from the gate structure and protrudes in the X direction beyond a side of the second sidewall away from the gate structure.

[0015] Optionally, a distance between the source contact portion and the gate structure in the X direction is less than a thickness of the first sidewall in the X direction, and a distance between the drain contact portion and the gate structure in the X direction is less than a thickness of the second sidewall in the X direction.

[0016] Optionally, a distance between the source contact portion and the gate structure in the X direction is less than or equal to 0, and a distance between the drain contact portion and the gate structure in the X direction is less than or equal to 0.

[0017] Optionally, the MOSFET structure further includes a gate structure lead-out portion and a gate contact portion. The gate structure lead-out portion is located on the substrate and connected to a first end of the gate structure in the Y direction, and a vertical projection of the gate contact portion on the substrate is located in a region where the gate structure lead-out portion is located.

[0018] Optionally, the MOSFET structure further includes a gate contact portion, and a vertical projection of the gate contact portion on the substrate is located in a region where the gate structure is located.

[0019] The present invention also provides a manufacturing method of a MOSFET structure, including the following steps:

[0020] Provide a substrate, and form an isolation structure in the substrate to define a first active region, a second active region and at least two third active regions in the substrate. The first active region and the second active region are spaced along the X direction, at least two of the third active regions are spaced along the Y direction, and two ends of the third active region along the X direction are respectively connected to the first active region and the second active region. Both the X direction and the Y direction are parallel to the plane where the substrate is located, and the Y direction is perpendicular to the X direction;

[0021] Form a gate structure on the substrate. The gate structure is located on the third active region and extends in the Y direction. A first end of the gate structure along the Y direction protrudes from a first end of the first active region and the second active region along the Y direction, and a second end of the gate structure along the Y direction is spaced from a second end of the first active region and the second active region along the Y direction by a preset distance;

[0022] Form a sidewall dielectric layer on the substrate, and pattern the sidewall dielectric layer to obtain a sidewall structure. The sidewall structure includes a first sidewall located at a first end of the gate structure along the X direction, a second sidewall located at a second end of the gate structure along the X direction, and a third sidewall located at a second end of the gate structure along the Y direction;

[0023] Form a source region and a drain region. The source region is located in the first active region, and the drain region is located in the second active region;

[0024] Form an interlayer dielectric layer on the substrate, and form a source contact portion and a drain contact portion in the interlayer dielectric layer. The source contact portion is located above the source region and on a side of the third sidewall away from the gate structure along the Y direction, and the drain contact portion is located above the drain region and on a side of the third sidewall away from the gate structure along the Y direction.

[0025] Optionally, after forming the source region and the drain region and before forming the interlayer dielectric layer, the following steps are further included: form a silicide layer on the top surface of the source region, the top surface of the drain region and the top surface of the gate structure.

[0026] Optionally, when forming the gate structure, a gate structure lead-out portion is also formed synchronously. The gate structure lead-out portion is located on the substrate and is connected to a first end of the gate structure along the Y direction. After forming the interlayer dielectric layer, the step of forming a gate contact portion in the interlayer dielectric layer is further included. A vertical projection of the gate contact portion on the substrate is located in the region where the gate structure lead-out portion is located.

[0027] Optionally, after forming the interlayer dielectric layer, a step of forming a gate contact in the interlayer dielectric layer is further included, and a vertical projection of the gate contact on the substrate is located in the region where the gate structure is located.

[0028] As described above, in the MOSFET structure of the present invention, the sidewall structure includes a first sidewall and a second sidewall located at two ends of the gate structure along the X direction, and a third sidewall located at one end of the gate structure along the Y direction. The source contact and the drain contact are both located on the side of the third sidewall away from the gate structure along the Y direction and are not in the same section as the channel, thereby reducing the contact-polysilicon pitch and being beneficial to improving the transistor density. The manufacturing method of the MOSFET structure of the present invention uses a sidewall patterning process to obtain the above sidewall structure, and the process is simple. Description of the Drawings

[0029] Figure 1 Shown is a schematic cross-sectional structure diagram of a MOSFET structure.

[0030] Figure 2 Shown as Figure 1 a planar layout diagram of the NMOS transistor in the shown structure.

[0031] Figure 3 Shown is a planar layout diagram of the MOSFET structure of the present invention in Embodiment 1.

[0032] Figure 4 Shown as Figure 3 a cross-sectional view of the shown structure along the X1 direction.

[0033] Figure 5 Shown as Figure 3 a cross-sectional view of the shown structure along the X2 direction.

[0034] Figure 6 Shown as Figure 3 a cross-sectional view of the shown structure along the X3 direction.

[0035] Figure 7 Shown are the planar layout and dimensions of a conventional device.

[0036] Figure 8 Shown are the planar layout and dimensions of the MOSFET structure of the present invention in Embodiment 1.

[0037] Figure 9 Shown are the planar layout and dimensions of the MOSFET structure of the present invention in Embodiment 2.

[0038] Figure 10It shows a schematic cross-sectional structure diagram along the X1 direction after forming a gate structure on the substrate in the manufacturing method of the MOSFET structure of the present invention.

[0039] Figure 11 It shows a schematic cross-sectional structure diagram along the X1 direction after depositing and planarizing a sidewall dielectric layer on the substrate 201 in the manufacturing method of the MOSFET structure of the present invention.

[0040] Figure 12 It shows a schematic cross-sectional structure diagram along the X1 direction after patterning the sidewall dielectric layer in the manufacturing method of the MOSFET structure of the present invention.

[0041] Figure 13 It shows a schematic cross-sectional structure diagram along the X2 direction after patterning the sidewall dielectric layer in the manufacturing method of the MOSFET structure of the present invention.

[0042] Figure 14 It shows a schematic cross-sectional structure diagram along the X1 direction after forming source and drain regions in the manufacturing method of the MOSFET structure of the present invention.

[0043] Figure 15 It shows a schematic diagram of forming a silicide layer on the top surfaces of the source region, the drain region, and the gate structure in the manufacturing method of the MOSFET structure of the present invention.

[0044] Figure 16 It shows a schematic cross-sectional structure diagram along the X1 direction after forming an interlayer dielectric layer on the substrate and planarizing the interlayer dielectric layer in the manufacturing method of the MOSFET structure of the present invention.

[0045] Element number description

[0046] 101 NMOS transistor

[0047] 102 PMOS transistor

[0048] 103 Active region contact

[0049] 104 Active region

[0050] 105 Polysilicon region

[0051] 106 Contact region

[0052] 107 Source / drain implantation region

[0053] 201 Substrate

[0054] 202 First active region

[0055] 203 Second active region

[0056] 204 Third active region

[0057] 205 Source region

[0058] 206 Drain region

[0059] 207 Source contact

[0060] 208 Drain contact

[0061] 209 First sidewall

[0062] 210 Second sidewall

[0063] 211 Third sidewall

[0064] 212 Well region

[0065] 213 Shallow trench isolation structure

[0066] 214 Source / drain implantation region

[0067] 215 Gate dielectric layer

[0068] 216 Polysilicon layer

[0069] 217 Gate structure lead-out portion

[0070] 218 Gate contact

[0071] 219 Sidewall dielectric layer

[0072] 220 Silicide layer

[0073] 221 Interlayer dielectric layer Detailed implementation manners

[0074] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please refer to Figures 1 to 16 . It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0076] Please refer to Figure 1, shown as a schematic cross-sectional structure of a MOSFET structure, including an NMOS transistor 101, a PMOS transistor 102, and an active region contact 103. Please refer to Figure 2 , shown as Figure 1 The layout plan of the NMOS transistor 101 in the shown structure, including an active region 104, a polysilicon region 105, a contact region 106, and a source / drain implantation region 107. Among them, Figure 1 and Figure 2 The shown MOSFET structure uses a self-aligned sidewall process. The active region contact 103 and the channel are located in the same longitudinal section. There must be a sidewall with a certain thickness to achieve isolation between the contact and the polysilicon. Among them, Figure 1 shows the contact-polysilicon pitch CPP, the sidewall thickness Lsp, the gate width Lg, and the width Lcnt of the contact. CPP = Lg + 2Lsp + Lcnt. It can be seen that Figure 1 and Figure 2 The CPP of the shown MOSFET structure is relatively large, which is not conducive to improving the transistor density. The present invention improves the MOSFET structure and its manufacturing process to increase the transistor density. The improvement scheme will be described below through specific embodiments.

[0077] Embodiment 1

[0078] In this embodiment, a MOSFET structure is provided. Please refer to Figures 3 to 6 , among which, Figure 3 shows the layout plan of this MOSFET structure, Figure 4 shows as Figure 3 The cross-sectional view of the shown structure along the X1 direction, Figure 5 shows as Figure 3 The cross-sectional view of the shown structure along the X2 direction, Figure 6 shows as Figure 3 The cross-sectional view of the shown structure along the X3 direction.

[0079] Specifically, as Figures 3 to 6As shown, the MOSFET structure includes a substrate 201, a first active region 202 and a second active region 203, at least two third active regions 204, a gate structure, a sidewall structure, a source region 205 and a drain region 206, a source contact 207 and a drain contact 208. Among them, the first active region 202 and the second active region 203 are located in the substrate 201 and are spaced apart along the X direction, the X direction is parallel to the plane where the substrate 201 is located, the at least two third active regions 204 are located in the substrate 201 and are spaced apart along the Y direction, and both ends of the third active region 204 along the X direction are respectively connected to the first active region 202 and the second active region 203. The Y direction is parallel to the plane where the substrate 201 is located, and the Y direction is perpendicular to the X direction; the gate structure is located on the third active region 204 and extends in the Y direction. The first end of the gate structure along the Y direction protrudes from the first ends of the first active region 202 and the second active region 202 along the Y direction, and the second end of the gate structure along the Y direction is spaced apart from the second ends of the first active region 202 and the second active region 202 by a preset distance; the sidewall structure includes a first sidewall 209 located at the first end of the gate structure along the X direction, a second sidewall 210 located at the second end of the gate structure along the X direction, and a third sidewall 211 located at the second end of the gate structure along the Y direction; the source region 205 is located in the first active region 202, and the drain region 206 is located in the second active region 203; the source contact 207 is located above the source region 205 and on the side of the third sidewall 211 away from the gate structure along the Y direction, and the source contact 207 is located above the drain region 206 and on the side of the third sidewall 211 away from the gate structure along the Y direction.

[0080] As an example, a well region 212 is provided in the substrate 201, and the first active region 202, the second active region 203 and the third active region 204 are defined in the well region 212 by a shallow trench isolation structure 213. Among them, for an NMOS transistor, the well region 212 is a P well.

[0081] As an example, Figure 4 A source-drain implantation region 214 is also shown. In the source-drain implantation region 214, the portion of the first active region 202 not blocked by the gate structure and the sidewall structure constitutes the source region 205, and the portion of the second active region 203 not blocked by the gate structure and the sidewall structure constitutes the drain region 206.

[0082] As an example, the number of the third active regions 204 between the first active region 202 and the second active region 203 can be adjusted as needed, for example, it can be 2 to 10, preferably 5 to 6. Each of the third active regions 204 serves as the channel region of a transistor. Multiple transistors share a source region and a drain region, and the multiple transistors are in a parallel relationship.

[0083] As an example, the source contact portion 207 and the drain contact portion 208 are located in the interlayer dielectric layer 221, and the interlayer dielectric layer 221 is located on the substrate 201 and covers the gate structure and the sidewall structure.

[0084] As an example, the gate structure includes a gate dielectric layer 215 and a polysilicon layer 216 which are sequentially arranged from bottom to top. Silicide layers 217 are provided on the top surfaces of the source region 205, the drain region 206, and the polysilicon layer 216 to reduce the contact resistance with the corresponding contact portions.

[0085] From Figure 3 the planar layout diagram of Figure 5 and Figure 6 the cross-sectional view of

[0086] it can be seen that in the MOSFET structure of this embodiment, the contact positions on the source and drain are located outside the channel cross-section, so that the CPP is not affected by the thicknesses of the first sidewall 209 and the second sidewall 210.

[0087] As an example, the third sidewall 211 protrudes from the side of the first sidewall 209 away from the gate structure along the X direction and protrudes from the side of the second sidewall 210 away from the gate structure along the X direction, so as to more effectively isolate the source contact portion 207 from the gate structure and more effectively isolate the drain contact portion 208 from the gate structure.

[0088] As an example, the distance between the source contact portion 207 and the gate structure along the X direction is less than the thickness of the first sidewall 209 along the X direction, and the distance between the drain contact portion 208 and the gate structure along the X direction is less than the thickness of the second sidewall 210 along the X direction, so that CPP < Lg + 2Lsp + Lcnt, which is beneficial to improving the transistor density.

[0089] As an example, the distance between the source contact portion 207 and the gate structure in the X direction may also be equal to 0, and the distance between the drain contact portion 208 and the gate structure in the X direction may also be equal to 0. At this time, CPP = Lg + Lcnt, which is beneficial to further improving the transistor density.

[0090] As an example, the distance between the source contact portion 207 and the gate structure in the X direction may be further less than 0, and the distance between the drain contact portion 208 and the gate structure in the X direction may be further less than 0. At this time, CPP < Lg + Lcnt, which is beneficial to further improving the transistor density.

[0091] As an example, as Figure 3 shown, in this embodiment, the MOSFET structure further includes a gate structure lead-out portion 217 and a gate contact portion 218. The gate structure lead-out portion 217 is located on the substrate 201 and is connected to the first end of the gate structure in the Y direction. The vertical projection of the gate contact portion 218 on the substrate 201 is located in the area where the gate structure lead-out portion 217 is located.

[0092] The area benefit of the MOSFET structure of this embodiment is described below by comparing with a conventional device:

[0093] Please refer to Figure 7 , which shows the planar layout and dimensions of a conventional device. At the 0.13-micron node, the typical dimension of the width a of the device in the Y direction is 0.36 microns, and the typical dimension of the width b of the device in the X direction is 0.3 microns. The device area is a·b. Among them, the sidewall size ratio R1 = 2Lsp / Pitch = 2·0.057 / 0.3 = 38%, and the ratio R2 of the minimum width of the active region to the pitch is 0.15 / 0.21. The dimension of the contact in the Y direction is 0.14 microns.

[0094] Please refer to Figure 8 , which shows a planar layout and dimensions of the MOSFET structure of this embodiment. Among them, the distance between the source contact portion 207 and the gate structure in the X direction is 0, and the distance between the drain contact portion 208 and the gate structure in the X direction is 0. Thus, the width of the MOSFET structure of this embodiment in the X direction is reduced by 38% and is 0.62b. In addition, the width of the MOSFET structure of this embodiment in the Y direction is increased by the dimension of the contact 0.14 microns and the isolation distance of 0.03 microns. Thus, the width value of the MOSFET structure of this embodiment in the Y direction is a + 0.17.

[0095] Therefore, the area ratio R3 of the MOSFET structure of this embodiment to the conventional device is R3 = (a + 0.17)·0.62b / ab = 0.62 + 0.17·0.62 / a. Through calculation, it can be obtained that when the value of a is greater than 0.28, the area ratio R3 is less than 1, that is, when the active area pitch (AA pitch) is greater than 0.28 microns, the total cell area can be reduced. For a 0.13-micron node device, the typical size of a is 0.36 microns. Therefore, the area ratio R3 of the MOSFET structure of this embodiment to the conventional device is R3 = (a + 0.17)·0.62b / ab = 0.62 + 0.17·0.62 / 0.36 = 0.91. That is, at the 0.13-micron node, the area of the MOSFET structure of this embodiment can be reduced to 91% of the conventional device, achieving an area gain.

[0096] Embodiment 2

[0097] This embodiment also provides a MOSFET structure. Please refer to Figure 9 , which shows a planar layout and dimensions of the MOSFET structure of this embodiment. Among them, this embodiment adopts basically the same technical solution as Embodiment 1. The difference is that in Embodiment 1, a gate structure lead-out portion 217 is provided at one end of the gate structure, and the gate contact portion 218 is located in the area where the gate structure lead-out portion 217 is located. In this embodiment, no additional gate structure lead-out portion is provided outside the gate structure, and the gate contact portion 218 is directly placed in the area where the gate structure is located, that is, the vertical projection of the gate contact portion 218 on the substrate 201 is located in the area where the gate structure is located.

[0098] As Figure 9 shown in the dimension information, the width of the MOSFET structure of this embodiment in the X direction is reduced by 38% compared with the conventional device, which is 0.62b. In addition, the width of the MOSFET structure of this embodiment in the Y direction increases by the contact size of 0.14 microns and the isolation distance of 0.03 microns, and reduces the length of the polysilicon end protruding area (the shortest distance from the polysilicon edge to the active area) by 0.07 microns. Finally, the width of the MOSFET structure of this embodiment in the Y direction is a + 0.1 micron.

[0099] Therefore, the area ratio R3 of the MOSFET structure in this embodiment to the conventional device is R3 = (a + 0.1)·0.62b / ab = 0.62 + 0.1·0.62 / a. By calculation, when the value of a is greater than 0.162, the area ratio R3 is less than 1, that is, when the active area pitch (AA pitch) is greater than 0.162 microns, the total cell area can be reduced. For 0.13-micron node devices, the typical size of a is 0.36 microns. Thus, the area ratio R3 of the MOSFET structure in this embodiment to the conventional device is R3 = (a + 0.17)·0.62b / ab = 0.62 + 0.1·0.62 / 0.36 = 0.79. That is, at the 0.13-micron node, the area of the MOSFET structure in this embodiment can be reduced to 79% of the conventional device, with a significant area gain.

[0100] Embodiment III

[0101] This embodiment provides a manufacturing method for a MOSFET structure for manufacturing the MOSFET structure described in Embodiment I or Embodiment II, including the following steps:

[0102] S1: Provide a substrate, form an isolation structure in the substrate to define a first active region, a second active region, and at least two third active regions in the substrate. The first active region and the second active region are spaced along the X direction, and at least two of the third active regions are spaced along the Y direction. Both ends of the third active region along the X direction are respectively connected to the first active region and the second active region. The X direction and the Y direction are both parallel to the plane of the substrate, and the Y direction is perpendicular to the X direction;

[0103] S2: Form a gate structure on the substrate. The gate structure is located on the third active region and extends in the Y direction. The first end of the gate structure along the Y direction protrudes from the first ends of the first active region and the second active region along the Y direction. The second end of the gate structure along the Y direction is spaced a preset distance from the second ends of the first active region and the second active region along the Y direction;

[0104] S3: Form a sidewall dielectric layer on the substrate and pattern the sidewall dielectric layer to obtain a sidewall structure. The sidewall structure includes a first sidewall located at the first end of the gate structure along the X direction, a second sidewall located at the second end of the gate structure along the X direction, and a third sidewall located at the second end of the gate structure along the Y direction;

[0105] S4: Form a source region and a drain region. The source region is located in the first active region, and the drain region is located in the second active region;

[0106] S5: Form an interlayer dielectric layer on the substrate, and form a source contact and a drain contact in the interlayer dielectric layer. The source contact is located above the source region and on the side of the third sidewall away from the gate structure along the Y direction, and the drain contact is located above the drain region and on the side of the third sidewall away from the gate structure along the Y direction.

[0107] Specifically, please refer to Figure 10 , which shows a schematic cross-sectional structure diagram along the X1 direction after the gate structure is formed on the substrate 201 in step S2. It should be noted that the specific positions of the X1 direction and the subsequent X2 direction and X3 direction can be referred to Figure 3 .

[0108] Specifically, for the MOSFET structure of Embodiment 1, when forming the gate structure in step S2, a gate structure lead-out portion 217 (as Figure 3 shown) is also synchronously formed. The gate structure lead-out portion is located on the substrate 201 and is connected to the first end of the gate structure along the Y direction.

[0109] Specifically, please refer to Figure 11 , which shows a schematic cross-sectional structure diagram along the X1 direction after the sidewall dielectric layer 219 is deposited on the substrate 201 and planarized in step S3. The sidewall dielectric layer 219 may include one or more of a silicon nitride layer and a silicon oxide layer.

[0110] Specifically, please Figure 12 and Figure 13 , which shows a schematic cross-sectional structure diagram after the sidewall dielectric layer 219 is patterned to obtain the first sidewall 209, the second sidewall 210, and the third sidewall 211 in step S3. Among them, Figure 12 is a schematic cross-sectional structure diagram along the X1 direction, Figure 13 is a schematic cross-sectional structure diagram along the X2 direction.

[0111] Specifically, please refer to Figure 14 , which shows a schematic cross-sectional structure diagram along the X1 direction after the source region 205 and the drain region 206 are formed in step S4. Among them, the source region 205 and the drain region 206 can be formed by ion implantation and activation.

[0112] Specifically, please refer to Figure 15 , in step S4, after the source region 205 and the drain region 206 are formed, a silicide layer 220 is then formed on the top surfaces of the source region 205, the drain region 206, and the top surface of the gate structure (specifically, the top surface of the polysilicon layer 216), and then step S5 is performed.

[0113] Specifically, please refer to Figure 16 , which shows a schematic cross-sectional structure diagram along the X1 direction after forming the interlayer dielectric layer 221 on the substrate 201 in the step S5 and planarizing the interlayer dielectric layer 221 by chemical mechanical polishing. The interlayer dielectric layer 221 may include one or more of a silicon nitride layer and a silicon oxide layer.

[0114] Specifically, schematic cross-sectional structure diagrams along the X1 direction, along the X2 direction, and along the X3 direction after forming the source contact portion 207 and the drain contact portion 208 in the interlayer dielectric layer 221 in the step S5 are respectively as Figure 4 , Figure 5 and Figure 6 shown.

[0115] Specifically, for the MOSFET structure of the first embodiment, after forming the interlayer dielectric layer 221 in the step S5, it further includes a step of forming a gate contact portion 218 (as Figure 3 shown) in the interlayer dielectric layer 221. The vertical projection of the gate contact portion 218 on the substrate 201 is located in the region where the gate structure lead-out portion 217 is located. For the MOSFET structure of the second embodiment, the vertical projection of the gate contact portion 218 formed after forming the interlayer dielectric layer 221 in the step S5 on the substrate 201 is located in the region where the gate structure is located (as Figure 9 shown).

[0116] In summary, in the MOSFET structure of the present invention, the sidewall structure includes a first sidewall and a second sidewall located at both ends of the gate structure along the X direction, and a third sidewall located at one end of the gate structure along the Y direction. The source contact portion and the drain contact portion are both located on the side of the third sidewall away from the gate structure along the Y direction and are not in the same section as the channel, thereby reducing the contact-polysilicon pitch and being beneficial to improving the transistor density. The manufacturing method of the MOSFET structure of the present invention uses a sidewall patterning process to obtain the above sidewall structure, and the process is simple. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0117] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A MOSFET structure, characterized in that, Comprising: A substrate; A first active region and a second active region, which are located in the substrate and are spaced apart along the X direction, and the X direction is parallel to the plane of the substrate; At least two third active regions, which are located in the substrate and are spaced apart along the Y direction, and both ends of the third active region along the X direction are respectively connected to the first active region and the second active region, the Y direction is parallel to the plane of the substrate, and the Y direction is perpendicular to the X direction; A gate structure, which is located on the third active region and extends in the Y direction, a first end of the gate structure along the Y direction protrudes from a first end of the first active region and the second active region along the Y direction, and a second end of the gate structure along the Y direction is spaced apart from a second end of the first active region and the second active region along the Y direction by a preset distance; A sidewall structure, which includes a first sidewall located at a first end of the gate structure along the X direction, a second sidewall located at a second end of the gate structure along the X direction, and a third sidewall located at a second end of the gate structure along the Y direction; A source region and a drain region, the source region is located in the first active region, and the drain region is located in the second active region; A source contact portion and a drain contact portion, the source contact portion is located above the source region and on a side of the third sidewall away from the gate structure along the Y direction, and the drain contact portion is located above the drain region and on a side of the third sidewall away from the gate structure along the Y direction.

2. The MOSFET structure according to claim 1, characterized in that: The third sidewall protrudes along the X direction from a side of the first sidewall away from the gate structure and protrudes along the X direction from a side of the second sidewall away from the gate structure.

3. The MOSFET structure according to claim 1, wherein: A distance between the source contact portion and the gate structure along the X direction is less than a thickness of the first sidewall along the X direction, and a distance between the drain contact portion and the gate structure along the X direction is less than a thickness of the second sidewall along the X direction.

4. The MOSFET structure according to claim 3, wherein: The distance between the source contact portion and the gate structure along the X direction is less than or equal to 0, and the distance between the drain contact portion and the gate structure along the X direction is less than or equal to 0.

5. The MOSFET structure according to claim 1, characterized in that: The MOSFET structure further includes a gate structure lead-out portion and a gate contact portion, the gate structure lead-out portion is located on the substrate and is connected to a first end of the gate structure along the Y direction, and a vertical projection of the gate contact portion on the substrate is located in a region where the gate structure lead-out portion is located.

6. The MOSFET structure according to claim 1, wherein: The MOSFET structure further includes a gate contact portion, and a vertical projection of the gate contact portion on the substrate is located in a region where the gate structure is located.

7. A manufacturing method of a MOSFET structure, characterized in that, Including the following steps: Provide a substrate, and form isolation structures in the substrate to define a first active region, a second active region, and at least two third active regions in the substrate. The first active region and the second active region are spaced apart along the X direction. At least two of the third active regions are spaced apart along the Y direction. Two ends of the third active region along the X direction are respectively connected to the first active region and the second active region. Both the X direction and the Y direction are parallel to the plane of the substrate, and the Y direction is perpendicular to the X direction. Form a gate structure on the substrate. The gate structure is located on the third active region and extends in the Y direction. A first end of the gate structure along the Y direction protrudes beyond a first end of the first active region and the second active region along the Y direction. A second end of the gate structure along the Y direction is spaced apart from a second end of the first active region and the second active region along the Y direction by a preset distance. Form a sidewall dielectric layer on the substrate, and pattern the sidewall dielectric layer to obtain a sidewall structure. The sidewall structure includes a first sidewall located at a first end of the gate structure along the X direction, a second sidewall located at a second end of the gate structure along the X direction, and a third sidewall located at a second end of the gate structure along the Y direction. Form a source region and a drain region. The source region is located in the first active region, and the drain region is located in the second active region. Form an interlayer dielectric layer on the substrate, and form a source contact portion and a drain contact portion in the interlayer dielectric layer. The source contact portion is located above the source region and on a side of the third sidewall away from the gate structure along the Y direction. The drain contact portion is located above the drain region and on a side of the third sidewall away from the gate structure along the Y direction.

8. The manufacturing method of the MOSFET structure according to claim 7, characterized in that After forming the source region and the drain region and before forming the interlayer dielectric layer, the following steps are further included: form a silicide layer on the top surface of the source region, the top surface of the drain region, and the top surface of the gate structure.

9. The manufacturing method of the MOSFET structure according to claim 7, characterized in that: When forming the gate structure, a gate structure lead-out portion is simultaneously formed. The gate structure lead-out portion is located on the substrate and connected to a first end of the gate structure along the Y direction. After forming the interlayer dielectric layer, the step of forming a gate contact portion in the interlayer dielectric layer is further included. A vertical projection of the gate contact portion on the substrate is located in the region where the gate structure lead-out portion is located.

10. The manufacturing method of the MOSFET structure according to claim 7, characterized in that: After forming the interlayer dielectric layer, the step of forming a gate contact portion in the interlayer dielectric layer is further included. A vertical projection of the gate contact portion on the substrate is located in the region where the gate structure is located.

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