Chip with input / output buffer

Abstract

A chip includes an input / output buffer (I / O buffer), a pad, and a biasing circuit. The I / O buffer is powered by a first power source and coupled to the pad. The pad is coupled to a system power source. When the system power source is on and the first power source is off, the biasing circuit generates a biasing signal and transmits the biasing signal to the I / O buffer to block a leakage path within the I / O buffer. In one example, the biasing circuit is powered by a second power source that is independent of the first power source and does not draw power from the pad. In another example, a power supply terminal of the biasing circuit is coupled to an electrostatic discharge bus, and the pad is coupled to the electrostatic discharge bus through a diode. Embodiments of the present invention are capable of blocking a leakage path and having reduced power consumption when a power source that powers an I / O buffer within a chip is turned off while another power source is turned on.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to buffers, and more specifically, to chips having input / output buffers. Background Technology

[0002] In some scenarios, when the chip's power supply is turned off, current from the system power supply may flow back into the chip through the chip's pads. Therefore, a design is needed to block this leakage path. However, the power consumption of such a design increases with the number of chip pads. How to suppress the power consumption of this design is a significant problem in chip design. Summary of the Invention

[0003] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.

[0004] This invention provides a chip with an input / output buffer that can block the generation of leakage paths within the input / output buffer when the power supply to the chip is disconnected and the system power supply is turned on, and has relatively low power consumption.

[0005] In a first aspect, the present invention provides a chip having an input / output buffer, comprising: a first input / output buffer and a first pad, wherein the first input / output buffer is powered by a first power supply and coupled to the first pad, and the first pad is coupled to a system power supply; a second input / output buffer and a second pad, wherein the second input / output buffer is powered by the first power supply and coupled to the second pad, and the second pad is coupled to the system power supply; and a bias circuit for generating a bias signal to the first input / output buffer and the second input / output buffer when the system power supply is turned on and the first power supply is turned off, so as to block a first leakage path in the first input / output buffer and a second leakage path in the second input / output buffer.

[0006] In some embodiments, the bias circuit is a voltage divider that generates a divided voltage as the bias signal.

[0007] In some embodiments, the bias circuit is powered by a second power supply that is independent of the first power supply and is not derived from either the first pad or the second pad.

[0008] In some embodiments, the chip further includes an electrostatic discharge bus, a first diode, and a second diode; wherein: the power supply terminal of the bias circuit is coupled to the electrostatic discharge bus; the first pad is coupled to the electrostatic discharge bus through the first diode; and the second pad is coupled to the electrostatic discharge bus through the second diode.

[0009] In some embodiments, the first input / output buffer includes a first floating N-well pull-up string and a first pad tracking circuit; the first pad tracking circuit couples the first pad to the gate and body region of a first leakage-proof transistor in the first floating N-well pull-up string according to the bias signal; the second input / output buffer includes a second floating N-well pull-up string and a second pad tracking circuit; and the second pad tracking circuit couples the second pad to the gate and body region of a second leakage-proof transistor in the second floating N-well pull-up string according to the bias signal.

[0010] In some embodiments, the first pad tracking circuit includes a first P-type transistor coupled between the gate of the first leakage protection transistor and the first pad, the gate of the first P-type transistor being controlled by the bias signal; and the second pad tracking circuit includes a second P-type transistor coupled between the gate of the second leakage protection transistor and the first pad, the gate of the second P-type transistor being controlled by the bias signal.

[0011] In some embodiments, the first pad tracking circuit includes a third P-type transistor coupled between the body region of the first leakage protection transistor and the first pad, the gate of the third P-type transistor being controlled by the bias signal; and the second pad tracking circuit includes a fourth P-type transistor coupled between the body region of the second leakage protection transistor and the second pad, the gate of the fourth P-type transistor being controlled by the bias signal.

[0012] Secondly, the present invention provides a chip with an input / output buffer, comprising: an input / output buffer and a pad, wherein the input / output buffer is powered by a first power supply and coupled to the pad, the pad being coupled to a system power supply; a bias circuit for generating a bias signal to the input / output buffer when the system power supply is turned on and the first power supply is turned off, thereby blocking leakage paths within the input / output buffer; wherein: the bias circuit is powered by a second power supply, the second power supply being independent of the first power supply and not derived from the pad.

[0013] In some embodiments, the bias circuit is a voltage divider that generates a divided voltage as the bias signal.

[0014] In some embodiments, the input / output buffer includes a floating N-well pull-up string and a pad tracking circuit; and the pad tracking circuit couples the pad to the gate and body region of the leakage-proof transistor in the floating N-well pull-up string according to the bias signal.

[0015] In some embodiments, the pad tracking circuit includes a P-type transistor coupled between the gate of the leakage protection transistor and the pad, the gate of the P-type transistor being controlled by the bias signal.

[0016] In some embodiments, the pad tracking circuit includes a P-type transistor coupled between the body region of the leakage protection transistor and the pad, the gate of the P-type transistor being controlled by the bias signal.

[0017] Thirdly, the present invention provides a chip with an input / output buffer, comprising: an input / output buffer and a pad, wherein the input / output buffer is powered by a first power supply and coupled to the pad, the pad being coupled to a system power supply; an electrostatic discharge bus and a diode, wherein the diode couples the pad to the electrostatic discharge bus; and a bias circuit for generating a bias signal to the input / output buffer when the system power supply is turned on and the first power supply is turned off, to block leakage paths within the input / output buffer, wherein the power supply terminal of the bias circuit is coupled to the electrostatic discharge bus.

[0018] In some embodiments, the bias circuit is a voltage divider that generates a divided voltage as the bias signal.

[0019] In some embodiments, the input / output buffer includes a floating N-well pull-up string and a pad tracking circuit; and the pad tracking circuit couples the pad to the gate and body region of the leakage-proof transistor in the floating N-well pull-up string according to the bias signal.

[0020] In some embodiments, the pad tracking circuit includes a P-type transistor coupled between the gate of the leakage protection transistor and the pad, the gate of the P-type transistor being controlled by the bias signal.

[0021] In some embodiments, the pad tracking circuit includes a P-type transistor coupled between the body region of the leakage protection transistor and the pad, the gate of the P-type transistor being controlled by the bias signal.

[0022] The following embodiments will be described in detail with reference to the accompanying drawings. The present invention is provided by way of example and is not intended to limit the invention. Those skilled in the art will readily understand these and other objects of the invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. Detailed descriptions are given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the invention. The included drawings are used to provide a further understanding of the embodiments of the invention, and are incorporated in and constitute a part of the embodiments of the invention. The drawings illustrate implementations of the embodiments of the invention and, together with the description, serve to explain the principles of the embodiments of the invention. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the invention.

[0024] Figure 1 This is a schematic diagram of a chip 100 with pad tracking according to an exemplary embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram showing details of the bias circuit 106, power-on system 108, floating N-well pull-up string 110, and pad tracking circuit 112 according to an embodiment of the present invention.

[0026] Figure 3 The present invention illustrates details of how the bias circuit 106 is powered via an electrostatic discharging bus (EBUS).

[0027] Figure 4 A chip with multiple pads 104_1, 104_2…104_N, multiple I / O buffers 102_1, 102_2…102_N and just one single bias circuit 106 is shown.

[0028] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0029] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0030] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0031] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0032] Figure 1 An example of a chip 100 is shown according to an exemplary embodiment of the present invention, in which the chip 100 has pad tracking capability.

[0033] Chip 100 with pad tracking capability includes an input / output buffer (I / O buffer) 102, pads (shown as "PAD") 104, and a bias circuit 106. The I / O buffer 102, powered by the chip's power supply (also interchangeably referred to as the "chip power") VDIO1, is coupled to the pads 104, and the pads 104 are coupled to the system power VDIO2, for example, via a power-on system 108. In this embodiment, the I / O buffer 102 is powered by the chip power supply VDIO1 (understandably, when the chip power supply VDIO1 is off, the I / O buffer 102 is expected to be inactive, and when the chip power supply VDIO1 is on, the I / O buffer 102 is expected to operate normally), while the system power supply VDIO2 is used to power other modules besides the input / output buffer 102. In this case, chip 100 is an overdriven device. The normal voltage levels of the chip power supply VDIO1 and the system power supply VDIO2 are the overdrive voltages. For example, 2*VDDQ, as marked in the figure, can be understood as approximately twice VDDQ, where VDDQ can be the threshold voltage required to turn on the driving transistor. It should be noted that the overdrive voltage is greater than the threshold voltage of the transistor; in this embodiment, 2*VDDQ is used as an example for illustration. Figure 1 This illustrates an example scenario where the system power supply VDIO2 is on (VDIO2 is 2*VDDQ) but the chip power supply VDIO1 is not on (VDIO1 is 0V). In this embodiment of the invention, the system power supply VDIO2 and the chip power supply VDIO1 are independent power supplies. Power supply VDIO1 is dedicated to powering the I / O buffer; in other words, the I / O buffer only functions properly when power supply VDIO1 is on. Therefore, when power supply VDIO1 is off, it is undesirable for leakage paths to exist within the I / O buffer due to the on / off state of other power supplies. In one example, when power supply VDIO1 is on, it can provide a voltage level close to 2*VDDQ, while when it is off, it provides a voltage level of 0V, equivalent to ground.

[0034] exist Figure 1 The diagram only shows the pull-up path of I / O buffer 102. For simplicity, the pull-down path of I / O buffer 102 is not shown. Figure 1The figures are shown in the diagram. Furthermore, for simplicity, the accompanying drawings only illustrate signal flow when power supply VDIO1 is off and VDIO2 is on. It is understood that chip 100, in addition to the example structure shown, may include one or more logic circuits to provide corresponding signals to the next stage when needed for operation. For example, when power supply VDIO1 is off and VDIO2 is on, the logic circuit causes Vmid to be provided to PMOS transistors P2 and P3, and causes the source signals of PMOS transistors P2 and P3 to be provided to the gate and bulk region of the leakage protection transistor P1. The I / O buffer 102 includes a floating N-well pull-up string 110 and a pad-tracking circuit 112. It should be noted that those skilled in the art should understand that a floating N-well pull-up string refers to a pull-up string containing at least one floating N-well PMOS transistor (which is used as a leakage protection transistor, such as...). Figure 2 The PMOS transistor P1 shown is an example of a PMOS transistor whose body region (which is an N-well region) is not coupled to the power supply terminal coupled to the source; that is, the body region and the source of the PMOS transistor have different couplings. The pad tracking circuit 112 is biased by the bias signal Vmid generated by the bias circuit 106. According to the bias signal Vmid, the pad tracking circuit 112 couples the pad 104 to the floating N-well pull-up string 110. Figure 1 As shown, when the bias voltage Vmid is at an appropriate voltage level, the pad level VPAD is coupled to the floating N-well pull-up string 110 via the pad tracking circuit 112. (Reference) Figure 1 In the power supply configuration shown, the system power supply VDIO2 is on (= 2*VDDQ) while the chip power supply VDIO1 is off (= 0V). Because the pad level VPAD (VPAD at 2*VDDQ) is applied to the floating N-well pull-up string 110 (e.g., the pad level VPAD is coupled to the gate of one of the transistors in the floating N-well pull-up string 110), the leakage path within the I / O buffer 102 from pad 104 (VPAD at 2*VDDQ) to VDIO1 (0V) is disrupted (blocked). This avoids unnecessary current consumption.

[0035] In one exemplary embodiment, the bias circuit 106 is powered by another power supply VDIO3. Figure 1 In the power supply scenario shown, such as Figure 1As shown, system power supply VDIO2 is on (=2*VDDQ), chip power supply VDIO1 is off (=0V), and power supply VDIO3 is on (≈2*VDDQ). Note that power supply VDIO3 is not directly derived from the pad voltage VPAD. In an exemplary embodiment, VDIO3 is an additional power supply independent of chip power supply VDIO1 and not derived from pad VPAD (i.e., power supply VDIO3 is independent of power supplies VDIO1 and VDIO2, respectively). In another exemplary embodiment, power supply VDIO3 can be replaced by the electrostatic discharging bus (EBUS) of chip 100 (e.g., ...). Figure 3 (As shown). In this other exemplary embodiment, pad 104 is connected to a diode (as shown). Figure 3 Diode 302 in the circuit is coupled to the electrostatic discharge bus (EBUS), meaning that the bias circuit 106 draws power from the EBUS instead of directly from the pad 104. When the system power supply VDIO2 is on (= 2*VDDQ), the bias circuit 106 is powered by the electrostatic discharge bus (EBUS), where the voltage level of the EBUS is close to 2*VDDQ. In one example, the bias circuit 106 can be a voltage divider that generates a divided voltage as the bias signal Vmid. For example, the bias voltage Vmid can be VDDQ, which is the appropriate voltage level for biasing the pad tracking circuit 112.

[0036] Figure 2 The diagram illustrates the specific circuit structures of the bias circuit 106, power-on system 108, floating N-well pull-up string 110, and pad tracking circuit 112 according to an exemplary embodiment of the present invention. However, the present invention should not be limited to this example structure, and all variations based on the inventive concept should fall within the protection scope of the present invention. For example, in a variant embodiment, the P-type transistor P3 in the pad tracking circuit 112 can be modified into an N-type transistor, the gate of which is controlled by the inverted signal of the bias signal Vmid.

[0037] exist Figure 2In the example, bias circuit 106 is a voltage divider that uses two resistors R1 and R2 to divide the voltage of power supply VDIO3 (≈2*VDDQ) to generate a divided voltage VDDQ as the bias signal Vmid. It should be noted that bias circuit 106 is not limited to a voltage divider; any structure capable of providing a bias signal is acceptable. This bias signal is provided to pad tracking circuit 112 when power supply VDIO1 is off, specifically to the gates of PMOS transistors P2 and P3 within the pad tracking circuit. Power-up system 108 is represented by resistor Rpull_up. One of the transistors (e.g., a PMOS transistor) P1 in the floating N-well pull-up string 110 is used as a leakage-blocking transistor. The pad tracking circuit 112 includes a P-type transistor (e.g., a PMOS transistor) P2, which is coupled between the gate of the leakage protection transistor P1 and the pad 104. The gate of the P-type transistor P2 is controlled by a bias signal Vmid. In the example shown in the figures, the pad tracking circuit 112 may also include a P-type transistor (e.g., a PMOS transistor) P3, which is coupled between the bulk region of the leakage protection transistor P1 and the pad 104. The gate of the P-type transistor P3 is also controlled by the bias signal Vmid. When the system power supply VDIO2 is on (= 2 * VDDQ) and the chip power supply VDIO1 is off (= 0 volts), according to the bias signal Vmid (= VDDQ), the pad voltage VPAD (= 2 * VDDQ) is coupled to the gate of the leakage protection transistor P1 through the on-state P-type transistor P2 and to the bulk region of the leakage protection transistor P1 through the on-state P-type transistor P3. Therefore, the leakage protection transistor P1 is turned off, and thus, the leakage path from VDIO2 through pad 104 and the floating N-well pull-up string 110 to VDIO1 is broken.

[0038] Figure 3 A schematic diagram illustrating how a bias circuit 106 is powered via an electrostatic discharge bus EBUS is described in detail according to an exemplary embodiment of the present invention. Figure 3 As shown, pad 104 is coupled to the electrostatic discharge bus EBUS via diode 302. When the system power supply VDIO2 coupled to pad 104 is turned on (=2*VDDQ), diode 302 couples the overdrive voltage level 2*VDDQ to the electrostatic discharge bus EBUS, and the bias circuit 106 generates a voltage divider voltage VDDQ as the bias voltage Vmid of I / O buffer 102.

[0039] Since the bias circuit 106 does not draw power directly from the pad 104, it is considered an external design and is not limited by the I / O buffer 102. Therefore, when a chip includes multiple pads, different I / O buffers on different pads can share the same bias circuit.

[0040] Figure 4 A schematic diagram of a chip including multiple pads 104_1, 104_2…104_N, multiple I / O buffers 102_1, 102_2…102_N, and a single bias circuit 106 is shown. When the system power supply VDIO2 is on (=2*VDDQ) and the chip power supply VDIO1 is off (=0V), a bias signal Vmid (=VDDQ) is generated by the single bias circuit 106, and the bias signal Vmid is dispatched / transmitted to all I / O buffers 102_1, 102_2…102_N.

[0041] Since only a single bias circuit 106 is needed for pad tracking across multiple pads 104_1, 104_2…104_N, the power consumption of the bias design is reduced. In conventional technology, each I / O buffer is equipped with a dedicated bias circuit, which consumes power, and N I / O buffers require N bias circuits, resulting in particularly high power consumption in conventional bias designs. With the bias circuit located outside the I / O buffer provided by this invention, the power consumption caused by the bias circuit is suppressed to 1 / N times the original amount.

[0042] Any chip that includes an I / O buffer that utilizes external bias circuitry (powered by an additional power supply independent of VDIO1 and not derived from any pad, or by the electrostatic discharge bus EBUS) should be considered within the scope of this invention.

[0043] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify claim elements does not in itself indicate any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with the same name from another element with the same name.

[0044] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. A chip with an input / output buffer, characterized in that, include: A first input / output buffer and a first pad, wherein the first input / output buffer is powered by a first power supply and coupled to the first pad, and the first pad is coupled to the system power supply; A second input / output buffer and a second pad, wherein the second input / output buffer is powered by the first power supply and coupled to the second pad, and the second pad is coupled to the system power supply; and, A bias circuit is used to generate a bias signal to the first input / output buffer and the second input / output buffer when the system power is turned on and the first power is turned off, so as to block the first leakage path in the first input / output buffer and the second leakage path in the second input / output buffer; The first input / output buffer includes a first floating N-well pull-up string and a first pad tracking circuit. The first pad tracking circuit couples the first pad to the gate and body region of the first leakage-proof transistor in the first floating N-well pull-up string according to the bias signal; The second input / output buffer includes a second floating N-well pull-up string and a second pad tracking circuit; and... The second pad tracking circuit couples the second pad to the gate and body region of the second leakage-proof transistor in the second floating N-well pull-up string according to the bias signal.

2. The chip as described in claim 1, characterized in that, The bias circuit is a voltage divider, which generates a divided voltage as the bias signal.

3. The chip as described in claim 1, characterized in that, The bias circuit is powered by a second power supply that is independent of the first power supply and is not derived from either the first pad or the second pad.

4. The chip as described in claim 1, characterized in that, The chip also includes an electrostatic discharge bus, a first diode, and a second diode; in: The power supply terminal of the bias circuit is coupled to the electrostatic discharge bus. The first pad is coupled to the electrostatic discharge bus via the first diode; and The second pad is coupled to the electrostatic discharge bus via the second diode.

5. The chip as described in claim 1, characterized in that: The first pad tracking circuit includes a first P-type transistor coupled between the gate of the first leakage-proof transistor and the first pad, and the gate of the first P-type transistor is controlled by the bias signal. as well as, The second pad tracking circuit includes a second P-type transistor coupled between the gate of the second leakage protection transistor and the first pad, and the gate of the second P-type transistor is controlled by the bias signal.

6. The chip as described in claim 1 or 5, characterized in that: The first pad tracking circuit includes a third P-type transistor coupled between the body region of the first leakage-proof transistor and the first pad, the gate of the third P-type transistor being controlled by the bias signal; and, The second pad tracking circuit includes a fourth P-type transistor coupled between the body region of the second leakage protection transistor and the second pad, and the gate of the fourth P-type transistor is controlled by the bias signal.

7. A chip with an input / output buffer, characterized in that, include: An input / output buffer and a pad, wherein the input / output buffer is powered by a first power supply and coupled to the pad, which is coupled to a system power supply; A bias circuit is used to generate a bias signal to the input / output buffer when the system power is turned on and the first power is turned off, so as to block the leakage path in the input / output buffer; The bias circuit is powered by a second power supply, which is independent of the first power supply and is not derived from the pad. The input / output buffer includes a floating N-well pull-up string and pad tracking circuitry; and, The pad tracking circuit couples the pad to the gate and body region of the leakage-proof transistor in the floating N-well pull-up string according to the bias signal.

8. The chip as described in claim 7, characterized in that, The bias circuit is a voltage divider, which generates a divided voltage as the bias signal.

9. The chip as described in claim 7, characterized in that, The pad tracking circuit includes a P-type transistor coupled between the gate of the leakage protection transistor and the pad, and the gate of the P-type transistor is controlled by the bias signal.

10. The chip as described in claim 7 or 9, characterized in that, The pad tracking circuit includes a P-type transistor coupled between the body region of the leakage protection transistor and the pad, and the gate of the P-type transistor is controlled by the bias signal.

11. A chip with an input / output buffer, characterized in that, include: An input / output buffer and a pad, wherein the input / output buffer is powered by a first power supply and coupled to the pad, and the pad is coupled to a system power supply; An electrostatic discharge bus and a diode, wherein the diode couples the pad to the electrostatic discharge bus; A bias circuit is used to generate a bias signal to the input / output buffer when the system power is turned on and the first power is turned off, so as to block the leakage path within the input / output buffer. The power supply terminal of the bias circuit is coupled to the electrostatic discharge bus. The input / output buffer includes a floating N-well pull-up string and pad tracking circuitry; and, The pad tracking circuit couples the pad to the gate and body region of the leakage-proof transistor in the floating N-well pull-up string according to the bias signal.

12. The chip as described in claim 11, characterized in that, The bias circuit is a voltage divider, which generates a divided voltage as the bias signal.

13. The chip as described in claim 11, characterized in that: The pad tracking circuit includes a P-type transistor coupled between the gate of the leakage protection transistor and the pad, and the gate of the P-type transistor is controlled by the bias signal.

14. The chip as described in claim 11 or 13, characterized in that: The pad tracking circuit includes a P-type transistor coupled between the body region of the leakage protection transistor and the pad, and the gate of the P-type transistor is controlled by the bias signal.

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