Tellurium oxide and thin film transistor including tellurium oxide as channel layer

Abstract

Provided are tellurium oxide and a thin film transistor including the tellurium oxide as a channel layer. Tellurium oxide is a metal oxide including tellurium, wherein a portion of the tellurium is in a Te2O3 state having an oxidation number of 0. 0 state, while the other part of tellurium is in Te with oxidation number 4 4+ state.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a transistor having an oxide semiconductor layer. Background Art

[0002] After the invention of thin film transistors (hereinafter referred to as TFTs) using amorphous silicon, display technology using TFTs has rapidly developed. These amorphous silicon TFTs are mainly used in flat panel displays because they can be formed over a large area at a low price.

[0003] Recently, TFTs using IGZO (In-Ga-Zn-O) or ZnO oxide semiconductors have been developed. These oxide semiconductors can primarily realize n-type semiconductors with electron conductivity, but it is difficult to realize p-type semiconductors with hole conductivity. Although some p-type oxide semiconductors have been developed, the use of TFTs using them is extremely limited due to their low on / off current ratio and low mobility. Summary of the Invention

[0004] Technical issues

[0005] The problem to be solved by the present invention is to provide a hole-conducting oxide semiconductor and a thin film transistor having the hole-conducting oxide semiconductor.

[0006] The technical problems of the present invention are not limited to the technical problems mentioned above, and those skilled in the art will clearly understand other technical problems not mentioned through the following description.

[0007] Technical Solution

[0008] In order to achieve the above object, one aspect of the present invention provides a tellurium oxide. The tellurium oxide is a metal oxide including tellurium, and a portion of the tellurium is in the Te with zero oxidation number. 0 state, while the other part of tellurium is in Te with a tetravalent oxidation number 4+ state.

[0009] In an example, it may contain 30% to 90% Te 0 and 10% to 70% Te 4+ In the example, Te 0 The content can be greater than Te 4+ content.

[0010] The tellurium oxide may be crystalline. The tellurium oxide may be polycrystalline. The tellurium oxide may be a p-type semiconductor. In the tellurium oxide, the energy level at the top of the valence band may be composed of Te 5p orbitals.

[0011] A metal having a positive oxidation number may be doped into tellurium oxide or added to tellurium oxide to form an alloy. A non-metallic element having a negative oxidation number may be doped into tellurium oxide or added to tellurium oxide to form an alloy.

[0012] Tellurium oxide can be represented by Formula 1 below.

[0013] [Formula 1]

[0014] Te 1-a M a O x-b A b

[0015] In Formula 1, x may be greater than 0 and less than 2, M may be a metal with a positive oxidation number, 0≤a≤0.5, A may be an element with a negative oxidation number, and 0≤b≤1. In one example, x may be between 0.2 and 1.2.

[0016] To achieve the above objectives, one aspect of the present invention provides a tellurium oxide semiconductor. The tellurium oxide semiconductor comprises metallic Te and TeO2, wherein the energy level at the top of the valence band is composed of a Te 5p orbital. The metallic Te may be present in an amount of 30 to 90%, and the TeO2 may be present in an amount of 10 to 70%. The metallic Te may be present in a greater molar amount than the TeO2.

[0017] To achieve the above object, one aspect of the present invention provides a method for manufacturing a tellurium oxide semiconductor layer. First, a tellurium oxide layer is deposited on a substrate. The deposited tellurium oxide layer is heat-treated to form a tellurium oxide layer in which a portion of Te is in a Te with an oxidation number of zero. 0 state, while the other part of Te is in Te with a tetravalent oxidation number 4+ tellurium oxide semiconductor layer.

[0018] During the heat treatment process, Te in the tellurium oxide layer 0 The content will decrease and Te 4+ The content of the tellurium oxide layer increases. A passivation layer may be formed covering the surface of the heat-treated tellurium oxide layer. The passivation layer may be a metal oxide insulating layer or a metal layer. The passivation layer may be an Al2O3 layer.

[0019] To achieve the above objectives, one aspect of the present invention provides a thin film transistor. The thin film transistor comprises a gate. A tellurium oxide channel layer comprising tellurium oxide is disposed on or below the gate. A gate insulating layer is disposed between the gate and the tellurium oxide channel layer. A source electrode and a drain electrode are electrically connected to respective ends of the tellurium oxide channel layer.

[0020] The gate insulating layer may be a high-k insulating layer having a higher dielectric constant than that of the silicon oxide layer. A tellurium oxide channel layer may be exposed between the source and drain electrodes, and a passivation layer may be provided between the source and drain electrodes to cover the surface of the exposed tellurium oxide channel layer. The passivation layer may be an Al2O3 layer. A first interfacial layer for mitigating Fermi level pinning between the tellurium oxide channel layer and the gate insulating layer and / or a second interfacial layer for mitigating Fermi level pinning between the tellurium oxide channel layer and the source / drain electrodes may be provided.

[0021] Beneficial effects

[0022] According to an embodiment of the present invention, a hole conductive oxide semiconductor and a thin film transistor having the same can be provided.

[0023] However, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

[0025] Figure 2 is TeO obtained during the manufacturing process of TFT according to Preparation Examples 1 to 7 x Patterned Te 3d 5 / 2 XPS curve diagram.

[0026] Figure 3 The TeO in TFT according to Preparation Example 4 is shown. x HR-TEM (high-resolution-transmission electron microscopy) image of the pattern (a), a screening TEM image of the marked area of ​​the HR-TEM image (b), and a SAED (selected area electron diffraction) pattern of the marked area (c).

[0027] Figure 4a is a graph showing transfer characteristics of TFTs according to Preparation Examples 1 to 6, and Figure 4b is a graph showing output characteristics of the TFT according to Preparation Example 4.

[0028] Figure 5a and Figure 5b are graphs respectively showing the transfer characteristics and the output characteristics of the TFT according to Preparation Example 8.

[0029] Figure 6 The TeO in the TFT according to Preparation Example 9 is shown. xHR-TEM (high-resolution-transmission electron microscopy) image of the pattern (a), a screening TEM image of the marked area of ​​the HR-TEM image (b), and a SAED (selected area electron diffraction) pattern of the marked area (c).

[0030] Figure 7a and Figure 7b are graphs showing transfer characteristics and output characteristics of the TFT according to Preparation Example 9, respectively. DETAILED DESCRIPTION

[0031] Hereinafter, to further illustrate the present invention, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in other forms. In the accompanying drawings, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In this embodiment, the terms "first," "second," or "third" are not intended to impose any limitations on the components, but should be understood as terms used to distinguish between components.

[0032] Tellurium oxide semiconductors

[0033] The tellurium oxide layer according to an embodiment of the present invention is a metal oxide layer containing tellurium and may have hole conductivity, i.e., a P-type semiconductor layer. In the tellurium oxide layer, some of the tellurium may be in an unoxidized state, i.e., a state having an oxidation number of 0, i.e., metal Te (Te 0 ) state. In addition, another portion of the tellurium in the tellurium oxide layer may be in a state with an oxidation number of 4+, i.e., Te 4+ In the example, in the tellurium oxide layer, tellurium can have only metallic Te state and Te 4+ In the example, Te 0 can be contained in an amount of 30% to 90%, and Te 4+ It may be contained in an amount of 10% to 70%. Specifically, Te 0 may be contained in an amount of 35 to 85% or 40 to 80%, and Te 4+ It may be included in an amount of 15 to 65% or 20 to 60%. In another example, Te 0 The content can be greater than Te 4+ content.

[0034] Tellurium oxide may contain metallic Te (i.e., Te 0) and TeO2. In this case, metallic Te may be contained in an amount of 30 to 90%, and TeO2 may be contained in an amount of 10 to 70%. Specifically, metallic Te may be contained in an amount of 35 to 85% or 40 to 80%, and the content of TeO2 may be contained in an amount of 15 to 65% or 20 to 60%. In one example, metallic Te in tellurium oxide may be contained in a larger molar amount than TeO2.

[0035] In one example, one or more metals with an oxidation number of +2, +3, or +4, as examples of metals in a positive oxidation state, may be added to tellurium oxide, where the tellurium oxide may be doped with or alloyed with the metal in a positive oxidation state. The density of holes in the tellurium oxide to which the metal in a positive oxidation state is added can be controlled. The metal in a positive oxidation state may replace a portion of the tellurium in the tellurium oxide. In another example, an element with a negative oxidation number may be doped with or added to the tellurium oxide to form an alloy. The element with a negative oxidation number may replace a portion of the oxygen.

[0036] The energy level of the valence band top of tellurium oxide can be derived from Te 0 The tellurium oxide is composed of the 5p orbital of the oxygen state, and can provide higher hole mobility than the conventionally known p-type oxide semiconductor having an energy level of the valence band top composed of the 2p orbital of oxygen.

[0037] Tellurium oxide may be in an amorphous state or a crystalline state. In addition, as an example of a crystalline state, tellurium oxide may be in a polycrystalline state or a single crystal state.

[0038] Tellurium oxide can be represented by Formula 1 below.

[0039] [Formula 1]

[0040] Te 1-a M a O x-b A b

[0041] In Formula 1, a portion of Te may be in a state having an oxidation number of 0 (Te 0 ) state, while the other part of Te can be in Te with +4 oxidation number 4+ In one example, with Te 4+ In comparison, Te 0 In other words, tellurium oxide may be a mixture of metal Te, i.e., Te 0 and TeO2. In one example, Te in tellurium oxide 0 May be contained in a greater molar amount than TeO2.

[0042] x may be greater than 0 and less than 2, specifically 0.1 to 1.8, more specifically 0.2 to 1.2, for example, may have a value of 0.25 to 1.1 or 0.3 to 1.

[0043] In Formula 1, M can be one or more metals with a positive oxidation number, for example, metals with an oxidation number of +2, +3, or +4, or a combination thereof, and 0 ≤ a ≤ 0.5. For example, M can be Sn, Al, Sb, Hf, La, Y, Zr, Zn, or a combination thereof. In tellurium oxide to which M is added, the density of holes can be controlled.

[0044] In Formula 1, A may be one or more elements having a negative oxidation number, and may be a non-metal element having an oxidation number of -1 or -2, or a combination thereof, and 0 ≤ b ≤ 1. As an example, A may be F, Cl, Br, I, S, Se, or a combination thereof.

[0045] The tellurium oxide semiconductor layer may be formed by depositing a tellurium oxide layer on a substrate and then heat-treating the deposited tellurium oxide layer.

[0046] The tellurium oxide layer may be in an amorphous state in the deposited state. The tellurium oxide layer may be formed using various methods used in the art, and specifically, it may be formed using a physical vapor deposition method such as sputtering or a chemical deposition method such as a chemical vapor deposition method or an atomic layer deposition method. In one embodiment, the tellurium oxide layer may be formed using a sputtering method using a Te target in an oxygen atmosphere. When a in Formula 1 exceeds 0, a sputtering method using a target of the corresponding metal may be additionally applied when depositing the tellurium oxide layer. In addition, in the above formula, when b exceeds 0, the corresponding gas may be contained in the atmosphere when depositing the tellurium oxide layer.

[0047] The heat treatment may be performed in air, oxygen, or vacuum atmosphere at a temperature of about 20 to 300° C., for example, about 50 to 250° C., specifically, 100 to 230° C. During the heat treatment process, the Te in the tellurium oxide layer 0 The content will decrease, and Te 4+ Furthermore, the tellurium oxide layer can be crystallized by heat treatment.

[0048] A passivation layer may be formed covering the surface of the heat-treated tellurium oxide layer. In this case, the crystallinity of the tellurium oxide layer can be further improved. The passivation layer may be a metal oxide insulating film such as Al2O3, HfO2, or ZrO2, or a metal film such as Ta, Ti, Al, or Zn. In this case, the heat applied during the process of forming the passivation layer may cause the metal in the passivation layer to diffuse into the tellurium oxide layer, thereby promoting crystallization.

[0049] The tellurium oxide semiconductor layer may be used as a channel layer of a thin film transistor, a channel layer of a phototransistor, an active layer of a photodetector, an active layer of a gas sensor, etc., which will be described later, but is not limited thereto.

[0050] p-type thin film transistor

[0051] Figure 1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

[0052] refer to Figure 1 , a substrate (10) may be provided. The substrate (10) may be a semiconductor, metal, glass or polymer substrate. A gate (G) extending in one direction may be formed on the substrate (10). The gate (G) may be formed using Al, Cr, Cu, Ta, Ti, Mo, W or an alloy thereof. A gate insulating layer (30) may be formed on the gate (G). The gate insulating layer (30) may be a silicon oxide layer (e.g., a SiO2 layer), a silicon oxynitride (SiON) layer, an aluminum oxynitride layer, a high-k insulating layer having a higher dielectric constant than the silicon oxide layer, or a composite layer thereof. The gate insulating layer (30) may be a high-k insulating layer having a higher dielectric constant than the silicon oxide layer, such as Al2O3, HfO2 or ZrO2. In this case, the driving voltage of the thin film transistor may be reduced.

[0053] A tellurium oxide channel layer (CH) may be formed on the gate insulating layer (30) so as to overlap the gate (20) on the gate (20). The tellurium oxide channel layer (CH) is the above-mentioned tellurium oxide layer and may be a p-type oxide semiconductor having hole conductivity. The tellurium oxide channel layer (CH) may be a semiconductor layer represented by the above formula 1.

[0054] The tellurium oxide channel layer (CH) may be in an amorphous state in a deposited state. The tellurium oxide channel layer (CH) may be formed using various methods used in the art, and specifically, a physical vapor deposition method such as sputtering or a chemical deposition method such as a chemical vapor deposition method or an atomic layer deposition method may be used. In one embodiment, the tellurium oxide channel layer (CH) may be formed using a sputtering method using a Te target in an oxygen atmosphere. In addition, the tellurium oxide channel layer (CH) may be patterned using various methods used in the art. The thickness of the tellurium oxide channel layer (CH) may be several to tens of nanometers, for example, 2 to 20 nm, for example, 5 to 10 nm.

[0055] A source electrode (S) and a drain electrode (D) may be formed on both ends of the tellurium oxide channel layer (CH), and a portion of the surface of the tellurium oxide channel layer (CH) may be exposed between the source electrode (S) and the drain electrode (D). The source electrode (S) and the drain electrode (D) may be formed using at least one metal selected from aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo), or an alloy containing at least one of these, or a metal oxide conductive film such as indium tin oxide (ITO).

[0056] The substrate on which the source / drain (S, D) is formed may be subjected to a heat treatment. The heat treatment may be performed in air, oxygen, or vacuum atmosphere at a temperature of about 20 to 300° C., for example, about 50 to 250° C., specifically, 100 to 230° C. During the heat treatment process, the Te in the tellurium oxide channel layer (CH) is 0 The content will decrease, and Te 4+ The content of tellurium oxide increases. In addition, the heat-treated tellurium oxide channel layer (CH) can be crystallized. In addition, the ohmic junction between the source / drain (S, D) and the metal oxide channel layer (CH) can be improved during the heat treatment process.

[0057] A passivation layer (60) can be formed between the source (S) and the drain (D) to cover the exposed surface of the tellurium oxide channel layer (CH). When the passivation layer (60) is formed, the crystallinity of the tellurium oxide channel layer (CH) can be further improved. The passivation layer (60) can be a metal oxide insulating film such as Al2O3, HfO2, ZrO2, or a metal film such as Ta, Ti, Al, or Zn. In this case, by applying heat in the process of forming the passivation layer (60), the metal in the passivation layer (60) can diffuse into the tellurium oxide channel layer (CH), thereby facilitating crystallization. When the passivation layer (60) is a metal film, the formed passivation layer (60) can be removed.

[0058] The thin film transistor may further include a lower interface layer (41) positioned between the tellurium oxide channel layer (CH) and the gate insulating layer (30) and / or an upper interface layer (43) positioned between the tellurium oxide channel layer (CH) and the source / drain (S, D). The lower interface layer (41) may be formed on the gate insulating layer (30) before forming the tellurium oxide channel layer (CH), and the upper interface layer (43) may be formed on the tellurium oxide channel layer (CH) before forming the source / drain (S, D). When the upper interface layer (43) is formed, the upper interface layer (43) on the tellurium oxide channel layer (CH) may be exposed between the source / drain (S, D). In this case, a passivation layer (60) may be formed in contact with the upper interface layer (43).

[0059] The lower interface layer (41) can reduce Fermi level pinning that may occur at the interface between the tellurium oxide channel layer (CH) and the gate insulating layer (30), while the upper interface layer (43) can reduce Fermi level pinning that may occur at the interface between the tellurium oxide channel layer (CH) and the source / drain (S, D). The lower interface layer (41) and the upper interface layer (43) can be ZnO, TiO2, Al2O3, HfO2 or ZrO2 independently of each other. However, the upper interface layer (43) can have a sufficiently thin thickness to enable charge tunneling to occur between the tellurium oxide channel layer (CH) and the source / drain (S, D). For example, the upper interface layer (43) can have a thickness of several nanometers.

[0060] Figure 1 The thin film transistor illustrated in FIG has a bottom gate / top contact structure, but is not limited thereto. A thin film transistor having a bottom gate / bottom contact structure, a top gate / top contact structure, or a top gate / bottom contact structure may also be implemented. In the top gate structure, the tellurium oxide channel layer is provided below the gate electrode to overlap with the gate electrode, while in the bottom contact structure, the source / drain electrode is positioned below the tellurium oxide channel layer and can be electrically connected to the tellurium oxide channel layer.

[0061] As an example of a complementary TFT circuit, a p-type thin film transistor may form an inverter together with an n-type thin film transistor. In this case, the n-type thin film transistor may include an n-type oxide semiconductor as a channel layer, and the n-type oxide semiconductor may be ZnO, IZO (InZnO), IGO (InGaO), or IGZO (InGaZnO), but is not limited thereto.

[0062] In addition, the p-type thin film transistor can be used as a switching device electrically connected to a pixel electrode of an organic light emitting diode (OLED) or a liquid crystal display, or can be used as a switching element electrically connected to one electrode of a memory device such as a resistance change memory (RRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM). However, the present invention is not limited thereto.

[0063] Hereinafter, preferred examples are provided to help understand the present invention. However, the following examples are only used to help understand the present invention, and the present invention is not limited to the following examples.

[0064] Preparation Example 1

[0065] By thermally oxidizing the p-type Si wafer used as the gate, a 100nm SiO2 layer is grown on the p-type Si wafer as the gate insulating film. A shadow mask is placed on the SiO2 layer, and a TeO2 layer of about 5nm is sputtered using a Te target. xThe pattern is deposited as a semiconductor layer while oxygen as a reactive gas and argon as a carrier gas are supplied into the chamber. x A shadow mask was placed on the pattern, and sputtering was used in an Ar atmosphere to deposit the electrode pattern on the TeO x Source and drain electrodes are formed on both ends of the pattern.

[0066] Preparation Examples 2 to 7

[0067] In addition to the temperature shown in Table 1 below, TeO x A thin film transistor was manufactured using the same method as in Preparation Example 1 except that the layer was heat-treated for 1 hour.

[0068] Table 1 below shows the TeO content during the manufacturing process of TFT according to Preparation Examples 1 to 7. x Composition of patterned films. TeO x The composition of the patterned thin film was measured using X-ray photoelectron spectroscopy (XPS).

[0069] Table 1

[0070]

[0071] Referring to Table 1, it can be seen that as the heat treatment temperature increases, the Te content present in the film decreases, while the O content increases. At the same time, it can be seen that when the heat treatment is performed at a temperature exceeding 250°C or 300°C or higher, the Te content decreases rapidly, presumably because Te volatilizes.

[0072] Figure 2 is TeO obtained during the manufacturing process of TFT according to Preparation Examples 1 to 7 x Patterned Te 3d 5 / 2 XPS curve of Te 3d 5 / 2 The results correspond to Te 4+ and metallic Te(Te 0 The deconvolution of the peaks at 576.1 ± 0.2 eV and 573.1 ± 0.2 eV of the TeO x Te in thin films 4+ and metallic Te(Te 0 ) ratio.

[0073] Refer to Table 1 and Figure 2 It can be seen that with the increase of heat treatment temperature, the metal Te (Te 0 ) ratio decreases, while Te 4 +Specifically, in the case of heat treatment at 150°C or lower (Preparation Examples 1 to 4), it can be seen that the metal Te (Te 0 ) is greater than Te 4+ However, when heat treated at 200°C or higher (Preparation Examples 5 to 7), it can be seen that Te 4+ The ratio is greater than that of metal Te (Te 0 ) ratio.

[0074] Figure 3 The TeO in the TFT according to Preparation Example 4 is shown. x HR-TEM (high-resolution-transmission electron microscopy) image of the pattern (a), a screening TEM image of the marked area of ​​the HR-TEM image (b), and a SAED (selected area electron diffraction) pattern of the marked area (c).

[0075] refer to Figure 3 , it can be seen that the TeO heat treated at 150 degrees x The pattern appears to be crystalline, particularly polycrystalline.

[0076] In addition, the TeO of the TFT heat-treated at 200 degrees according to Preparation Example 5 x The patterns also exhibit similar crystallinity.

[0077] Figure 4a is a graph showing transfer characteristics of TFTs according to Preparation Examples 1 to 6, Figure 4b is a graph showing the output characteristics of the TFT according to Preparation Example 4. When measuring the transfer characteristics of the TFT, the applied voltage between the drain and source (V DS ) is -0.1 V and -10 V. The mobility and on / off ratio of the TFT according to this composition are shown in Table 1.

[0078] refer to Figure 4a and Figure 4b , when a negative voltage is applied to the gate, including the untreated TeO x The patterned TFT (Preparation Example 1) and each comprising a TeO x The patterned TFTs (Preparation Examples 2 to 6) were all turned on, and thus it can be seen that all of the TFTs exhibited p-type TFT characteristics.

[0079] However, including untreated TeO x The patterned TFT (Preparation Example 1) and the TeO x The patterned TFT (Preparation Example 2) showed a low on / off ratio. Also, the TFT comprising TeO 2 was heat-treated at 250°C. xThe patterned TFT (Preparation Example 6) showed slightly poor reproducibility, which is estimated to be due to the volatilization of Te during the heat treatment process described with reference to Table 1.

[0080] Meanwhile, including TeO which was heat-treated at 150 degrees x The patterned TFTs showed excellent output characteristics.

[0081] Preparation Example 8

[0082] A TFT was manufactured in the same manner as in Preparation Example 4 except that a 30 nm Al2O3 layer was formed as a gate insulating film instead of a 100 nm SiO2 layer on a p-type Si wafer as a gate electrode.

[0083] Figure 5a and 5b are graphs showing transfer characteristics and output characteristics of the TFT according to Preparation Example 8, respectively.

[0084] refer to Figure 5a and Figure 5b , the TFT using SiO2 film as gate insulating film according to Preparation Example 4 (FIG. 4, air 150°C) shows a driving voltage of about 50V, while the TFT using Al2O3 film as gate insulating film according to Preparation Example 8 shows a driving voltage of about 10V. x In a thin film transistor as a channel layer, when a high-k insulating layer (Al2O3) is used as a gate insulating layer, the driving voltage is reduced.

[0085] Preparation Example 9

[0086] TeO exposed between the source and drain electrodes of the thin film transistor according to Preparation Example 4 x A 10 nm Al2O3 passivation layer was formed on the pattern using an atomic layer deposition method at 150°C. In Preparation Example 4, after forming the source / drain electrodes, TeO x The layer was heat treated for 1 hour.

[0087] Preparation Example 10

[0088] TeO exposed between the source and drain electrodes of the thin film transistor according to Preparation Example 5 x A 10 nm Al2O3 passivation layer was formed on the pattern using an atomic layer deposition method at 150°C. In Preparation Example 5, after forming the source / drain electrodes, TeO was deposited at 200°C in an atmosphere. x The layer was heat treated for 1 hour.

[0089] Figure 6The TeO in the TFT according to Preparation Example 9 is shown. x HR-TEM (high-resolution-transmission electron microscopy) image of the pattern (a), a screening TEM image of the marked area of ​​the HR-TEM image (b), and a SAED (selected area electron diffraction) pattern of the marked area (c).

[0090] refer to Figure 6 , it can be seen that, compared with the preparation example 4 ( Figure 3 ) of the unpassivated TeO x Compared with the thin film, the TeO passivated with Al2O3 layer x The film exhibits significant crystallinity and also forms grains. The improvement in crystallinity is believed to be due to the doping of Al into the TeO layer in contact with the Al2O3 passivation layer. x The Al2O3 passivation layer is formed at a temperature of about 150℃.

[0091] The TeO of the TFT according to Preparation Example 10 was heat-treated at 200°C. x The film also showed Figure 6 The results were similar to those of

[0092] Figure 7a and 7b are graphs showing transfer characteristics and output characteristics of the TFT according to Preparation Example 9, respectively.

[0093] refer to Figure 7a and Figure 7b The TFT according to Preparation Example 9 includes a TeO passivated with an Al2O3 layer. x The film is thus similar to the one prepared in Example 4 with unpassivated TeO x Compared with the thin film TFT (Figure 4, air 150℃), the on / off current ratio is improved by about 2.6 times and the SS (subthreshold swing) value is improved by about 13 times.

[0094] Although exemplary embodiments of the present invention have been described above, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A thin film transistor, comprising: gate; A tellurium oxide channel layer comprising tellurium oxide and disposed on or under the gate, wherein the tellurium oxide is a metal oxide including tellurium, wherein a portion of the tellurium is in a Te with an oxidation number of zero. 0 state, and the other part of the tellurium is in Te with a valence number of four 4+ state; a gate insulating layer disposed between the gate electrode and the tellurium oxide channel layer; and A source electrode and a drain electrode are electrically connected to two ends of the tellurium oxide channel layer respectively.

2. The thin film transistor according to claim 1, wherein in the tellurium oxide, the Te 0 Contained in an amount of 30 to 90%, the Te 4+ It is contained in an amount of 10 to 70%.

3. The thin film transistor according to claim 1, wherein in the tellurium oxide, the Te 0 The content is greater than Te 4+ content. The thin film transistor according to claim 1 , wherein the tellurium oxide is crystalline. The thin film transistor according to claim 4 , wherein the tellurium oxide is polycrystalline. The thin film transistor according to claim 1 , wherein the tellurium oxide is a p-type semiconductor. 7 . The thin film transistor according to claim 1 , wherein the energy level of the valence band top of the tellurium oxide consists of a Te 5p orbital. 8 . The thin film transistor according to claim 1 , wherein a metal having a positive oxidation number is doped into the tellurium oxide or added to the tellurium oxide to form an alloy. 9 . The thin film transistor according to claim 1 , wherein a non-metal element having a negative oxidation number is doped into the tellurium oxide or added to the tellurium oxide to form an alloy.

10. The thin film transistor according to claim 1, wherein the tellurium oxide is represented by the following formula 1: [Formula 1] yourself 1-a M a A x-b A b In Formula 1, x is greater than 0 and less than 2, M is a metal having a positive oxidation number, 0≤a≤0.5, A is an element having a negative oxidation number, and 0≤b≤1. The thin film transistor according to claim 10 , wherein x is between 0.2 and 1.

2. 12 . The thin film transistor according to claim 1 , wherein the gate insulating layer is a high-k insulating layer having a higher dielectric constant than that of a silicon oxide layer. 13 . The thin film transistor according to claim 1 , wherein the tellurium oxide channel layer is exposed between the source electrode and the drain electrode, and further comprising a passivation layer disposed between the source electrode and the drain electrode to cover a surface of the exposed tellurium oxide channel layer. The thin film transistor according to claim 13 , wherein the passivation layer is an Al 2 O 3 layer.

15. The thin film transistor according to claim 1, further comprising: a first interface layer, the first interface layer being disposed between the tellurium oxide channel layer and the gate insulating layer and being used to alleviate Fermi level pinning between the tellurium oxide channel layer and the gate insulating layer, and / or A second interface layer is provided between the tellurium oxide channel layer and the source / drain electrodes, and is used to alleviate Fermi level pinning between the tellurium oxide channel layer and the source / drain electrodes.

16. A method for manufacturing the thin film transistor of claim 1, comprising: depositing a tellurium oxide layer on a substrate; The deposited tellurium oxide layer is heat-treated to form the tellurium oxide channel layer, wherein a portion of Te is in a Te with zero oxidation number. 0 state, while the other part of Te is in Te with a tetravalent oxidation number 4+ state.

17. The method according to claim 16, wherein in the heat treatment step, Te in the tellurium oxide layer 0 The content of Te 4+ The content increased.

18. The method according to claim 16, further comprising: A passivation layer is formed covering the surface of the heat-treated tellurium oxide layer. The method according to claim 18 , wherein the passivation layer is a metal oxide insulating layer or a metal layer.

20. The method of claim 18, wherein the passivation layer is an Al2O3 layer.

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