Electrical power module

Abstract

The invention relates to an integrated semiconductor power transistor package (10) comprising a half-bridge circuit (100) comprising a negative power terminal of a high-side switch (110) connected in series with a positive power terminal of a low-side switch (130); each switch (110, 130) comprising a plurality of semiconductor power transistor dies (400a, 400b) connected in electrical parallel; a first substrate (41) having a cladding layer (415c) sinter-bonded to at least one semiconductor power transistor die (400b) defining said low-side power switch (130); a second substrate (41) parallel to said first substrate (41); said second substrate (44) having a cladding layer (445d) sinter-bonded to at least one semiconductor power transistor die (400a) defining said high-side power switch (110); a plurality of vertical spacers (425b, 425a); and an encapsulant (460) sealing at least a cavity between said first and second substrates (41, 44).

Description

Technical Field

[0001] This invention relates to multiple semiconductor power transistors with a high power density packaged double-sided cooling package structure. This packaging method reduces thermal resistance, improves the integrity of gate control signals, reduces material costs, and requires fewer manufacturing process steps. Background Technology

[0002] Semiconductor power transistors packaged in half-bridge circuit structures are commonly used to implement DC-AC power inverter circuits, AC-DC power converter circuits, and DC-DC power converter circuits. The semiconductor power transistors used in such power conversion circuits dissipate heat. Effectively dissipating this heat from the package is important for maximizing the power that such semiconductor power transistors can handle while minimizing the size and cost of the semiconductor power transistor package.

[0003] By reducing the number of material layers and bonding layers between the semiconductor power transistor die and the package heat sink, the thermal resistance between them can be minimized. Reducing the number of material and bonding layers further reduces the number of required manufacturing process steps, thereby lowering packaging costs.

[0004] Improvements in semiconductor power transistor technology have increased transistor switching speeds to tens of amperes within nanoseconds. However, the parasitic source inductance of the semiconductor power transistor package, combined with rapid switching current transients, can cause transient voltage spikes that are opposite to the control gate signal. If these transient voltage spikes are not mitigated, they can lead to a significant deterioration in switching performance and, in some cases, device failure.

[0005] The bonding between the semiconductor power transistor die and the substrate typically limits package reliability when subjected to stress caused by thermal cycling. Alternative bonding methods with improved thermal cycling durability can be used to improve overall package reliability.

[0006] Stray inductance within the semiconductor power transistor package and its connection to external circuitry can cause overvoltage transients during fast transistor switching events. If left unmitigated, these overvoltage transients can lead to transistor failure. While increasing the gate resistance can reduce the transistor's switching speed and thus suppress these transients, this reduction in switching speed increases switching losses, which is undesirable.

[0007] Connecting multiple semiconductor power transistors in parallel can cause gate signal resonant oscillations to occur in the parallel-driven transistors. If this oscillation is not mitigated, it can lead to significant changes in dynamic current sharing and junction temperature variations between the parallel transistors, resulting in performance degradation and potential device failure.

[0008] This invention aims to provide embodiments that solve one or more of the problems described above. This disclosure, including improvements to the packaging and cooling of semiconductor power transistors, describes embodiments that allow power semiconductor switches to operate with optimal performance, highest power density, and lowest cost. Summary of the Invention

[0009] This invention discloses an integrated semiconductor power transistor package (10), including a half-bridge circuit (100) and a negative power terminal of a high-side switch (110) connected in series with the positive power terminal of a low-side switch (130); each switch (110, 130) includes a plurality of semiconductor power transistor dies (400a, 400b) connected in parallel; a first substrate (41) having a cover layer (415c) sintered and bonded to at least one semiconductor power transistor die (400b), the at least one semiconductor power transistor die (400b) defining the low-side power switch (130); a second substrate (41) parallel to the first substrate (41); the second substrate (44) having a cover layer (445d) sintered and bonded to at least one semiconductor power transistor die (400a, 400b). 00a), at least one semiconductor power transistor die (400a) defines the high-side power switch (110); a plurality of vertical spacers (425b) sinter bond at least one semiconductor power transistor die (400b) to a cover layer (445c) of the second substrate (44), wherein at least one semiconductor power transistor die (400b) defines a low-side power switch (130) on the first substrate (41); a plurality of vertical spacers (425a) sinter bond at least one semiconductor power transistor die (400a) to a cover layer (415c) of the first substrate (41), wherein at least one semiconductor power transistor die (400a) defines a high-side power switch (110) on the second substrate; and a sealant (460) that at least seals the cavity between the first and second substrates (41, 44).

[0010] This also includes an electrical interconnect structure that forms a Kelvin gate return signal path between the negative power supply terminal pad (220) and the lead frame pin (505b) of each semiconductor power transistor die (400a, 400b).

[0011] It also includes: at least one lead frame pin (505a) bonded to the cover layer of the first substrate (41); and at least one lead frame pin (605a) bonded to the cover layer of the second substrate (44).

[0012] It also includes: at least one heat sink (405a) bonded to the outer cover layer (415a) of the first substrate (41); and at least one heat sink (405b) bonded to the outer cover layer (445a) of the second substrate (44).

[0013] It also includes: a plurality of resistors (810a-810d); and an interconnection structure forming an electrical path, wherein at least one of the resistors (810a-810d) is connected in series between the lead frame pin (505a) and the gate terminal pad (415e) of each semiconductor power transistor die (400a, 400b).

[0014] It also includes: at least one energy absorption buffer die (820a, 820b); and an interconnection structure that forms an electrical connection between the terminals of such buffer die and the positive voltage external terminals and the negative voltage external terminals of the half-bridge circuit (100). Attached Figure Description

[0015] Figure 1 An exemplary half-bridge circuit according to certain embodiments of the present invention is shown.

[0016] Figure 2 A cross-section of a semiconductor power transistor die according to certain embodiments of the present invention is shown schematically.

[0017] Figure 3 An exemplary gate drive circuit structure according to certain embodiments of the present invention is shown.

[0018] Figure 4 A cross-section of an exemplary double-sided cooling package structure according to certain embodiments of the present invention is shown.

[0019] Figure 5 An exemplary structure of a first substrate sub-assembly according to certain embodiments of the present invention is shown.

[0020] Figure 6 An exemplary structure of a second substrate subassembly according to certain embodiments of the present invention is shown.

[0021] Figure 7 An exemplary side view cross-section of an encapsulation structure according to certain embodiments of the present invention is shown.

[0022] Figure 8 Another exemplary structure of a second substrate subassembly according to certain embodiments of the present invention is shown.

[0023] The embodiments of the invention and their advantages can be best understood by referring to the following detailed description. It should be understood that similar reference numerals are used to indicate similar elements shown in one or more drawings, which are shown to illustrate embodiments of the invention and not to limit the scope of protection of the invention. Detailed Implementation

[0024] This invention relates to the packaging of semiconductor power transistors and to apparatus and methods for maximizing power density while minimizing thermal resistance between the packaged transistor and an external heat sink.

[0025] This invention provides embodiments that address one or more of the problems described above. The invention describes improvements to packaging and cooling structures, and describes embodiments that allow packaged semiconductor power transistors to be more efficient, more reliable, have higher power density, and are more cost-effective.

[0026] Figure 1 A schematic half-bridge electrical configuration 100 of two power switches according to the present invention is shown. In some embodiments, each of the two half-bridge power switches 110 and 130 may include one or more semiconductor power transistors connected in parallel. The positive power terminal of the transistor defining the high-side power switch 110 is electrically connected to a positive voltage external terminal 150, and the negative power terminal 170 of the transistor defining power switch 110 is electrically connected to a midpoint terminal 160. The positive power terminal of the transistor defining the low-side power switch 130 is electrically connected to the midpoint terminal 160, and the negative power terminal of the transistor defining power switch 130 is electrically connected to a negative voltage external terminal 170. The semiconductor power transistors defining power switches 110 and 130 are controlled via their respective gate control signal portions 120 and 140.

[0027] In some embodiments, the package may include diode structures 110a and 130a, which include a plurality of semiconductor diode dies connected in parallel with high-side and low-side power switches 110 and 130, respectively.

[0028] Figure 2 A cross-section of an exemplary internal structure of a semiconductor power transistor die 200 according to certain embodiments of the present invention is schematically shown. The schematic diagram of the semiconductor power transistor die 200 shows a positive power terminal pad 210, a negative power terminal pad 220, and a transistor gate terminal pad 230. In some embodiments, the semiconductor power transistor includes a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT) structure. The positive and negative power terminals correspond to the drain and source terminals in the MOSFET transistor structure, respectively. The positive and negative power terminals correspond to the collector and emitter terminals in the IGBT transistor structure, respectively.

[0029] In some embodiments, the MOSFET or IGBT transistor structure may be formed of silicon, silicon carbide, gallium nitride, another III-V semiconductor, or other semiconductor materials.

[0030] Certain embodiments of the present invention can be used to implement DC-to-AC power inverter circuits, AC-to-DC power converter circuits, and DC-to-DC power converter circuits. Such power conversion circuits generate heat as a byproduct. Most of this heat is generated by the semiconductor power transistors within the package. Certain embodiments of the present invention provide a more efficient and uniform way to dissipate heat through the top and bottom surfaces of the package.

[0031] Figure 3 Various embodiments of the semiconductor power transistor gate drive circuits of the present invention are schematically illustrated. Circuit 300a schematically illustrates a common gate drive circuit. A gate driver 320 having a gate drive supply voltage Vdd 320a has a return path electrically connected to a negative potential, which is electrically connected to the negative power terminal 310b of the semiconductor power transistor 310 via a series-connected parasitic inductance Lp 330. This parasitic inductance 330 is a result of the parasitic effects of the electrical interconnect structure within the power semiconductor package and the gate drive circuit 320 outside the power semiconductor package. The gate driver 320 controls the semiconductor power transistor 310 by applying a gate control signal 320b to the gate terminal 310c of the semiconductor power transistor. The semiconductor power transistor 310 is turned on when the voltage Vgn 310d between the gate terminal 310c and the negative power terminal 310b of the semiconductor power transistor 310 is higher than a certain device-specific voltage threshold. Similarly, the semiconductor power transistor is turned off when Vgn 310d is lower than a certain device-specific threshold. The gate control voltage Vgn 310d is also affected by the parasitic inductance Lp 330 and the rate of change of current (di / dt) during the transistor's turn-on and turn-off transients. The gate control voltage Vgn 310d is opposite to the voltage across the parasitic inductance Vind 330a. The effective gate control voltage Vgn 310d can be expressed as:

[0032]

[0033] To mitigate the impact of parasitic inductance Lp 330 on the gate control voltage Vgn 310d, an alternative circuit 300b with a Kelvin gate return signal 350 is directly connected to the negative power terminal of the power semiconductor power transistor. Certain exemplary embodiments of the invention include a package interconnect structure that electrically implements the Kelvin gate return signal 350. An exemplary embodiment 300c of the invention implements a structure for implementing a common gate control signal 320c for a plurality of parallel-connected semiconductor power transistor dies 200. Circuit 300c schematically illustrates three semiconductor power transistor dies 200 connected in parallel. Another exemplary embodiment 300d of the invention includes a package interconnect structure and a plurality of resistive elements 310e, which are electrically connected in series with each of the plurality of parallel-connected semiconductor power transistor dies. An advantage of the invention is that the resistive elements 310e connected in series with each individual semiconductor power transistor die 200 suppress voltage ripple on the gate control signal 320c, which is caused by resonant oscillations between the gate control signal terminals of such parallel-connected semiconductor power transistor dies 200.

[0034] Figure 4 A cross-section of the internal structure of an exemplary half-bridge semiconductor power transistor package according to certain embodiments of the present invention is schematically shown. One embodiment of the semiconductor power transistor die 400a implements a high-side power switch 110. A second embodiment of the semiconductor power transistor die 400b implements a low-side power switch 130. Package 10 includes a first substrate 41 having an exemplary outer copper plating layer 415a and exemplary inner copper plating layers 415c, 415d, and 415e, wherein the outer and inner plating layers are electrically isolated by a substrate core 415b. Package 10 also includes an exemplary second substrate 44 having an exemplary outer copper plating layer 445a and exemplary inner copper plating layers 445c, 445d, 445e, and 445f, wherein the outer and inner plating layers are electrically isolated by a substrate core 445b. In some exemplary embodiments, such first and second substrates 41, 44 may be direct-bonded copper (DBC) substrates, active metal brazing (AMB) substrates, or direct-plated copper (DPC) substrates.

[0035] In the second example, the positive power terminal pad 210 of the low-side power transistor die 400b is directly electrically and thermally bonded to the cladding layer 415c of the first substrate 41 via the bonding layer 450b, wherein this cladding layer 415c forms a mid-point terminal electrical connection 160. The negative power terminal pad 220 of the low-side power transistor die 400b is electrically and thermally bonded to the cladding layer 445c via vertical spacers 425b and bonding layers 430b, 420b, wherein the cladding layer 445c forms a negative voltage external terminal electrical connection 170.

[0036] The positive power terminal pad 210 of the high-side power transistor die 400a is directly electrically and thermally bonded to the cladding layer 445d of the second substrate via bonding layer 450a, wherein the cladding layer 445d forms a positive voltage external terminal electrical connection 150. The negative power terminal pad 220 of the high-side power transistor die 400a is electrically and thermally bonded to the cladding layer 415c via vertical spacer 425a and bonding layers 430a and 420a, wherein the cladding layer 415c forms a midpoint terminal electrical connection 160.

[0037] In some exemplary embodiments, bonding layers 420a, 430a, 450a, 420b, 430b, and 450b are achieved by sintering. A paste or film containing silver, copper, platinum, palladium, or gold particles, microparticles, or nanoparticles can be used to form the sintered bond. Compared to welding, the sintered bond of the present invention has the advantages of significantly reducing thermal cycling fatigue, thereby improving the durability of the bonding layer, and reducing thermal resistance, thereby improving cooling performance.

[0038] In some embodiments, spacers 425a, 425b may be made of a conductive and thermally conductive metal alloy, including copper alloys, Si-filled AlMg alloys, or other alloys having the necessary thermal and electrical conductivity.

[0039] In some exemplary embodiments, the wire bonding structure defines an electrical connection between the gate terminal pad 230 of transistor die 400b and the overlay 415e defining the interconnect structure of the gate control signal 320b, and an electrical connection between the negative power terminal pad 220 of transistor die 400b and the copper overlay 415d that together define the Kelvin gate return signal interconnect structure. The exemplary wire bonding structure correspondingly electrically connects the gate terminal pad 230 and the negative power terminal pad 220 of transistor 400a to corresponding copper overlays 445f and 445e on the second substrate, thereby forming the gate control 320b and Kelvin return signal interconnect structure. In other embodiments, the gate and power terminal pads 220, 230 of transistors 400a, 400b may be wire-bonded to leadframe pins, or the leadframe pins may be directly bonded to the gate 230 and the power terminal pad 220 without bonding wires.

[0040] The heat generated by transistor 400a is partially propagated and transferred through bonding layer 450a, inner copper cladding layer 445e, substrate die 445b, outer copper cladding layer 445a, and heat sink bonding layer 410b, and dissipated by an exemplary external heat sink 405b. The heat generated by transistor 400a is further partially diffused and transferred through bonding layer 430a, spacer 425a, bonding layer 420a, inner copper cladding layer 415c, substrate die 415b, outer copper cladding layer 415a, and heat-dissipating bonding layer 410a, and dissipated by an exemplary external heat sink 405a. The thermal resistance from transistor die 400a to heat sink 405b is proportionally lower than the thermal resistance from die 400a to heat sink 405a. The proportionally higher thermal resistance from die 400a to heat sink 405a is caused by the additional thermal resistance introduced by spacer 425a and bonding layer 420a, and by the fact that the cross-sectional area of ​​spacer 425a is smaller than the total area of ​​die 400a. Due to the inverted complementary structure of this invention, the thermal resistance from die 400b to heat sink 405a is proportionally lower than the thermal resistance from die 400b to heat sink 405b. This complementary thermal resistance relationship results in a lower heat flux concentration on both heat sinks, more uniform cooling performance, and allows for a closer horizontal spacing between dies 400a and 400b, thereby reducing the size and cost of the double-sided cooling package while achieving the same thermal performance. One advantage of this invention is the reduction in the number of material layers and bonding layers between transistors 400a, 400b and external heat sinks 405a, 405b.

[0041] In some exemplary embodiments, heat sinks 405a and 405b may be air-cooled. In other exemplary embodiments, heat sinks 405a and 405b may be liquid-cooled. In some exemplary embodiments, heat sinks 405a and 405b may be flat plates, fins, plates with microchannels, or plates with other microstructures. In some embodiments, heat sinks 405a and 405b may be made of copper alloy, aluminum alloy, or other metal alloys.

[0042] In some exemplary embodiments, the heat sink bonding layers 410a, 410b can be formed by welding. In some embodiments, the bonding layers 410a, 410b can be formed by sintering a paste or film comprising silver, copper, platinum, palladium, or gold particles, microparticles, or nanoparticles. In other embodiments, the bonding layers 410a, 410b can be formed by a thermally conductive adhesive. In other embodiments, the bonding layers 410a, 410b can be formed by a thermal interface material comprising thermally conductive paste and a thermally conductive pad.

[0043] The sealant 460 at least surrounds the cavity formed between the first and second substrates. One advantage of the invention is that the sealant 460 provides mechanical structural support, prevents the ingress of moisture and contaminants, and provides electrical isolation between the power semiconductor transistors and the internal interconnect structures of the package. In some exemplary embodiments, the sealant 460 may comprise a polymer, such as epoxy, polyester, polyurethane, or other plastics.

[0044] Figure 5 A top view of an embodiment including an exemplary first substrate subassembly is shown. This embodiment illustrates an exemplary embodiment of a low-side power switch 130 including four power semiconductor transistor dies 200 connected in parallel.

[0045] An exemplary gate control signal 320c interconnect structure includes copper leadframe pins 505a bonded to a copper-clad layer shape 520, which are further individually bonded to the gate terminal pads 230 of each individual semiconductor power transistor die 200 via wires 560b, 570b, 580b, and 590b.

[0046] An exemplary Kelvin gate interconnect structure for the return signal 360 includes copper leadframe pins 505b bonded to a copper-clad layer shape 510, which are further individually bonded via wires 560a, 570a, 580a, 590a to the negative power terminal pads 220 of each individual semiconductor power transistor die instance.

[0047] The negative power terminal 220 of the semiconductor power transistor die is schematically shown as 560c, 570c, 580c and 590c.

[0048] The top surface of the spacer 425b, which is bonded to the negative power terminal pad of each semiconductor power transistor die instance, is shown by reference numerals 560d, 570d, 580d, and 590d.

[0049] An exemplary interconnect structure for the midpoint terminal 160 includes a power lead frame pin 505d bonded to the copper-clad layer shape 530, which further bonds to the positive power terminal pad of each semiconductor power transistor die instance. One advantage of the invention is the large continuous surface area of ​​the copper-clad layer 530, which minimizes impedance, resulting in lower thermal conductivity losses, while also minimizing stray inductance between the transistor dies in the high-side and low-side power switches 110, 130, thereby improving switching performance and further enhancing the structural rigidity of the package.

[0050] In another exemplary embodiment of this disclosure, copper lead frame pins 505c, bonded to copper cladding 530, provide an external inductive connection to midpoint terminal 160 for implementing an external overcurrent detection circuit.

[0051] Figure 6A top view of an embodiment including an exemplary second substrate subassembly is shown. This embodiment illustrates an exemplary embodiment of a high-side power switch 110 comprising four power semiconductor transistor dies 200 connected in parallel.

[0052] An exemplary interconnect structure for the gate control signal 320c includes a copper leadframe pin 605a bonded to a copper-clad layer shape 620, which is further individually bonded to the gate terminal pad 230 of each individual semiconductor power transistor die 200 via wires 660b, 670b, 680b, and 690b.

[0053] An exemplary interconnect structure for the Kelvin gate return signal 360 includes a copper leadframe pin 605b bonded to a copper-clad layer shape 610, which is further individually bonded via wires 660a, 670a, 680a, and 690a to the negative power terminal pad 220 of each individual semiconductor power transistor die instance.

[0054] The negative power terminals of semiconductor power transistors are schematically shown as 660c, 670c, 680c, and 690c.

[0055] The top surface of the spacer 425a, which is bonded to the negative power terminal pad of each semiconductor power transistor die instance, is shown by 660d, 670d, 680d and 690d.

[0056] An exemplary interconnect structure for the positive voltage external terminal 150 includes a power lead frame pin 605d bonded to a copper layer shape 630. An exemplary interconnect structure for the negative voltage external terminal 170 includes a power lead frame pin 605e bonded to a copper layer shape 640, which further bonds to the positive power terminal pad of each individual semiconductor power transistor die instance. An advantage of the structure of the present invention is the close parallel proximity of the copper layers 630 and 640 corresponding to the positive voltage external terminals 150 and 170 of the half-bridge circuit configuration 100. This parallel proximity suppresses parasitic loop inductance between 150 and 170, thereby reducing the magnitude of switching transient voltage overshoot.

[0057] An exemplary embodiment of the copper lead frame pin 605c, which is bonded to the copper cladding layer 630, provides an external inductive connection to a positive voltage external terminal for implementing an external overcurrent detection circuit.

[0058] One advantage of this invention is achieved by bonding one power leadframe pin 505d to a first substrate and two other power leadframe pins 605d and 605e to a second substrate. The width of the power leadframe pins and the number of power leadframe pins in the same plane drive the overall package width. By separating the three power leadframes in two parallel planes, one plane per substrate, the total package width can be reduced. The cost of two leadframes is twice the material cost of a copper leadframe. In contrast, the material cost per unit area of ​​each substrate is more than 30 times higher than the material cost of each copper leadframe. The reduction in package width allowed by this invention increases overall power density and reduces overall material cost.

[0059] Figure 7 Two side view cross sections are shown, and an exemplary embodiment of a package comprising four power semiconductor transistor dies connected in parallel for each high-side 110 and low-side 130 power switch is provided.

[0060] The cross-sectional plane passes through the semiconductor power transistor die 200, which includes the high-side power switch 110. The cross-sectional plane passes through the semiconductor power transistor die 200, which includes the low-side power switch 130.

[0061] An exemplary power leadframe pin 505d is bonded to a copper plating layer shape 530 on a first substrate via a bonding layer 712. Exemplary power leadframe pins 605d and 605e are bonded to copper plating layer shapes 630 and 640 on a second substrate via bonding layers 714 and 724, respectively. An exemplary signal leadframe pin 605c is bonded to a copper plating layer shape 630 on a second substrate via a bonding layer 715. Signal leadframe pin 505c is bonded to a copper plating layer shape 530 on a first substrate via a bonding layer 725. In some exemplary embodiments of the invention, leadframe pin bonding layers 712, 714, 715, 724, and 725 may be formed by soldering, ultrasonic soldering, or in some embodiments, leadframe pin bonding layers 712, 714, 715, 724, and 725 may be formed using a paste or film containing silver, copper, platinum, palladium, or gold particles, microparticles, or nanoparticles.

[0062] In one exemplary embodiment of the invention, the package and leadframe pins are sealed with sealant 360, except for the leadframe pins 505c, 605c extending beyond the sealant, the exposed power leadframe pin surfaces 711, 713, 723, and the external copper layers 415a, 445a. The advantage of the exposed large surface area of ​​the power leadframe pin surfaces 711, 713, 723 is that it allows for the formation of low-impedance connections to external buses. An exemplary embodiment of the low-impedance engagement between the bus and the power leadframe pin surfaces 711, 713, 723 includes a solder joint. In some exemplary embodiments of the invention, such a solder joint can be formed using ultrasonic welding, laser welding, or electron beam welding.

[0063] The heights of spacers 425a and 425b are determined by i) the required electrical clearance between the internal copper plating shapes (415c, 415d, 415e) of the first substrate 41 and the internal copper plating shapes (445c, 445d, 445e, 445f) of the second substrate 42 and ii) the power lead frame pins on the first substrate 505d and the power lead frame pins on the second substrates 605d and 605e. The minimum electrical clearance depends on the maximum operating voltage of the specific application and the voltage withstand characteristics of the sealant 460 material. In one exemplary embodiment, the height of spacers 425a and 425b is 2.4 mm. Typically, the heights of spaces 425a and 425b will be between 1.5 mm and 5.0 mm.

[0064] Figure 8 A top view of one embodiment of the invention is shown, which includes an exemplary second substrate subassembly. This embodiment illustrates an exemplary embodiment of four power semiconductor transistor dies 200 connected in parallel, each including a high-side power switch 110, wherein individual resistive element examples 810a, 810b, 810c, 810d are electrically connected in series between the interconnect structure of the gate control signal 320c and the gate terminal pad 230 of each individual semiconductor power transistor die 200. An exemplary embodiment of such resistive elements may include surface-mount metal film resistors soldered to a copper-clad layer.

[0065] Another exemplary embodiment of the present invention includes a temperature sensing device 850 having a first terminal and a second terminal, the first terminal being coupled to a copper-clad layer shape 840a further coupled to a leadframe pin 830a, and the second terminal being coupled to a copper-clad layer shape 840b further coupled to a leadframe pin 830b. In other exemplary embodiments, the first terminal may be a sintered bonded to the copper-clad layer shape 840a, and the second terminal may be a wire coupled to the copper-clad layer shape 840b. In some exemplary embodiments, such a temperature sensing device 850 may be a thermistor, a thermocouple, or a resistance temperature detector (RTD). Such a temperature sensing device 850 may be used by external circuitry to monitor the internal temperature of the package for diagnostics, thermal power reduction control, or thermal shutdown control.

[0066] Some exemplary embodiments of the present invention may further include an exemplary energy absorption buffer 800 for suppressing transient voltage oscillations caused by the switching of a semiconductor power transistor 200. The energy absorption buffer is electrically connected between a positive voltage external terminal 150 and a negative voltage external terminal 170. An exemplary embodiment of the buffer may be a resistive-capacitive (RC) buffer 800, comprising a capacitor 800a and a resistor 800c connected in series, both implemented as semiconductor dies, with the bottom surface of the die corresponding to its external capacitor terminal 800b and its top surface corresponding to its external resistor terminal 800d. In some exemplary embodiments of the present invention, each of a plurality of such buffer dies 820a and 820b solders or sinters-bonds its respective terminal 800b to a copper-clad layer shape 630, and its terminal 800d is bonded to a copper-clad layer shape 640 using multiple bonding wires. Advantages of the energy absorption buffer 800 of the present invention include reduced voltage stress on the semiconductor power transistor and reduced high-frequency voltage oscillations.

[0067] In the foregoing specification, this disclosure has been described with reference to specific embodiments. However, as those skilled in the art will understand, the various embodiments disclosed herein can be modified or practiced in various other ways without departing from the spirit and scope of this disclosure. Therefore, this description is to be considered illustrative and intended to teach those skilled in the art to make and use various embodiments of the disclosed invention. It should be understood that the forms of disclosure shown and described herein are to be considered representative embodiments. Equivalent elements, materials, processes, or steps may be used in place of those elements, materials, processes, or steps representatively illustrated and described herein. Furthermore, certain features of this disclosure may be used independently of the use of other features, as will be apparent to those skilled in the art upon benefiting from this description of the disclosure.

[0068] As used herein, the terms “comprising,” “including,” “having,” or any contextual variations thereof are intended to cover non-exclusive inclusion. For example, a process, product, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such a process, product, article, or apparatus. Furthermore, unless expressly stated to the contrary, “or” means inclusive or, not exclusive, or. For example, the condition “A or B” satisfies any of the following conditions: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0069] It should also be understood that one or more elements depicted in the accompanying drawings / figures may also be implemented in a more separate or integrated manner, or even removed or rendered inoperable in some cases, as is useful depending on the specific application.

Claims

1. An integrated semiconductor power transistor package comprising a half bridge circuit comprising a negative power terminal of a high side power switch connected in series with a positive power terminal of a low side power switch; each power switch comprising a plurality of semiconductor power transistor dies connected in electrical parallel; a first substrate having a midpoint terminal copper clad layer shape sinter bonded to positive power terminal pads of at least one semiconductor power transistor die defining said low side power switch; a second substrate parallel to said first substrate; said second substrate having a positive voltage external terminal copper clad layer shape sinter bonded to positive power terminal pads of at least one semiconductor power transistor die defining said high side power switch; a plurality of first vertical spacers sinter bonding negative power terminal pads of at least one semiconductor power transistor die to negative voltage external terminal copper clad layer shapes of said second substrate wherein at least one semiconductor power transistor die defines a low side power switch on said first substrate; a plurality of second vertical spacers sinter bonding negative power terminal pads of at least one semiconductor power transistor die to midpoint terminal copper clad layer shapes of first substrate wherein at least one semiconductor power transistor die defines a high side power switch on said second substrate; a positive voltage external terminal power supply lead frame pin bonded to a copper clad layer shape of second substrate, a negative voltage external terminal power supply lead frame pin bonded to a copper clad layer shape of second substrate wherein the positive voltage external terminal power supply lead frame pin is adjacent to the negative voltage external terminal power supply lead frame pin; at least one of the second substrate power supply lead frame pins is at least partially covered by a midpoint voltage external terminal power supply lead frame pin wherein the power supply lead frame pins are bonded to copper clad layer shapes of first substrate; and a sealant sealing at least a cavity between said first and second substrates and a cavity between second substrate power supply lead frame pins and first substrate power supply lead frame pins. Further comprising:

2. The integrated semiconductor power transistor package of claim 1, wherein, an electrical interconnect structure forming a Kelvin gate return signal path between negative supply terminal pads of each semiconductor power transistor die and lead frame pins. Further comprising:

3. The integrated semiconductor power transistor package of any of the preceding claims, wherein, at least one first lead frame pin bonded to a cladding of said first substrate; and at least one second lead frame pin bonded to a cladding of said second substrate. Further comprising: at least one first heat sink bonded to an outer cladding of said first substrate; and 4. The integrated semiconductor power transistor package of claim 1, wherein, at least one second heat sink bonded to an outer cladding shape of said second substrate. Further comprising: a plurality of resistors; and an interconnect structure forming an electrical path wherein at least one of the resistors is connected in series between a lead frame pin and a gate terminal pad of each semiconductor power transistor die.

5. The integrated semiconductor power transistor package of claim 1, wherein: Further comprising: at least one energy absorbing snubber die; and an interconnect structure forming an electrical connection between such snubber die terminals and positive voltage external terminals and negative voltage external terminals of said half bridge circuit. Further comprising:

6. The integrated semiconductor power transistor package of claim 1, wherein, at least one energy absorbing snubber die; and an interconnect structure forming an electrical connection between such snubber die terminals and positive voltage external terminals and negative voltage external terminals of said half bridge circuit. ​ ​

Images