Semiconductor package including substrate and high-density interconnect structure coupled thereto.

Abstract

A package includes a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure, and the substrate are coupled together such that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels at least through the substrate, then through the interconnect structure, and returns through the substrate.

Description

[0001] Priority requirements under 35 USC §119

[0002] This patent application claims priority to non-provisional application number 16 / 803,804, filed on February 27, 2020, entitled “Package including a substrate and a high-density interconnect structure coupled to the substrate,” which has been assigned to the assignee and is incorporated herein by reference. Technical Field

[0003] Various features relate to packages that include integrated devices, but more specifically, to packages that include integrated devices, substrates, and high-density interconnect structures coupled to the substrates. Background Technology

[0004] Figure 1 Package 100 is shown, comprising a substrate 102, an integrated device 104, and an encapsulation layer 108. Substrate 102 includes multiple dielectric layers 120, multiple interconnects 122, and multiple solder interconnects 124. Multiple solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. Encapsulation layer 108 encapsulates the integrated device 104 and the multiple solder interconnects 144. Fabricating small packages including substrates with high-density interconnects can be challenging. There is currently a need for more compact packages that can accommodate high-density interconnects and / or high pin counts. Summary of the Invention

[0005] Various features relate to packages that include integrated devices, but more specifically, to packages that include integrated devices, substrates, and high-density interconnect structures coupled to the substrates.

[0006] One example provides a package including a substrate, an integrated device, and interconnect structures. The substrate includes a first surface and a second surface. The substrate further includes multiple interconnects. The integrated device is coupled to the substrate. The interconnect structures are coupled to the surfaces of the substrate. The integrated device, interconnect structures, and substrate are coupled together in such a way that a first electrical signal of the integrated device is configured to travel at least through the substrate, then through the interconnect structures, and back through the substrate.

[0007] Another example provides a device including a substrate, an integrated device, and components for interconnect redistribution. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The components for interconnect redistribution are coupled to a surface of the substrate. The integrated device, the components for interconnect redistribution, and the substrate are coupled together such that a first electrical signal of the integrated device is configured to travel at least through the substrate, then through the components for interconnect redistribution, and back through the substrate.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate including a first surface and a second surface, wherein the substrate further includes a plurality of interconnects. The method couples an integrated device to the substrate. The method couples an interconnect structure to the surface of the substrate. The integrated device, the interconnect structure, and the substrate are coupled together such that a first electrical signal of the integrated device is configured to travel at least through the substrate, then through the interconnect structure, and back through the substrate. Attached Figure Description

[0009] Various features, properties and advantages will become apparent from the following detailed description when viewed in conjunction with the accompanying drawings, in which similar reference characters are identified correspondingly throughout the drawings.

[0010] Figure 1 A side view of the package, including the integrated devices and the substrate, is shown.

[0011] Figure 2 A side view of the package, including a high-density interconnect structure coupled to the substrate, is shown.

[0012] Figure 3 This diagram shows a view of possible electrical paths in a package that includes a high-density interconnect structure coupled to a substrate.

[0013] Figure 4 This diagram shows a view of possible electrical paths in a package that includes a high-density interconnect structure coupled to a substrate.

[0014] Figure 5 This diagram shows a view of possible electrical paths in a package that includes a high-density interconnect structure coupled to a substrate.

[0015] Figure 6 A side view of a package-on-package (PoP) showing a high-density interconnect structure coupled to a substrate is presented.

[0016] Figure 7 A side view of the package, including a high-density interconnect structure coupled to the substrate, is shown.

[0017] Figure 8 (including) Figures 8A to 8D This demonstrates an exemplary sequence for manufacturing high-density interconnect structures.

[0018] Figure 9 An exemplary flowchart of a method for manufacturing high-density interconnect structures is shown.

[0019] Figure 10 (including) Figures 10A to 10C The example sequence for manufacturing the substrate is shown.

[0020] Figure 11 An exemplary flowchart of a method for manufacturing a substrate is shown.

[0021] Figure 12 (including) Figures 12A to 12B This illustrates an exemplary sequence for manufacturing a package that includes a high-density interconnect structure coupled to a substrate.

[0022] Figure 13 An exemplary flowchart of a method for manufacturing a package is shown, the package including a high-density interconnect structure coupled to a substrate.

[0023] Figure 14 Various electronic devices are showcased that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Detailed Implementation

[0024] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring various aspects with unnecessarily detailed information. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring various aspects of this disclosure.

[0025] This disclosure describes a package including a substrate, electronic circuitry (which may be formed in an integrated device), and interconnect structures. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing electrical connections to a board. The integrated device is coupled to the first surface (or the second surface) of the substrate. The interconnect structures are coupled to the first surface (or the second surface) of the substrate. The integrated device, the interconnect structures, and the substrate are coupled together such that a first electrical signal of the integrated device is configured to travel through the substrate, then through the interconnect structures, and back through the substrate. The interconnect structures may provide at least one electrical connection between two integrated devices coupled to the substrate. The interconnect structures may be substrates including a dielectric layer and a plurality of redistributed interconnects. The interconnect structures may be high-density interconnect structures configured to have interconnects with a minimum pitch smaller than the minimum pitch of interconnects from the substrate. The interconnect structures allow the package to have a small and compact form factor while also providing a high input / output (I / O) pin count.

[0026] Exemplary package including a high-density interconnect structure coupled to a substrate

[0027] Figure 2 A side view of package 200, including a high-density interconnect structure, is shown. Package 200 is coupled to board 290 (e.g., printed circuit board (PCB)) via multiple solder interconnects 280. Package 200 provides a compact form factor package while also featuring a high input / output pin count.

[0028] like Figure 2 As shown, package 200 includes substrate 202, first integrated device 204, second integrated device 206, encapsulation layer 208, first interconnect structure 210, and second interconnect structure 230. Substrate 202 can be considered as the main substrate of package 200 (e.g., the first substrate). As will be further described below, the integrated device (e.g., 204, 206), interconnect structure (e.g., 210, 230), and substrate 202 are coupled together in such a way that when an electrical signal (e.g., a first electrical signal, a second electrical signal) travels between the integrated device and the board (e.g., 290), the electrical signal travels through at least substrate 202, then through the interconnect structure (e.g., 210, 230), and returns through substrate 202. This can be achieved by an interconnect structure (e.g., 210, 230) providing at least one electrical path between a first electrical contact provided by substrate 202 and a second electrical contact provided by substrate 202, wherein the first contact is electrically connected to an integrated device (e.g., 204, 206), and wherein the second contact is connected to one or more of the interconnects.

[0029] Substrate 202 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). Substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder mask layer 224, and a second solder mask layer 226. The plurality of interconnects 222 may be configured to provide at least one electrical connection to and / or from a board (e.g., 290). The plurality of interconnects 222 may have a first minimum pitch and a first minimum line spacing (L / S). In some embodiments, the first minimum pitch of the plurality of interconnects 222 is in the range of approximately 100-200 micrometers (μm). In some embodiments, the first minimum line spacing (L / S) of the plurality of interconnects 222 is in the range of approximately 5 / 5-20 / 20 micrometers (μm). Different embodiments may use different substrates. Substrate 202 may be a laminated substrate, a coreless substrate, or a substrate including a core layer. In some embodiments, at least one dielectric layer 220 may include a core layer and / or a prepreg layer. At least one dielectric layer 220 may have a dielectric constant in the range of approximately 3.5-3.7. At least one dielectric layer 220 may include a glass fabric for reinforcing the substrate 202. (The following is incomplete and requires further context.) Figures 10A to 10C Examples of substrate fabrication are further described below. As will be further described below, in some embodiments, substrate 202 may be fabricated using a modified semi-additive process (mSAP) or a semi-additive process (SAP).

[0030] A first integrated device 204 is coupled to a first surface (e.g., the bottom surface) of a substrate 202. The first integrated device 204 is coupled to the substrate via a plurality of interconnects 240. The plurality of interconnects 240 may include copper pillars and / or solder interconnects. An underfill 242 is located between the substrate 202 and the first integrated device 204. The underfill 242 may surround the plurality of interconnects 240. A first interconnect structure 210 is coupled to the first surface of the substrate 202. As will be further described below, the first interconnect structure 210 may be a high-density interconnect structure. The first interconnect structure 210 may be coupled to the substrate 202 via a plurality of solder interconnects 250 and / or pillar interconnects (e.g., copper pillar interconnects). When the package 200 is coupled to a board 290, the first integrated device 204 and the first interconnect structure 210 are located between the substrate 202 and the board 290. The first integrated device 204 and the first interconnect structure 210 may be located laterally to the plurality of solder interconnects 280. This configuration places the first integrated device 204 and the first interconnect structure 210 on the same side as the plurality of solder interconnects 280, which saves space and helps reduce the overall height and footprint of the package 200 by reducing the number of metal layers in the substrate 202 and / or reducing wiring congestion in the substrate 202. The end result is a package with a more compact form factor. Furthermore, the first interconnect structure 210 can help reduce the cost of the substrate 202 (e.g., the main substrate) because the interconnects of the substrate 202 do not need to be so close together (e.g., a lower L / S ratio) to achieve die disconnection, as the interconnects of the first interconnect structure 210 will facilitate close-to-die disconnection. As will be further described below, at least one interconnect structure may be located above another surface of the substrate 202. In some embodiments, the interconnect structure may be integrated or embedded within the substrate 202.

[0031] The second integrated device 206 is coupled to a second surface (e.g., the top surface) of the substrate 202. The second integrated device 206 is coupled to the substrate via a plurality of interconnects 260. The plurality of interconnect structures 260 may include copper pillars and / or solder interconnects. A second interconnect structure 230 is coupled to the second surface of the substrate 202. The second interconnect structure 230 may be coupled to the substrate 202 via a plurality of solder interconnects 270.

[0032] Encapsulation layer 208 is located over a second surface (e.g., top surface) of substrate 202, such that encapsulation layer 208 encapsulates second integrated device 206 and second interconnect structure 230. Encapsulation layer 208 may include a mold, resin, epoxy resin, and / or polymer. Encapsulation layer 208 may be a means for encapsulation.

[0033] Integrated devices (e.g., 204, 206) may include dies (e.g., bare semiconductor dies). Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, GaAs-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon carbide (SiC)-based integrated devices, memories, and / or combinations thereof. Integrated devices (e.g., 204, 206) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0034] Different implementations may couple different components to substrate 202. Other components that may be coupled to substrate 202 (e.g., surface-mount components) include passive devices (e.g., capacitors). Examples of other components that may be coupled to substrate 202 are shown below. Figure 7 The text is presented and described in Chinese.

[0035] The first interconnect structure 210 and the second interconnect structure 230 can be high-density interconnect structures having a second minimum pitch and a second minimum line spacing (L / S). In some embodiments, the second minimum pitch of the interconnects for the interconnect structures (e.g., 210, 230) is in the range of approximately 100-200 micrometers (μm). In some embodiments, the second minimum line spacing (L / S) of the interconnects for the interconnect structures (e.g., 210, 230) is in the range of approximately 5 / 5-20 / 20 micrometers (μm) (e.g., a minimum linewidth of approximately 5-20 micrometers (μm) and a minimum spacing of approximately 5-20 micrometers (μm)). The first interconnect structure 210 and the second interconnect structure 230 can each have an interconnect having a corresponding second minimum pitch smaller than the first minimum pitch of the substrate 202. Similarly, the first interconnect structure 210 and the second interconnect structure 230 can each have an interconnect having a corresponding minimum pitch smaller than the first minimum line spacing (L / S) of the substrate 202. Interconnect structures (e.g., 210, 230) can be considered secondary substrates (e.g., second substrates) that include interconnects with a higher density than those on substrate 202 (e.g., the main substrate). Interconnect structures (e.g., 210, 230) are local devices and / or structures configured to be placed in a region near an integrated device. The size of the interconnect structures can vary depending on the implementation. However, the footprint of the interconnect structures will be smaller than the footprint of substrate 202. For example, in some implementations, the area occupied by the interconnect structures (e.g., 210, 230) may be 25% or less of the area of ​​substrate 202.

[0036] As will be further described below, some electrical signals (e.g., a first electrical signal, a second electrical signal) to and from integrated devices (e.g., 204, 206) can be configured to travel through a first interconnect structure 210 and / or a second interconnect structure 230. Interconnect structures with higher density interconnects allow package 200 to provide a higher number of I / O pins without increasing the size of package 200. For example, using interconnect structures (e.g., 210, 230) allows substrate 202 to have a smaller number of metal layers, which helps reduce the overall height of package 200. One or more interconnect structures (e.g., 210, 230) can help reduce congestion and / or entanglement in certain areas of substrate 202 (e.g., areas close to integrated devices) caused by a large number of pins and / or netlists.

[0037] Figure 2 A first interconnect structure 210 is shown, comprising at least one dielectric layer 211, a plurality of interconnects 212, a solder mask layer 214, and a solder mask layer 216. The plurality of interconnects 212 may be redistributed interconnects. The redistributed interconnects may be interconnects fabricated using a redistributed layer (RDL) manufacturing process. The first interconnect structure 210 may be configured as a substrate (e.g., a coreless substrate) including a plurality of redistributed layers (e.g., redistributed metal layers). As described above, the interconnects of the interconnect structure may have a higher density (e.g., a lower minimum pitch and / or a lower minimum L / S) than the interconnects of substrate 202. The solder mask layer 214 is located above a first surface of the first interconnect structure 210. The solder mask layer 216 is located above a second surface of the first interconnect structure 210. A plurality of solder interconnects 250 are coupled to the first surface of the first interconnect structure 210.

[0038] The second interconnect structure 230 is similar to the first interconnect structure 210. The second interconnect structure 230 may include the same components and / or materials as the first interconnect structure 210. The second interconnect structure 230 may include a different number of metal layers (e.g., redistribution layers) than the first interconnect structure 210. Interconnect structures can be used to provide at least one electrical connection between two or more integrated devices. For example, electrical signals between the first and second integrated devices can pass through a substrate (e.g., through a first plurality of interconnects through the substrate), through the interconnect structure (e.g., through a plurality of interconnects through the interconnect structure), and back through the substrate (e.g., through a second plurality of interconnects through the substrate). The first and second integrated devices may be located above the same surface of the substrate or above different surfaces of the substrate. The terms "first surface" and "second surface" for substrate are arbitrary and can refer to any surface of the substrate. For example, the first surface of the substrate may be the bottom surface of the substrate, and the second surface of the substrate may be the top surface of the substrate. In another example, the first surface of the substrate may be the top surface of the substrate, and the second surface of the substrate may be the bottom surface of the substrate. Interconnect structures (e.g., 210, 230) may be means for interconnect redistribution. The following... Figures 8A to 8D Examples of methods for manufacturing interconnect structures are shown and described in the document.

[0039] As described above, interconnect structures are components coupled to substrate 202, allowing package 200 to provide a higher number of I / O pins without increasing the overall size of package 200. In some embodiments, one or more electrical signals to and from one or more integrated devices can travel through one or more interconnect structures. One or more interconnect structures (e.g., 210, 230) can help reduce congestion and / or entanglement in certain areas of the substrate due to a large number of pins and / or netlists. A netlist is the arrangement of circuit components and how the components are electrically coupled together.

[0040] In some embodiments, at least one dielectric layer 211 may include a prepreg layer and / or a photoimageable dielectric layer. At least one dielectric layer 211 may have a dielectric constant in the range of approximately 3.3-4.0. In some embodiments, at least one dielectric layer 211 of the interconnect structure may include a glass fabric. However, the glass fabric will be thinner than the glass fabric in at least one dielectric layer 220 of the substrate 202.

[0041] Figure 3 This illustrates a conceptual view of how electrical signals can be configured to travel within a package. (e.g.) Figure 3As shown, the first electrical signal 302 can be configured to travel to and from the first integrated device 204. The path of the first electrical signal 302 (when starting from the first integrated device 204) includes traveling through (i) multiple first interconnects from multiple interconnects 240, (ii) multiple first interconnects from multiple interconnects 222 of the substrate 202, (iii) multiple first solder interconnects from multiple solder interconnects 250, (iv) multiple first interconnects (e.g., 212) from the first interconnect structure 210, (v) multiple second solder interconnects from multiple solder interconnects 250, (vi) multiple second interconnects from multiple interconnects 222 of the substrate 202, (vii) first solder interconnects from multiple solder interconnects 280, and (viii) interconnects of the board 290. In some embodiments, the first electrical signal 302 can be configured to travel from the board 290 to the first integrated device 204 in the reverse order described above. Therefore, as described above, the first integrated device 204, the first interconnect structure 210 and the substrate 202 can be coupled together such that the first electrical signal 302 between the first integrated device 204 and the board 290 can be configured to travel through the substrate 202, then through the first interconnect structure 210 and back through the substrate 202.

[0042] Figure 3 A second electrical signal 304 is shown, which can be configured to travel to and from the first integrated device 204. The path of the second electrical signal 304 (when starting from the first integrated device 204) includes traveling through (i) multiple second interconnects from multiple interconnects 240, (ii) multiple third interconnects from multiple interconnects 222 of the substrate 202, (iii) multiple third solder interconnects from multiple solder interconnects 250, (iv) multiple second interconnects (e.g., 212) from the first interconnect structure 210, (v) multiple fourth solder interconnects from multiple solder interconnects 250, (vi) multiple fourth interconnects from multiple interconnects 222 of the substrate 202, (vii) second solder interconnects from multiple solder interconnects 280, and (viii) interconnects of the board 290. In some embodiments, the second electrical signal 304 can be configured to travel from the board 290 to the first integrated device 204 in the reverse order described above.

[0043] Figure 3A third electrical signal 306 is shown, which can be configured to travel to and from the first integrated device 204. The path of the third electrical signal 306 (when starting from the first integrated device 204) includes traveling through (i) multiple third interconnects from multiple interconnects 240, (ii) multiple fifth interconnects from multiple interconnects 222 of the substrate 202, (iii) multiple third solder interconnects from multiple solder interconnects 280, and (iv) interconnects of the board 290. In some embodiments, the third electrical signal 306 can be configured to travel from the board 290 to the first integrated device 204 in the reverse order described above.

[0044] Figure 3 A fourth electrical signal 308 is shown, which can be configured to travel to and from the second integrated device 206. The path of the fourth electrical signal 308 (when starting from the second integrated device 206) includes traveling through (i) multiple first interconnects from multiple interconnects 260, (ii) multiple sixth interconnects from multiple interconnects 222 of the substrate 202, (iii) multiple first solder interconnects from multiple solder interconnects 270, (iv) multiple first interconnects from the second interconnect structure 230, (v) multiple second solder interconnects from multiple solder interconnects 270, (vi) multiple seventh interconnects from multiple interconnects 222 of the substrate 202, (vii) a fourth solder interconnect from multiple solder interconnects 280, and (viii) interconnects of the board 290. In some embodiments, the fourth electrical signal 308 can be configured to travel from the board 290 to the second integrated device 206 in the reverse order described above.

[0045] It should be noted that the multiple solder interconnects 280 may represent pins of package 200. Therefore, the illustrated electrical signals and / or electrical paths may represent electrical signal paths between the integrated device and the pins of the package, where the pins are represented by solder interconnects from the multiple solder interconnects 280. It should be noted that the pins may be represented by other components, such as pillars (e.g., copper pillars). Different embodiments may have different numbers of electrical signals going to and from different integrated devices. The paths of these electrical signals may differ. The electrical signals may include I / O signals. Instead of I / O signals, the exemplary paths shown in this disclosure may also be applicable to power and / or ground.

[0046] Figure 4 This shows another view of how electrical signals can conceptually travel through an encapsulation. Figure 4A substrate 402, a first integrated device 204 coupled to the substrate 402, a first interconnect structure 210 coupled to the substrate 402, a second interconnect structure 410a coupled to the substrate 402, a third interconnect structure 410b coupled to the substrate 402, and a plurality of solder interconnects 280 coupled to the substrate 402 are shown. The plurality of solder interconnects 280 may represent pins of the substrate 402 and / or pins of a package including the substrate 402. The substrate 402 may be implemented in any of the packages described in this disclosure.

[0047] The first integrated device 204 can be configured to perform various functions, conceptually represented by first function 420, second function 430, third function 440, fourth function 450, and fifth function 460. Different integrated devices can be configured to perform different functions and / or different numbers of functions. Examples of functions include processing functions, computing functions, filtering functions, transmission functions, receiving functions, compression functions, etc. In some embodiments, each function can be associated with a specific netlist of the package.

[0048] like Figure 4 As shown, electrical signals 422 going to and from the first function 420 of the first integrated device 204 can travel through the substrate 402, the first interconnect structure 210, and return through the substrate 402 (to connect with...). Figure 3 (Similar to the description in the text). Another electrical signal 424, going to and from the first function 420, can travel through the substrate 402, bypassing the interconnect structure.

[0049] One advantage of high-density interconnect structures is their ability to handle and manage packaged wiring entanglement and / or wiring congestion. In some implementations, complex, tight, and / or difficult wiring for interconnects can be accomplished within an interconnect structure (e.g., 210). For example, wiring entanglement and / or crossings for interconnects of different signals can be accomplished within an interconnect structure (e.g., 210). Figure 4 An electrical signal 432 is shown that travels to and from the second function 430 of the first integrated device 204, through the substrate 402, the first interconnect structure 210, and back through the substrate 402. The electrical signal 432 travels through the first interconnect structure 210 such that it intersects (e.g., vertically and / or horizontally) with an electrical signal 422 traveling through interconnects in the first interconnect structure 210. It should be noted that other electrical signals in the package may intersect (e.g., vertically and / or horizontally) within interconnect structures (e.g., 210, 230).

[0050] Electrical signals 442 going to and from the third function 440 of the first integrated device 204 can travel through the substrate 402, the second interconnect structure 410a, and return through the substrate 402. Similarly, electrical signals 444 going to and from the third function 440 of the first integrated device 204 can travel through the substrate 402, the second interconnect structure 410a, and return through the substrate 402.

[0051] Electrical signals 452 destined for or originating from the fourth function 450 of the first integrated device 204 can travel through the substrate 402, bypassing the interconnect structure. Electrical signals 454 destined for or originating from the fourth function 450 of the first integrated device 204 can travel through the substrate 402, the third interconnect structure 410b, and return through the substrate 402. Similarly, electrical signals 456 destined for or originating from the fourth function 450 of the first integrated device 204 can travel through the substrate 402, the third interconnect structure 410b, and return through the substrate 402.

[0052] Electrical signals 462, going to and from the fifth function 460 of the first integrated device 204, can travel through the substrate 402 and the third interconnect structure 410b, and return through the substrate 402. Electrical signals 464, going to and from the fifth function 460, can travel through the substrate 402, bypassing the interconnect structure. Electrical signals 466, going to and from the fifth function 460, can travel through the substrate 402, bypassing the interconnect structure.

[0053] Figure 5 This shows another view of how electrical signals can conceptually travel through an encapsulation. Figure 5 The illustration shows a substrate 502, a first integrated device 204 coupled to the substrate 502, a second integrated device 504 coupled to the substrate 502, a first interconnect structure 510 coupled to the substrate 502, a third interconnect structure 410b coupled to the substrate 502, and a plurality of solder interconnects coupled to the substrate 502.

[0054] The second integrated device 504 can be configured to perform various functions, which are conceptually represented by a first function 570, a second function 580, and a third function 590.

[0055] like Figure 5 As shown, electrical signals 522 going to and from the first function 420 of the first integrated device 204 can travel through the substrate 402, the first interconnect structure 510, and return through the substrate 502 (to connect with...). Figure 3 (Similar to the description in the text). Electrical signals 532 going to and from the second function 430 can travel through the substrate 502, bypassing the interconnect structure.

[0056] Electrical signals 572 going to and from the first function 570 of the second integrated device 504 can be configured to travel through the substrate 402, the first interconnect structure 510, and return through the substrate 502 (to connect with...). Figure 3 (Similar methods are described in the text).

[0057] The electrical signal 574 between the first function 570 of the second integrated device 504 and the first function 420 of the first integrated device 204 can be configured to travel through the substrate 402, the first interconnect structure 510, and return through the substrate 502 (to connect with...). Figure 3 (Similar methods are described in the text).

[0058] Electrical signals 582 destined for and originating from the second integrated device 504 and its second function 580 can be configured to travel through the substrate 502, bypassing the interconnect structure. Electrical signals 592 destined for and originating from the second integrated device 504 and its third function 590 can be configured to travel through the substrate 502, bypassing the interconnect structure. It should be noted that... Figures 3 to 5 The electrical paths for the various signals shown are merely exemplary. Different implementations may provide different electrical paths for different functions of the integrated device. In some implementations, one or more functions of the integrated device may be coupled to (i) electrical paths through interconnect structures and / or (ii) electrical paths bypassing interconnect structures.

[0059] Figure 6 A package-on-package (PoP) with interconnect structures is shown. PoP601 includes package 200 and package 600. Package 600 may be a first package, and package 200 may be a second package. Package 600 is coupled to board 290 via multiple solder interconnects 680. Package 200 is coupled to package 600 such that package 200 is located above package 600, and package 600 is located between board 290 and package 200.

[0060] Package 600 is similar to package 200, but may include components different from those in package 200. Package 600 includes a substrate 602, a first integrated device 604, a second integrated device 606, a third integrated device 605, a fourth integrated device 607, an encapsulation layer 608, and a first interconnect structure 610. Substrate 602 includes at least one dielectric layer 620, a plurality of interconnects 622, a solder resist layer 624, and a solder resist layer 626.

[0061] Figure 6Various exemplary and / or conceptual paths that at least one current (e.g., at least one electrical signal, at least one power) may take in the PoP 600 are illustrated. For example, an electrical signal 640 may travel between a first integrated device 204 and a second integrated device 206 via a first interconnect structure 210. The electrical signal 640 may be configured to travel through substrate 202 (e.g., a first plurality of interconnects of substrate 202), through the first interconnect structure 210 (e.g., a plurality of interconnects of the first interconnect structure 210), and return through substrate 202 (e.g., a second plurality of interconnects of substrate 202).

[0062] In another example, electrical signal 642 may be configured to travel between first integrated device 204 and second integrated device 206 via second interconnect structure 230. Electrical signal 642 may be configured to travel through substrate 202 (e.g., a first plurality of interconnects of substrate 202), through second interconnect structure 230 (e.g., a plurality of interconnects of second interconnect structure 230), and return through substrate 202 (e.g., a second plurality of interconnects of substrate 202).

[0063] In another example, electrical signal 644 may be configured to travel between the first integrated device 204 and the solder interconnect 280 via the second interconnect structure 230. Electrical signal 644 may be configured to travel through substrate 202 (e.g., a first plurality of interconnects of substrate 202), through the second interconnect structure 230 (e.g., a plurality of interconnects of the second interconnect structure 230), and return through substrate 202 (e.g., a second plurality of interconnects of substrate 202).

[0064] In another example, electrical signal 646 may be configured to travel between second integrated device 606 and solder interconnect 680 via first interconnect structure 610. Electrical signal 646 may be configured to travel through substrate 602 (e.g., a first plurality of interconnects of substrate 602), through first interconnect structure 610 (e.g., a plurality of interconnects of first interconnect structure 610), and return through substrate 602 (e.g., a second plurality of interconnects of substrate 602).

[0065] In another example, electrical signal 648 may be configured to travel between first integrated device 604 and second integrated device 606 via first interconnect structure 610. Electrical signal 648 may be configured to travel through substrate 602 (e.g., a first plurality of interconnects of substrate 602), through first interconnect structure 610 (e.g., a plurality of interconnects of first interconnect structure 610), and return through substrate 602 (e.g., a second plurality of interconnects of substrate 602).

[0066] The paths taken by various electrical signals may be similar to... Figure 3The electrical paths described herein are similar. However, it should be noted that the paths of the electrical signals shown in this disclosure are exemplary and / or conceptual. Different embodiments may use different paths for the electrical signals. Furthermore, the electrical signals and / or electrical paths may travel through different types of interconnects (e.g., vias, traces, pads, pillars), soldered interconnects, and / or components (e.g., passive devices). Thus, for example, an electrical signal traveling between an integrated device and an interconnect structure may travel through at least one intervening component (e.g., a passive device, a capacitor) between the integrated device and the interconnect structure. The paths shown for the electrical signals may also be applied to power supplies and / or grounds.

[0067] As described above, the package may include different components and / or different numbers of components located above different portions of the substrate. Figure 7 The package 700, including its interconnect structure, is shown. Package 700 and... Figure 2 The package 200 is similar to and includes components similar to those in the package 200.

[0068] Package 700 includes a first integrated device 204, a second integrated device 206, a third integrated device 704, a first interconnect structure 710, a second interconnect structure 230, and a passive device 706.

[0069] Package 700 is coupled to board 290 via multiple pillars (e.g., copper pillars) 780. Multiple solder interconnects 760 are available for coupling the multiple pillars 780 to substrate 202. Multiple solder interconnects 770 are available for coupling the multiple pillars 780 to board 290. First integrated device 204, third integrated device 704, and first interconnect structure 710 are coupled to a first surface of substrate 202. First integrated device 204, third integrated device 704, and first interconnect structure 210 are located on the same side as the multiple pillars 780.

[0070] Package 700 includes a first interconnect structure 710. The first interconnect structure 710 may be similar to the first interconnect structure 210. Figure 7 The first interconnect structure 710 is shown to include at least one dielectric layer 711, a plurality of redistributed interconnects 712, a solder mask layer 214, and a solder mask layer 216. The plurality of redistributed interconnects 712 can be fabricated using a redistribution layer process (e.g., a non-SAP process). Figure 7 As shown, the plurality of redistributed interconnects 712 may have a shape different from that of interconnect 212. For example, at least some of the plurality of redistributed interconnects 712 may include a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The plurality of redistributed interconnects 712 may have a minimum pitch and / or similar L / S to the minimum spacing and / or line spacing (L / S) of the plurality of interconnects 212. Similarly, at least one dielectric layer 711 may comprise a material similar to that of at least one dielectric layer 211.

[0071] The first interconnect structure 710 and / or the plurality of pillars 780 may be implemented in any of the packages described in this disclosure. Following the description of various packages having interconnect structures, processes for manufacturing the interconnect structures, substrates, and packages.

[0072] Exemplary sequence for manufacturing high-density interconnect structures

[0073] Figure 8 (which includes) Figures 8A to 8D This illustrates an exemplary sequence for providing or manufacturing high-density interconnect structures. In some implementations, Figures 8A to 8D The order can be used for supplying or manufacturing. Figure 2 The first interconnect structure 210, or any of the interconnect structures described in this disclosure.

[0074] It should be noted that, Figures 8A to 8D The sequence of processes can be combined with one or more stages to simplify and / or clarify the order used to provide or manufacture the interconnect structure. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of this disclosure. Different embodiments can manufacture the interconnect structure in different ways.

[0075] like Figure 8A As shown, stage 1 illustrates the state after the carrier 800 is provided. The carrier 800 may be a substrate and / or a wafer. The carrier 800 may include glass and / or silicon. The carrier 800 may be a first carrier.

[0076] Phase 2 illustrates the state after the adhesive layer 810 is disposed (e.g., formed) over the carrier 800. The adhesive layer 810 may be an adhesive film.

[0077] Phase 3 illustrates the state after the dielectric layer 820 is applied to the adhesive layer 810. The dielectric layer 820 may comprise a polymer material. However, different embodiments may comprise different materials. The dielectric layer 820 may be a passivation layer. The dielectric layer 820 may be deposited and / or coated over the adhesive layer 810. Different embodiments may use different types of passivation layers. Passivation layers may comprise PSR, SR, PID, and / or ABF.

[0078] Stage 4 illustrates the state after a plurality of interconnects 822 have been formed over dielectric layer 820. The plurality of interconnects 822 may include traces and / or pads. Forming the plurality of interconnects 822 may include forming a seed layer, performing photolithography, electroplating, lift-off, and / or etching processes. Stage 4 may illustrate an example of forming a redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure. The plurality of interconnects 822 may be part of a plurality of interconnects 212.

[0079] Phase 5 illustrates the state after the dielectric layer 830 is formed over the multiple interconnects 822 and the dielectric layer 820. The dielectric layer 830 may be deposited and / or coated over the multiple interconnects 822 and the dielectric layer 820. The dielectric layer 830 may include a polymer. The dielectric layer 830 may be similar to the dielectric layer 820.

[0080] like Figure 8B As shown, stage 6 illustrates the state after cavity 831 is formed in dielectric layer 830. Cavity 831 can be formed using an etching process.

[0081] Stage 7 illustrates the state after a plurality of interconnects 832 have been formed over dielectric layer 830. The plurality of interconnects 832 may include vias, traces, and / or pads. Forming the plurality of interconnects 832 may include forming a seed layer, performing photolithography, electroplating, lift-off, and / or etching processes. Stage 7 may illustrate an example of forming a redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure. The plurality of interconnects 832 may be part of a plurality of interconnects 212.

[0082] Phase 8 illustrates the state after a dielectric layer 840 has been formed over the multiple interconnects 832 and the dielectric layer 830. The dielectric layer 840 may be deposited and / or coated over the multiple interconnects 832 and the dielectric layer 830. The dielectric layer 840 may include a polymer. The dielectric layer 840 may be similar to the dielectric layer 830.

[0083] Stage 9 shows the state after cavity 841 is formed in dielectric layer 840. Cavity 841 can be formed using an etching process.

[0084] Stage 10 illustrates the state after a plurality of interconnects 842 have been formed over dielectric layer 840. The plurality of interconnects 842 may include vias, traces, and / or pads. Forming the plurality of interconnects 842 may include forming a seed layer, performing photolithography, electroplating, lift-off, and / or etching processes. Stage 10 may illustrate an example of forming a redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure. The plurality of interconnects 842 may be part of a plurality of interconnects 212.

[0085] like Figure 8C As shown, stage 11 illustrates the state after a dielectric layer 850 has been formed over multiple interconnects 842 and dielectric layer 840. Dielectric layer 850 may be deposited and / or coated over the multiple interconnects 842 and dielectric layer 840. Dielectric layer 850 may include a polymer. Dielectric layer 850 may be similar to dielectric layer 840.

[0086] Stage 12 shows the state after cavity 851 is formed in dielectric layer 850. Cavity 851 can be formed using an etching process.

[0087] Stage 13 illustrates the state after a plurality of interconnects 852 have been formed over dielectric layer 850. The plurality of interconnects 852 may include vias, traces, and / or pads. Forming the plurality of interconnects 852 may include forming a seed layer, performing photolithography, electroplating, lift-off, and / or etching processes. Stage 13 may illustrate an example of forming a redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure. The plurality of interconnects 852 may be part of a plurality of interconnects 212.

[0088] Phase 14 illustrates the state after the carrier 800 and adhesive 801 are decoupled from dielectric layer 211 (e.g., removed). Dielectric layer 211 may represent dielectric layers 820, 830, 840, and / or 850. Multiple interconnects 212 may represent multiple interconnects 822, 832, 842, and / or 852.

[0089] like Figure 8D As shown, stage 15 illustrates the state after the first solder mask 214 and the second solder mask 216 are formed over the first interconnect structure 210 (e.g., a high-density interconnect structure).

[0090] Phase 16 illustrates the state after multiple welded interconnects 250 are coupled to the first interconnect structure 210. Phases 15 and 16 can demonstrate, for example... Figure 2 An example of the described first interconnect structure 210. In some embodiments, the first interconnect structure 210 is part of a wafer and can be diced to cut the wafer into individual interconnect structures. When the interconnect structure (e.g., 210) is fabricated using an SAP process or mSAP process, the thickness of each of the dielectric layers (e.g., 820, 830, 840) can be approximately 20-25 micrometers (μm), and the thickness of each of the metal layers (on which the interconnects are formed) can be approximately 15 micrometers (μm). In some embodiments, the plurality of interconnects 212 may include redistributed interconnects, which include U-shaped interconnects or V-shaped interconnects. In some embodiments, Figures 8A to 8DThe sequence can be used to fabricate a first interconnect structure 710 comprising a plurality of redistributed interconnects 712, wherein at least some of the redistributed interconnects include U-shaped interconnects or V-shaped interconnects. The terms “U-shaped” and “V-shaped” can refer to the side profile shape of the interconnects and / or redistributed interconnects. U-shaped and V-shaped interconnects may have top and bottom portions. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect). When the interconnect structure (e.g., 710) is fabricated using a redistributed layer (RDL) fabrication process, the thickness of each of the dielectric layers (e.g., 820, 830, 840) may be approximately 5-10 micrometers (μm), and the thickness of each of the metal layers (on which the redistributed interconnects are formed) may be approximately 5-10 micrometers (μm). An exemplary flowchart of a method for fabricating a high-density interconnect structure is shown.

[0091] In some implementations, manufacturing a package that includes a high-density interconnect structure involves several processes. Figure 9 An exemplary flowchart of a method 900 for providing or manufacturing high-density interconnect structures is shown. In some embodiments, Figure 9 Method 900 can be used to provide or manufacture the products described in this disclosure. Figure 2 and / or Figure 7 High-density interconnect structures (e.g., 210, 230, 710). However, method 900 can be used to provide or manufacture any of the interconnect structures described in this disclosure.

[0092] It should be noted that Figure 9 The method may combine one or more processes to simplify and / or specify the method used to provide or manufacture interconnect structures. In some implementations, the order of processes may be changed or modified. Figure 9 This will be described in terms of manufacturing redistributed interconnects. However, Figure 9 This method can be used to manufacture any type of interconnect.

[0093] The method provides a carrier (e.g., 800) at 905. The carrier may include an adhesive layer 810 disposed above the carrier. The carrier 800 may be a substrate and / or a wafer. The carrier 800 may include glass and / or silicon. The adhesive layer 810 may be an adhesive film. Figure 8A Phases 1 and 2 show examples of carriers with an adhesive layer disposed on top of the carrier.

[0094] This method forms a first redistribution layer (at 910) by forming a dielectric layer (e.g., 820) and a plurality of interconnects 822 over a carrier and an adhesive. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include depositing (e.g., depositing, coating) the dielectric layer 820 over the adhesive layer 810, forming a seed layer, performing a photolithography process, performing an electroplating process, performing a stripping process, and / or performing an etching process. Figure 8A Phases 3-4 show examples of forming a first redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure.

[0095] The method forms a second redistribution layer (at 915) by forming a dielectric layer (e.g., 830) and a plurality of interconnects 832 over a first redistribution layer. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include disposing the dielectric layer 830 over the dielectric layer 820 and the interconnects 822, forming a seed layer, performing a photolithography process, performing an electroplating process, performing a lift-off process, and / or performing an etching process. Figures 8A to 8B Phases 5-7 demonstrate examples of forming a second redistribution layer (e.g., a redistribution metal layer) for a high-density interconnect structure.

[0096] This method forms (at 920) (multiple) additional redistribution layers by forming one or more dielectric layers (e.g., 840, 850) and multiple interconnects (e.g., 842, 852) over the second redistribution layer. The dielectric layer may include a polymer. Forming the dielectric layer and multiple interconnects may include disposing one or more dielectric layers (e.g., 840, 850) over the dielectric layer 830 and the interconnects 832, forming a seed layer, performing a photolithography process, performing an electroplating process, performing a lift-off process, and / or performing an etching process. Figures 8B to 8C Phases 8-13 demonstrate examples of forming additional redistribution layers (e.g., redistribution metal layers) for high-density interconnect structures.

[0097] This method decouples the carrier (e.g., 800) and adhesive (e.g., 810) from the dielectric layer (e.g., 820) (at 925). Figure 8C Phase 14 shows an example of decoupling the carrier and adhesive from the dielectric layer.

[0098] The method forms (at 930) a first solder resist layer (e.g., 214) and a second solder resist layer (e.g., 216) over the dielectric layer of the interconnect structure (e.g., 210). Figure 8D Phase 15 shows an example of forming a solder resist layer over the dielectric layer of the interconnect structure.

[0099] This method couples multiple welded interconnects (e.g., 250) to (in 935) an interconnect structure (e.g., 210). Figure 8D Phase 16 can demonstrate an example of coupling welded interconnects to an interconnect structure.

[0100] In some embodiments, the first interconnect structure 210 is part of a wafer, and dicing can be performed to cut the wafer into individual interconnect structures. Method 900 can be used to fabricate interconnect structures including multiple interconnect structures 212 and / or multiple redistributed interconnect structures 712.

[0101] Exemplary sequence for manufacturing substrates

[0102] In some implementations, the fabrication of the substrate includes several processes. Figure 10 (including...) Figures 10A to 10C This illustrates an exemplary sequence for providing or manufacturing a substrate. In some embodiments, Figures 10A to 10C The order can be used for supplying or manufacturing. Figure 2 Substrate 202. However, the process of FIG10 can be used to manufacture any of the substrates described in this disclosure.

[0103] It should be noted that, Figures 10A to 10C The order of processes can be combined with one or more stages to simplify and / or clarify the sequence used for providing or manufacturing the substrate. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of this disclosure.

[0104] like Figure 10A As shown, stage 1 illustrates the state after a carrier 1000 is provided and a metal layer is formed over the carrier 1000. The metal layer can be patterned to form interconnects 1002. Electroplating and etching processes can be used to form the metal layer and the interconnects.

[0105] Phase 2 illustrates the state after the dielectric layer 1020 is formed over the carrier 1000 and interconnect 1002. The dielectric layer 1020 may include polyimide. However, different embodiments may use different materials for the dielectric layer.

[0106] Stage 3 shows the state after multiple cavities 1010 are formed in the dielectric layer 1020. The multiple cavities 1010 can be formed using an etching process (e.g., photolithography) or a laser process.

[0107] Stage 4 illustrates the state after interconnects 1012 are formed in and above dielectric layer 1020. For example, vias, pads, and / or traces can be formed. Electroplating processes can be used to form the interconnects.

[0108] Phase 5 illustrates the state after another dielectric layer 1022 is formed on top of dielectric layer 1020. Dielectric layer 1022 can be made of the same material as dielectric layer 1020. However, different embodiments may use different materials for the dielectric layer.

[0109] like Figure 10B As shown, stage 6 illustrates the state after multiple cavities 1030 are formed in the dielectric layer 1022. The cavities 1030 can be formed using etching or laser processes.

[0110] Stage 7 illustrates the state after interconnects 1014 are formed in and above dielectric layer 1022. For example, vias, pads, and / or traces can be formed. Electroplating processes can be used to form the interconnects.

[0111] Stage 8 illustrates the state after another dielectric layer 1024 is formed on top of dielectric layer 1022. Dielectric layer 1024 can be made of the same material as dielectric layer 1020. However, different embodiments may use different materials for the dielectric layer.

[0112] Stage 9 shows the state after multiple cavities 1040 are formed in the dielectric layer 1024. The cavities 1040 can be formed using etching or laser processes.

[0113] like Figure 10C As shown, stage 10 illustrates the state after interconnects 1016 are formed in and above dielectric layer 1024. For example, vias, pads, and / or traces can be formed. Electroplating processes can be used to form the interconnects.

[0114] Some or all of interconnects 1002, 1012, 1014 and / or 1016 may define a plurality of interconnects 222 of substrate 202. Dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 220.

[0115] Phase 11 shows the state after the carrier 1000 is decoupled from the dielectric layer 220 (e.g., removed, ground away) and leaves the substrate 202.

[0116] Phase 12 shows the state after the first solder resist layer 224 and the second solder resist layer 226 are formed on the substrate 202.

[0117] Different implementations may use different processes to form (multiple) metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form (multiple) metal layers. For example, sputtering, spraying, and / or electroplating processes may be used to form (multiple) metal layers.

[0118] Exemplary flowchart of a method for manufacturing a substrate

[0119] In some implementations, the fabrication of the substrate involves several processes. Figure 11 An exemplary flowchart of a method 1100 for providing or manufacturing a substrate is shown. In some embodiments, Figure 11 Method 1100 can be used to provide or manufacture Figure 2 The substrate. For example. Figure 11 The method can be used to manufacture substrate 202.

[0120] It should be noted that, Figure 11The method may combine one or more processes to simplify and / or define the method for providing or manufacturing a substrate. In some embodiments, the order of processes may be changed or modified.

[0121] This method provides a carrier 1000 (at 1105). Different embodiments may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Figure 10A Phase 1 shows the state after the carrier is provided.

[0122] This method involves forming a metal layer (at 1110) over a carrier 1000. This metal layer can be patterned to form interconnects. An electroplating process can be used to form the metal layer and the interconnects. Figure 10A Phase 1 shows the state after the metal layer and interconnect 1002 are formed.

[0123] The method involves forming a dielectric layer 1020 (at 1115) over a carrier 1000 and an interconnect 1002. The dielectric layer 1020 may comprise polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) within the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figure 10A Stages 2-3 show the formation of the dielectric layer and cavities within the dielectric layer.

[0124] This method forms interconnects (at 1120) in and over the dielectric layer. For example, interconnect 1012 can be formed in and over the dielectric layer 1020. Electroplating processes can be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or in the dielectric layer. Figure 10A Phase 4 shows an example of forming interconnects in and over the dielectric layer.

[0125] The method (at 1125) forms a dielectric layer 1022 over a dielectric layer 1020 and an interconnect. The dielectric layer 1022 may comprise polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) within the dielectric layer 1022. These cavities may be formed using an etching process or a laser process. Figures 10A to 10B Stages 5-6 demonstrate the formation of a dielectric layer and cavities within the dielectric layer.

[0126] This method (at 1130) forms interconnects in and / or above the dielectric layer. For example, interconnect 1014 can be formed. An electroplating process can be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer above and in the dielectric layer. Figure 10B Phase 7 shows an example of forming interconnects in and over the dielectric layer.

[0127] This method can form (multiple) additional dielectric layers and additional interconnects, as described in 1125 and 1130. Figures 10B to 10C Stages 8-10 show examples of forming interconnects in and over the dielectric layer.

[0128] Once all (or more) dielectric layers and additional interconnects are formed, the method can decouple the carrier (e.g., 1000) from dielectric layer 1020 (e.g., remove, grind away), leaving the substrate. In some embodiments, the method may form a solder resist layer (e.g., 224, 226) over the substrate.

[0129] Different implementations may use different processes to form (multiple) metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form (multiple) metal layers. For example, sputtering, spraying, and / or electroplating processes may be used to form (multiple) metal layers.

[0130] Exemplary sequence for manufacturing a package including a high-density interconnect structure coupled to a substrate.

[0131] Figure 12 (which includes) Figures 12A to 12B This illustrates an exemplary sequence for providing or manufacturing a package that includes a high-density interconnect structure coupled to a substrate. In some embodiments, Figures 12A to 12B The order can be used to provide or manufacture including Figure 2 The package 200 of the substrate 202 and the first interconnect structure 210, or any of the packages described in this disclosure.

[0132] It should be noted that, Figures 12A to 12B The order of processes can be combined with one or more stages to simplify and / or specify the sequence used for providing or manufacturing the package. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of this disclosure. Figures 12A to 12B The order can be used to manufacture one package or several packages at a time (as part of a wafer).

[0133] like Figure 12A As shown, Phase 1 illustrates the state after substrate 202 has been provided. Substrate 202 can be supplied by a vendor or manufactured by the vendor. Figures 10A to 10C The process shown is similar to that used to fabricate substrate 202. However, different embodiments may use different processes to fabricate substrate 202. Examples of processes that can be used to fabricate substrate 202 include semi-additive process (SAP) and modified semi-additive process (mSAP). Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222.

[0134] Phase 2 illustrates the state after the first integrated device 204 is coupled to a first surface (e.g., the bottom surface) of the substrate 202. The first integrated device 204 is coupled to the substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 may be coupled to interconnects of a plurality of interconnects 222 from the substrate 202. The first integrated device 204 may be coupled to the substrate 202 such that the front side (e.g., the active side) of the first integrated device 204 faces the substrate 202.

[0135] Phase 3 shows the state after the underfill 242 is provided between the substrate 202 and the first integrated device 204.

[0136] Phase 4 illustrates the state after the first interconnect structure 210 is coupled to the first surface of the substrate 202. The first interconnect structure 210 can be coupled to the substrate 202 via multiple solder interconnects.

[0137] Phase 5 illustrates the state after multiple weld interconnects 280 are coupled to the first surface of substrate 202. The multiple weld interconnects 280 can be coupled to interconnects of multiple interconnects 222 from substrate 202.

[0138] like Figure 12B As shown, stage 6 illustrates the state of the substrate 202 after it has been flipped, which has a first integrated device 204, a first interconnect structure 210 and a plurality of welded interconnects 280.

[0139] Phase 7 illustrates the state after several components are coupled to the second surface (e.g., the top surface) of the substrate 202. For example, the second integrated device 206 and the second interconnect structure 230 are coupled to the second surface of the substrate 202.

[0140] Phase 8 illustrates the state after the encapsulation layer 208 is formed above the second surface of the substrate 202, such that the encapsulation layer 208 encapsulates the second integrated device 206 and the second interconnect structure 230. The process of forming and / or setting the encapsulation layer 208 may include using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Phase 8 may illustrate a package 200, which includes the substrate 202, the first integrated device 204, the first interconnect structure 210, the second integrated device 206, the second interconnect structure 230, and the encapsulation layer 208.

[0141] The packages described in this disclosure (e.g., 200, 600, 700) can be manufactured one at a time, or they can be manufactured together as part of one or more wafers and then cut into individual packages.

[0142] Exemplary flowchart of a method for manufacturing a package including a high-density interconnect structure coupled to a substrate.

[0143] In some implementations, fabricating a package that includes a high-density interconnect structure coupled to a substrate involves several processes. Figure 13 An exemplary flowchart of a method 1300 for providing or manufacturing a package including a high-density interconnect structure coupled to a substrate is shown. In some embodiments, Figure 13 Method 1300 can be used to provide or manufacture the invention described in this disclosure. Figure 2 Package 200. However, method 1300 can be used to provide or manufacture any of the packages described in this disclosure.

[0144] It should be noted that Figure 13 The method may combine one or more processes to simplify and / or define the method for providing or manufacturing a package that includes a high-density interconnect structure coupled to a substrate. In some embodiments, the order of the processes may be changed or modified.

[0145] The method provides a substrate (e.g., 202) at 1305. Substrate 202 may be supplied by a vendor or manufactured. Substrate 202 includes a first surface and a second surface. Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Different embodiments may provide different substrates. Figures 10A to 10C The process shown is similar to that used to manufacture substrate 202. However, different embodiments may use different processes to manufacture substrate 202. Figure 12A Phase 1 shows and describes an example of providing a substrate.

[0146] This method (at 1310) couples a first integrated device (e.g., 204) and a first interconnect structure (e.g., 210) to a first surface of a substrate (e.g., 202). The first integrated device 204 can be coupled to the substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 can be coupled to interconnects of a plurality of interconnects 222 from the substrate 202. The first integrated device 204 can be coupled to the substrate 202 such that the front side (e.g., the active side) of the first integrated device 204 faces the substrate 202. As an example, the integrated device 204 and the interconnect structure 210 can be coupled to the substrate 202 such that the integrated device, the interconnect structure, and the substrate are coupled together such that when a first electrical signal travels between the integrated device and the board (e.g., 290), the first electrical signal travels through the substrate 202, then through the interconnect structure 210, and returns through the substrate 202. Figure 12A Phases 2-4 show and describe examples of integrated devices and interconnect structures coupled to a substrate. Coupling integrated devices to a substrate may also include providing an underfill (e.g., 242) between the first integrated device 204 and the substrate 202. Figure 12A Phase 3 shows and describes the bottom filler that is being provided.

[0147] This method couples multiple weld interconnects (e.g., 280) to a first surface of a substrate (e.g., 202) (at 1315). Figure 12A Phase 5 shows and describes an example of coupling welded interconnects to a substrate.

[0148] This method couples a component to a second surface of substrate 202 (at 1320). Different embodiments may couple different components and / or different numbers of components. Components may include a second integrated device 206, a second interconnect structure 230, and a passive device 706. In some embodiments, the substrate may be flipped before the component is coupled to the substrate. Figure 12B Phase 7 shows and describes the various components coupled to the second surface of the substrate.

[0149] The method involves forming (at 1325) an encapsulation layer (e.g., 208) above a second surface of a substrate (e.g., 202), such that the encapsulation layer 208 encapsulates the second integrated device 206 and the second interconnect structure 230. The process of forming and / or configuring the encapsulation layer 208 may include using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Figure 12B Phase 8 shows and describes an example of an encapsulation layer that sits above a substrate and encapsulates the integrated device.

[0150] Exemplary electronic device

[0151] Figure 14 Various electronic devices are demonstrated that can be integrated with any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, connectors, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, mobile phone device 1402, laptop computer device 1404, fixed-location terminal device 1406, wearable device 1408, or automobile 1410 may include device 1400 as described herein. Device 1400 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Figure 14The devices 1402, 1404, 1406, and 1408 shown, as well as vehicle 1410, are merely exemplary. Other electronic devices may also feature device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other device for storing or retrieving data or computer instructions, or any combination thereof.

[0152] Figures 2 to 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12B and / or Figures 13 to 14 One or more of the components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 2 to 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12B and / or Figures 13 to 14 The corresponding descriptions herein are not limited to dies and / or ICs. In some embodiments, Figures 2 to 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10C , Figure 11 , Figures 12A to 12B and / or Figures 13 to 14 The descriptions therein can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some embodiments, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a thermal device, and / or a connector.

[0153] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, these drawings may not be drawn to scale. In some cases, not all parts and / or components may be shown for clarity. In some cases, the positioning, location, size, and / or shape of various parts and / or components in the drawings may be exemplary. In some embodiments, the various parts and / or components in the drawings may be optional.

[0154] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of the disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to mean direct or indirect coupling between two objects. For example, if object A is physically in contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact with each other. The term “electrically coupled” can refer to two objects being directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. There may or may not be current traveling between two electrically coupled objects. The term “encapsulation” means that an object can partially or completely encapsulate another object. It should be further noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that the component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Therefore, for example, a first component above a second component may mean: (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on its surface), and / or (3) the first component is in the second component (e.g., embedded). The term “approximately 'value X'”, or “about value X”, as used in this disclosure, means a value that differs from “value X” by less than 10%. For example, a value of approximately 1 or about 1 would mean a value in the range of 0.9-1.1.

[0155] In some embodiments, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., a seed layer + metal layer). In some embodiments, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use similar or different processes to form interconnects. In some embodiments, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0156] Furthermore, it should be noted that the various disclosures contained herein can be described as processes, depicted as flowcharts, diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many operations can be performed in parallel or concurrently. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0157] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of various aspects of this disclosure is intended to be exemplary and not to limit the scope of the claims. Therefore, the teachings of this disclosure can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

[0158] In the following text, several non-limiting examples are given for the purpose of understanding this disclosure.

[0159] A package includes a substrate having a first surface and a second surface, wherein the substrate further includes a plurality of interconnects for providing electrical connections to a board; electronic circuitry coupled to the first surface or the second surface of the substrate or integrated into the substrate (which may include integrated devices and / or be formed in integrated devices); and an interconnect structure coupled to the first surface of the substrate, wherein the electronic circuitry, the interconnect structure, and the substrate are coupled together such that when a first electrical signal travels between the electronic circuitry and the board, the first electrical signal travels at least through the substrate, then through the interconnect structure, and returns through the substrate. The interconnect structure may provide at least one electrical path (or electrical connection) between a first electrical contact provided by the substrate and a second electrical contact provided by the substrate, wherein the first contact is electrically connected to the electronic circuitry, and wherein the second contact is electrically connected to one or more of the interconnects.

[0160] A package includes a substrate comprising a first surface and a second surface, wherein the substrate further includes a plurality of interconnects for providing electrical connections between two integrated circuits; a first electronic circuit (which may include an integrated device and / or be formed in an integrated device) coupled to the first surface or the second surface of the substrate or integrated into the substrate; a second electronic circuit (which may include an integrated device and / or be formed in an integrated device); and an interconnect structure coupled to the first surface of the substrate, wherein the electronic circuit, the interconnect structure, and the substrate are coupled together such that when a first electrical signal travels between the electronic circuit (e.g., the first integrated device) and another electronic circuit (e.g., the second integrated device), the first electrical signal travels at least through the substrate, then through the interconnect structure, and returns through the substrate. The interconnect structure may provide at least one electrical path (or electrical connection) between a first electrical contact provided by the substrate and a second electrical contact provided by the substrate, wherein the first contact is electrically connected to the electronic circuit, and wherein the second contact is electrically connected to one or more of the interconnects.

[0161] An apparatus includes a substrate comprising a first surface and a second surface, wherein the substrate further includes a plurality of interconnects for providing electrical connections to a board; electronic circuitry coupled to the first surface or the second surface of the substrate or integrated into the substrate (which may include integrated devices and / or be formed in integrated devices); and interconnect redistribution components coupled to the first surface of the substrate, wherein the electronic circuitry, the interconnect redistribution components, and the substrate are coupled together such that when a first electrical signal travels between the electronic circuitry and the board, the first electrical signal travels at least through the substrate, then through the interconnect redistribution components, and returns through the substrate. The interconnect structure may provide at least one electrical path (or electrical connection) between a first electrical contact provided by the substrate and a second electrical contact provided by the substrate, wherein the first contact is electrically connected to the electronic circuitry, and wherein the second contact is electrically connected to one or more of the interconnects.

[0162] A method for manufacturing a package includes providing a substrate including a first surface and a second surface, wherein the substrate further includes a plurality of interconnects for providing electrical connections to a board; coupling electronic circuitry to or integrating it into the first surface or the second surface of the substrate; and coupling an interconnect structure to the first surface of the substrate, wherein the electronic circuitry, the interconnect structure, and the substrate are coupled together such that when a first electrical signal travels between the electronic circuitry and the board, the first electrical signal travels at least through the substrate, then through the interconnect structure, and returns through the substrate. The interconnect structure may provide at least one electrical path (or electrical connection) between a first electrical contact provided on the substrate and a second electrical contact provided on the substrate, wherein the first contact is electrically connected to the electronic circuitry, and wherein the second contact is electrically connected to one or more of the interconnects.

Claims

1. A package, comprising: A substrate includes a plurality of first interconnects and a plurality of second interconnects, the plurality of second interconnects being located on a first surface of the substrate and configured to electrically couple the substrate to a plate or to a second substrate; Integrated devices, coupled to the substrate; as well as Interconnect structure, coupled to the substrate, The integrated device and the interconnect structure are located laterally to the plurality of second interconnects and on the first surface of the substrate. The integrated device, the interconnect structure, and the substrate provide electrical paths from the integrated device to the substrate, from the substrate to the interconnect structure, and from the interconnect structure back to the substrate for a first electrical signal for the integrated device.

2. The packaging according to claim 1, The plurality of first interconnects of the substrate include a first minimum spacing, and The interconnect structure includes a plurality of third interconnects having a second minimum spacing smaller than the first minimum spacing.

3. The package of claim 1, wherein the interconnect structure comprises at least one dielectric layer and a plurality of redistributed interconnects.

4. The package of claim 1, wherein the interconnect structure includes another substrate having a plurality of fourth interconnects.

5. The packaging according to claim 1, The integrated device is configured to perform a first function and a second function, and The first function is configured to send the first electrical signal through the electrical path, the first electrical signal traveling from the integrated device through the substrate, then through the interconnect structure, and back through the substrate.

6. The package of claim 5, wherein the second function is associated with a second electrical path for a second electrical signal, the second electrical path being from the integrated device, through the substrate, then through the interconnect structure, and back through the substrate.

7. The packaging according to claim 5, The second function is associated with a second electrical path for a second electrical signal, the second electrical path being from the integrated device, through the substrate, and... The second electrical path bypasses the interconnect structure.

8. The package of claim 1, wherein the package is coupled to the board such that the integrated device and the interconnect structure are located between the substrate and the board.

9. The package of claim 8, wherein the package is part of a stacked package (PoP).

10. The packaging according to claim 1, further comprising: A second integrated device coupled to the second surface of the substrate, and A second interconnect structure coupled to a second surface of the substrate.

11. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobiles.

12. The packaging according to claim 1, further comprising: A third integrated device coupled to the surface of the second substrate; as well as A third interconnect structure coupled to the surface of the second substrate.

13. An apparatus comprising: A substrate includes a plurality of first interconnects and a plurality of second interconnects, the plurality of second interconnects being located on a first surface of the substrate and configured to electrically couple the substrate to a plate or to a second substrate; Integrated devices, coupled to the substrate; as well as Components for interconnect redistribution are coupled to the surface of the substrate. The integrated device and the component for interconnect redistribution are located laterally to the plurality of second interconnects and on the first surface of the substrate. The integrated device, the interconnect redistribution component, and the substrate provide electrical paths from the integrated device to the substrate, from the substrate to the interconnect redistribution component, and from the interconnect redistribution component back to the substrate for a first electrical signal of the integrated device.

14. The apparatus according to claim 13, The plurality of first interconnects of the substrate include a first minimum spacing, and The components used for interconnect redistribution include a plurality of third interconnects having a second minimum spacing smaller than the first minimum spacing.

15. The apparatus of claim 13, wherein the component for interconnect redistribution comprises at least one dielectric layer and a plurality of redistribution interconnects.

16. The apparatus of claim 13, wherein the component for interconnect redistribution includes another substrate having a plurality of fourth interconnects.

17. The apparatus according to claim 13, The integrated device is configured to perform a first function and a second function, and The first function is configured to send the first electrical signal through the electrical path, the first electrical signal traveling from the integrated device through the substrate, then through the interconnect redistribution components, and returning through the substrate.

18. The apparatus of claim 17, wherein the second function is associated with a second electrical path for a second electrical signal, the second electrical path traveling from the integrated device through the substrate, then through the interconnect redistribution component, and returning through the substrate.

19. The apparatus according to claim 17, The second function is associated with a second electrical path for a second electrical signal, the second electrical path traveling from the integrated device through the substrate, and The second electrical path bypasses the component used for interconnect redistribution.

20. The apparatus of claim 13, wherein the apparatus is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobiles.

21. A method for manufacturing a package, comprising: A substrate is provided comprising a plurality of first interconnects and a plurality of second interconnects, the plurality of second interconnects being located on a first surface of the substrate and configured to electrically couple the substrate to a plate or to a second substrate; The integrated device is coupled to the substrate; as well as The interconnect structure is coupled to the substrate. The integrated device and the interconnect structure are located laterally to the plurality of second interconnects and on the first surface of the substrate. The integrated device, the interconnect structure, and the substrate provide electrical paths from the integrated device to the substrate, from the substrate to the interconnect structure, and from the interconnect structure back to the substrate for a first electrical signal for the integrated device.

22. The method according to claim 21, The plurality of first interconnects of the substrate include a first minimum spacing, and The interconnect structure includes a plurality of third interconnects having a second minimum spacing smaller than the first minimum spacing.

23. The method of claim 21, wherein the interconnect structure comprises at least one dielectric layer and a plurality of redistributed interconnects.

24. The method of claim 21, wherein the interconnect structure includes another substrate having a plurality of interconnects.

25. The method according to claim 21, The integrated device is configured to perform a first function and a second function, and The first function is configured to send a first electrical signal that travels through the integrated device, through the substrate, through the interconnect structure, and back through the substrate via the electrical path.

26. The method of claim 25, wherein the second function is associated with a second electrical path for a second electrical signal, the second electrical path traveling from the integrated device through the substrate, then through the interconnect structure, and returning through the substrate.

27. The method according to claim 25, The second function is associated with a second electrical path for a second electrical signal, the second electrical path traveling from the integrated device through the substrate, and The second electrical path bypasses the interconnect structure.

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