Leakage Current Sensing Circuit and Fluxgate Driver

Abstract

The present invention provides a leakage current sensing circuit and a fluxgate driver. The leakage current sensing circuit is suitable for a fluxgate device. The leakage current sensing circuit includes a duty cycle sensing circuit, a compensation circuit, and a control signal generating circuit. The duty cycle sensing circuit receives a pulse width modulation signal from an inverter circuit, uses a frequency signal to sample the pulse width modulation signal to sense the duty cycle of the pulse width modulation signal, and outputs a counting signal. During the self-test period, the compensation circuit adjusts the number of pulses of the counting signal according to the offset signal. The control signal generating circuit calculates the average value of the counting signal, compares the average value with a plurality of critical values ​​to generate a plurality of control signals respectively, wherein the control signal is used to indicate the leakage current state of the fluxgate device.

Description

Technical Field

[0001] The invention relates to a leakage current sensing circuit and a fluxgate driver, and in particular to a leakage current sensing circuit suitable for a fluxgate device. Background Art

[0002] In order to increase the performance and endurance of electric vehicles, multiple batteries connected in series and parallel must be used to drive the electric vehicle with high voltage. However, when the electric vehicle is driving or charging, the road, weather or vehicle conditions may cause leakage current in the electric vehicle, and the leakage current will pose a significant risk to the driver and the surrounding environment. Therefore, the demand for leakage current sensors is increasing day by day, and it has always been the direction of efforts of technicians in this field. Summary of the invention

[0003] The present invention is directed to a leakage current sensing circuit which can detect the leakage current state of a fluxgate device according to a pulse width modulation signal.

[0004] According to an embodiment of the present invention, a leakage current sensing circuit is suitable for a fluxgate device. The leakage current sensing circuit includes a duty cycle sensing circuit, a compensation circuit, and a control signal generating circuit. The duty cycle sensing circuit receives a pulse width modulation signal from an inverter circuit, uses a frequency signal to sample the pulse width modulation signal to sense the duty cycle of the pulse width modulation signal, and outputs a counting signal. The compensation circuit is coupled to the duty cycle sensing circuit, and during a self-test, the number of pulses of the counting signal is adjusted according to an offset signal. The control signal generating circuit is coupled to the compensation circuit, calculates an average value of the counting signal, and compares the average value with a plurality of critical values ​​to generate a plurality of control signals respectively, wherein the control signal is used to indicate the leakage current state of the fluxgate device.

[0005] According to an embodiment of the present invention, a fluxgate driver includes an inverter circuit and a leakage current sensing circuit. The inverter circuit is coupled to the first side of the fluxgate device and generates a pulse width modulation signal according to the induced current on the first side. The leakage current sensing circuit is coupled to the inverter circuit and receives the pulse width modulation signal to generate a plurality of control signals. The leakage current sensing circuit includes a duty cycle sensing circuit, a compensation circuit and a control signal generating circuit. The duty cycle sensing circuit senses the duty cycle of the pulse width modulation signal by sampling the pulse width modulation signal with a frequency signal and outputs a counting signal. The compensation circuit is coupled to the duty cycle sensing circuit and adjusts the number of pulses of the counting signal according to the offset signal during the self-test. The control signal generating circuit is coupled to the compensation circuit and calculates the average value of the counting signal and compares the average value with a plurality of critical values ​​to generate a plurality of control signals respectively, wherein the control signal is used to indicate the leakage current state of the fluxgate device.

[0006] According to the above, the leakage current sensing circuit proposed by the present invention can be applied to any equipment with a fluxgate device (such as an electric vehicle), and according to the pulse width modulation signal generated by the inverter circuit, the duty cycle of the pulse width modulation signal and the output count signal are calculated, and then the control signal is generated according to the average value of the count signal to indicate the leakage current state of the fluxgate device. In this way, the safety of the equipment can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 is a schematic diagram of a fluxgate driver according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a leakage current sensing circuit according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a leakage current sensing circuit according to another embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of an inverter circuit according to an embodiment of the present invention;

[0012] Figure 5 is an operation waveform diagram of an inverter circuit according to an embodiment of the present invention;

[0013] Figure 6 It is an action waveform diagram of a pulse width modulation signal according to an embodiment of the present invention;

[0014] Figure 7 FIG. 4 is an operation waveform diagram during a self-test period according to an embodiment of the present invention.

[0015] Description of Figure Numbers

[0016] 100, 200, 302: leakage current sensing circuit;

[0017] 101, 201, 301, 401: inverter circuit;

[0018] 110, 210, 400: duty cycle sensing circuit;

[0019] 120, 220: compensation circuit;

[0020] 130, 230: control signal generating circuit;

[0021] 203, 303: error signal output circuit;

[0022] 204, 304: signal format conversion circuit;

[0023] 221: offset value correction circuit;

[0024] 222: filter;

[0025] 223: Temperature compensation circuit;

[0026] 224: temperature sensor;

[0027] 231, 235: absolute value operation circuit;

[0028] 232, 234: average value filter;

[0029] 233, 236: comparison circuit;

[0030] 240: abnormal state sensor;

[0031] 241: oscillation sensing circuit;

[0032] 242: frequency sensing circuit;

[0033] 243: Overcurrent sensing circuit;

[0034] 300: fluxgate driver;

[0035] 305: voltage regulator;

[0036] 306: Oscillator;

[0037] 307: self-test current generating circuit;

[0038] 308: reference voltage generator;

[0039] 410: Chopper switch circuit;

[0040] 420: H-bridge circuit;

[0041] 430: pulse width modulation signal generator;

[0042] ALA, ALA1~ALA3: prompt signal;

[0043] AS: analog output signal;

[0044] AVG: number of cycles;

[0045] CK, CPCK: frequency signal;

[0046] CS1~CSn: control signal;

[0047] DFF: switching circuit;

[0048] DT, DT': counting signal;

[0049] DTp, DTn, DOF: pulse number;

[0050] EC1, EC2: input terminals;

[0051] FG: fluxgate device;

[0052] GND, VD5V, VDD, VREF, VRs, VOUT: voltage;

[0053] IS, IT, ITa, ITd: current;

[0054] LG, N1, N2: logic circuit;

[0055] M0~M3: transistors;

[0056] OF: offset signal;

[0057] OP: Comparator;

[0058] PH1, PH2: conductive path;

[0059] PWM: pulse width modulation signal;

[0060] PWMB: operation signal;

[0061] Rs: resistance;

[0062] SID1, SID2: side;

[0063] ST1, ST2: output terminals;

[0064] SW: switch;

[0065] t1~t4, Tp, Tn: time;

[0066] TE: ambient temperature;

[0067] TEST: self-test pulse signal;

[0068] TH1~THn: critical value. DETAILED DESCRIPTION

[0069] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0070] Please refer to Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a leakage current sensing circuit according to an embodiment of the present invention. Figure 1In the illustrated embodiment, the inverter circuit 101 can generate a pulse width modulation signal PWM according to the output signal of the fluxgate device, and the leakage current sensing circuit 100 can generate control signals CS1-CSn according to the pulse width modulation signal PWM to indicate the leakage current state of the fluxgate device. In the present embodiment, the leakage current sensing circuit 100 includes a duty cycle sensing circuit 110, a compensation circuit 120, and a control signal generating circuit 130. The duty cycle sensing circuit 110 can be coupled to the inverter circuit 101, and use the frequency signal CK to sample the pulse width modulation signal PWM to sense the duty cycle of the pulse width modulation signal PWM, and output a counting signal DT. The frequency of the frequency signal CK is greater than the frequency of the pulse width modulation signal PWM. In some embodiments, the compensation circuit 120 can be coupled to the duty cycle sensing circuit 110, and during the self-test, adjust the number of pulses of the counting signal DT according to the offset signal OF. In some embodiments, the control signal generating circuit 130 can be coupled to the compensation circuit 120 to calculate the average value of the counting signal DT adjusted by the compensation circuit 120, and can compare the average value with the critical values ​​TH1~THn respectively to generate control signals CS1~CSn to indicate the leakage current state of the fluxgate device.

[0071] In some embodiments, the inverter circuit 101 may use a bridge inverter circuit or other inverter circuits or combinations thereof. The duty cycle sensing circuit 110 may be implemented using a combination of a sampling circuit and an operation circuit. The compensation circuit 120 may be implemented using a combination of a filter, a sensor, and an operation circuit. The control signal generating circuit 130 may be implemented using a combination of an absolute value operation circuit, an average filter, and a comparison circuit.

[0072] It is worth mentioning that in this embodiment, the inverter circuit 101 can generate a pulse width modulation signal PWM represented by a periodic square wave according to the output signal of the fluxgate device. Generally speaking, when there is no leakage current in the fluxgate device, the inverter circuit 101 can output a pulse width modulation signal PWM with a duty cycle (high / low potential ratio) of 50% / 50%. In contrast, when there is a leakage current in the fluxgate device, the fluxgate device will generate a magnetic field, and the duty cycle of the pulse width modulation signal PWM output by the inverter circuit 101 will change. In some embodiments, the larger the current value of the leakage current, the larger the change value of the duty cycle of the pulse width modulation signal PWM, showing a linear relationship. In this way, the leakage current sensing circuit 100 described in the present invention can sense the duty cycle of the pulse width modulation signal PWM and generate control signals CS1~CSn to indicate the leakage current state of the fluxgate device.

[0073] Please refer to Figure 2 . Figure 2 FIG. 1 is a schematic diagram of a leakage current sensing circuit according to another embodiment of the present invention. Figure 2In the illustrated embodiment, the leakage current sensing circuit 200 can be coupled to the inverter circuit 201 and generate control signals CS1-CS3 and an adjusted count signal DT'. The control signals CS1, CS2 and CS3 are used to indicate the leakage current state and abnormal state of the fluxgate device, respectively. In some embodiments, the leakage current sensing circuit 200 can be coupled to the error signal output circuit 203 and / or the signal format conversion circuit 204 to output prompt signals ALA1-ALA3 and / or analog output signals AS according to the control signals CS1-CS3 to provide prompts, judgments or other applications. In this embodiment, the leakage current sensing circuit 200 includes a duty cycle sensing circuit 210, a compensation circuit 220, a control signal generating circuit 230 and an abnormal state sensor 240. The duty cycle sensing circuit 210 is used to receive a pulse width modulation signal PWM, and use the frequency signal CK to sample the pulse width modulation signal PWM to sense the duty cycle of the pulse width modulation signal PWM, and then output the count signal DT.

[0074] In this embodiment, the compensation circuit 220 can receive the counting signal DT and generate the counting signal DT' after adjusting the pulse number. In some embodiments, the compensation circuit 220 can include at least one of an offset correction circuit 221, a filter 222 and a temperature compensation circuit 223. In some embodiments, the offset correction circuit 221 can be coupled to the duty cycle sensing circuit 210 to receive the counting signal DT, and can adjust the pulse number of the counting signal DT according to the offset signal OF during the self-test. In some embodiments, the offset correction circuit 221 can be a dynamic offset correction (DOC) circuit. The offset signal OF can be pre-set or provided by the user input, or can be dynamically set according to the pulse width modulation signal PWM within an initial period of time after the fluxgate device is powered on (power ON).

[0075] In some embodiments, the filter 222 can be coupled to the offset correction circuit 221 to filter out noise of the count signal DT. The temperature compensation circuit 223 can be coupled to the filter 222 and receive the ambient temperature TE through a temperature sensor 224 disposed around (or inside) the leakage current sensing circuit 200, and then adjust (e.g., perform addition and subtraction operations) the number of pulses of the count signal DT according to the ambient temperature TE to generate the count signal DT'.

[0076] In this embodiment, the control signal generating circuit 230 can be coupled to the compensation circuit 220 to receive the adjusted count signal DT' and generate control signals CS1 and CS2. In some embodiments, the control signal generating circuit 230 can only include an absolute value operation circuit 231, an average value filter 232 and a comparison circuit 233. The absolute value operation circuit 231 can perform an absolute value operation on the count signal DT' to generate a non-negative first signal S1. The average value filter 232 can be coupled to the absolute value operation circuit 231 and perform a low-pass filter on the first signal S1 to obtain an average value of the first signal S1. For example, when the input signal is an alternating current (AC) signal with positive and negative values, the negative value in the AC signal can be positively converted by the absolute value operation circuit 231, and then a DC-like average value signal can be output by the average value filter 232. The comparison circuit 233 can be coupled to the average value filter 232 and generate a control signal CS1 after comparing the threshold value TH1 with the average value of the first signal S1. For example, a logic high level may be output when the input signal is greater than or equal to the threshold value TH1, and vice versa.

[0077] In some embodiments, the control signal generating circuit 230 may further include an average filter 234, an absolute value operation circuit 235, and a comparison circuit 236. The average filter 234 may perform a low-pass filter on the count signal DT' to obtain an average value of the count signal DT'. The absolute value operation circuit 235 may be coupled to the average filter 234 and take an absolute value of the average value. For example, when the input signal is a DC signal, the average value may be outputted by the average filter 234 first, and then the absolute value may be taken by the absolute value operation circuit 235. The comparison circuit 236 may be coupled to the absolute value operation circuit 235 and generate a control signal CS2 according to the critical value TH2 and the average value of the non-negative input signal. Among them, the critical values ​​TH1 and TH2 may be pre-set or provided for user input. In some embodiments, the critical value TH1 may be set to 30 mA, and the critical value TH2 may be set to 6 mA.

[0078] In some embodiments, the abnormal state sensor 240 can be coupled to the duty cycle sensing circuit 210 and / or the control signal generating circuit 230, and generate a control signal CS3. In some embodiments, the abnormal state sensor 240 can include at least one of an oscillation sensing circuit 241, a frequency sensing circuit 242, and an overcurrent sensing circuit 243, and in some embodiments, can also include a logic circuit LG. The oscillation sensing circuit 241, the frequency sensing circuit 242, and the overcurrent sensing circuit 243 can be pre-set or input by the user to determine the critical values ​​of different judgment conditions to determine the abnormal state. In this embodiment, the oscillation sensing circuit 241 can be coupled to the frequency source of the fluxgate device to sense whether the fluxgate device has an oscillation abnormality. For example, when the oscillation sensing circuit 241 senses that the frequency source has no output frequency or the frequency is lower than the default critical value, it may represent that the fluxgate device is not connected properly or the circuit is not welded properly, resulting in an abnormal state of no oscillation or stopped oscillation, and the oscillation sensing circuit 241 can generate an oscillation abnormality signal.

[0079] In some embodiments, the frequency sensing circuit 242 can be coupled to the duty cycle sensing circuit 210, and determine whether the fluxgate device has a frequency abnormality according to the counting signal DT. For example, when the frequency sensing circuit 242 determines that the output frequency of the fluxgate device is higher (or lower) than the default critical value, a frequency abnormality signal can be generated. In some embodiments, the overcurrent sensing circuit 243 can be coupled to the control signal generating circuit 230 to sense the overcurrent state of the fluxgate device. For example, the overcurrent sensing circuit 243 can be coupled to the absolute value operation circuit 231 in the control signal generating circuit 230 to receive the first signal S1 after the adjusted pulse number and the absolute value operation, and when the overcurrent sensing circuit 243 determines that the current of the first signal S1 is greater than the preset critical value, a current abnormality signal can be generated. In this embodiment, the logic circuit LG can be coupled to the output end of the oscillation sensing circuit 241, the frequency sensing circuit 242 and the overcurrent sensing circuit 243, and generate the control signal CS3 according to the oscillation abnormality signal, the frequency abnormality signal and the current abnormality signal. For example, the logic circuit LG may be replaced by an OR gate circuit, a NOR gate circuit, or other logic gate circuits or a combination thereof.

[0080] In some embodiments, the leakage current sensing circuit 200 can be coupled to the error signal output circuit 203. The error signal output circuit 203 can generate corresponding prompt signals ALA1-ALA3 according to any of the control signals CS1-CS3 to issue a warning when a leakage current or abnormal state occurs in the fluxgate device. For example, the error signal output circuit 203 can be a plurality of buffer circuits (e.g., a pull-up circuit, a pull-down circuit, or a combination thereof). The error signal output circuit 203 can further include a buzzer, a light emitting diode, or other warning circuits to generate a prompt signal in the form of sound and / or light.

[0081] In some embodiments, the leakage current sensing circuit 200 can be coupled to the signal format conversion circuit 204. The signal format conversion circuit 204 can convert the counting signal DT' adjusted by the compensation circuit 220 from a digital format to an analog format, and output an analog voltage signal AS for subsequent interpretation or application of other processing. In other embodiments, the error signal output circuit 203 and / or the signal format conversion circuit 204 can also be set in the leakage current sensing circuit 200, and this embodiment is not limited thereto.

[0082] Please refer to Figure 3 . Figure 3 FIG. 1 is a schematic diagram of a fluxgate driver according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the fluxgate device FG has two sets of coils on the first side SID1 and the second side SID2. The fluxgate driver 300 has input terminals EC1 and EC2 that can be coupled to the first side SID1 of the fluxgate device FG to receive the induced current IS on the first side SID1. In some embodiments, the fluxgate driver 300 may also have output terminals ST1 and ST2 that can be coupled to the second side SID2 of the fluxgate device FG to output the self-test current IT to the second side SID2, so that the fluxgate device FG can generate the induced current IS on the first side SID1 according to the self-test current IT on the second side SID2. In the present embodiment, the fluxgate driver 300 includes an inverter circuit 301, a leakage current sensing circuit 302, an error signal output circuit 303, a signal format conversion circuit 304, a voltage regulator 305, an oscillator 306, a self-test current generating circuit 307, and a reference voltage generator 308. Among them, Figure 3 The embodiments of the leakage current sensing circuit 302, the error signal output circuit 303, and the signal format conversion circuit 304 can refer to Figure 2 The relevant descriptions of the leakage current sensing circuit 200 , the error signal output circuit 203 , and the signal format conversion circuit 204 are not repeated here.

[0083] In this embodiment, the inverter circuit 301 can receive the induced current IS and generate a pulse width modulation signal. The leakage current sensing circuit 302 can generate multiple control signals according to the pulse width modulation signal. In some embodiments, the error signal output circuit 303 and / or the signal format conversion circuit 304 can generate a prompt signal ALA and / or an analog output signal AS according to the multiple control signals output by the leakage current sensing circuit 302, respectively, to indicate the leakage current and / or abnormal state of the fluxgate device FG. In some embodiments, the voltage regulator 305 can be used to stabilize any voltage signal in the fluxgate driver 300. For example, the voltage regulator 305 can be a low-dropout linear regulator (Low-Dropout Regulator, LDO). In some embodiments, the oscillator 306 can be used to generate a frequency signal for the leakage current sensing circuit 302 to judge the leakage current state.

[0084] In some embodiments, the self-test current generating circuit 307 can be used to generate a self-test current IT, and output it to the second end SID2 of the fluxgate device FG through the output ends ST1 and ST2 of the fluxgate driver 300. In some embodiments, the self-test current generating circuit 307 can generate a DC signal during the first self-test period, and generate an AC signal during the second self-test period. The start time, time length, implementation order or period interval of the first self-test period and the second self-test period are not limited in this embodiment. For example, a self-test can be performed during a period of time after the fluxgate device FG is powered on (or after a period of time or other arbitrary set period), and the first self-test period is performed first, and then the second self-test period is performed, and vice versa. The first self-test period and the second self-test period can be performed continuously or discontinuously. In some embodiments, the reference voltage generator 308 can be used to generate and output a reference voltage VOUT.

[0085] Please refer to Figure 4 and Figure 5 . Figure 4 FIG. 4 is a schematic diagram of an inverter circuit according to an embodiment of the present invention. Figure 5 FIG. 1 is an operation waveform diagram of an inverter circuit according to an embodiment of the present invention. Figure 4In the illustrated embodiment, the inverter circuit 401 can receive the output signal on the first side SID1 of the fluxgate device FG through the input terminals EC1 and EC2, and generate a pulse width modulation signal PWM to the duty cycle sensing circuit 400. In the present embodiment, the inverter circuit 401 includes a chopper switch circuit 410, an H-bridge circuit 420, and a pulse width modulation signal generator 430. The chopper switch circuit 410 can be coupled between the fluxgate device FG and the H-bridge circuit 420 to switch the polarity of the input signal. The H-bridge circuit 420 can use a plurality of switch circuits and a pulse width modulation signal PWM to switch different conductive paths PH1 and PH2 to generate a ramp signal VRs according to the output signal of the fluxgate device FG. The pulse width modulation signal generating circuit 430 can be coupled to the H-bridge circuit 420, and generate a pulse width modulation signal PWM according to the ramp signal VRs. In detail, the H-bridge circuit 420 includes transistors M0-M3, a resistor Rs and a switch SW, and has a power supply terminal, a ground terminal and a load terminal to receive the operating power supply VDD, the ground power supply GND and the output ramp signal VRs respectively. The actual number of components of the transistors M0-M3, the resistor Rs and the switch SW is not used to limit the present embodiment. In some embodiments, the resistor Rs is coupled between the load terminal and the ground terminal of the H-bridge circuit 420. In some embodiments, a switch SW may be provided between the resistor Rs and the ground terminal of the H-bridge circuit 420 to adjust the sensitivity of the sensing leakage current. In the present embodiment, the first terminals of the transistors M0 and M1 are commonly coupled to the power supply terminal. The second terminals of the transistors M0 and M1 are respectively coupled to the two output terminals of the chopper switch circuit 410. The first terminal of the transistor M2 is coupled to the second terminal of the transistor M0. The first terminal of the transistor M3 is coupled to the second terminal of the transistor M1. The second terminals of the transistors M2 and M3 are commonly coupled to the load terminal. The control terminals of the transistors M0 and M2 commonly receive the pulse width modulation signal PWM. The control terminals of the transistors M1 and M3 receive the operation signal PWMB together. In this embodiment, the conductive type of the transistors M0 and M1 is P-type, and the conductive type of the transistors M2 and M3 is N-type, so that the conduction state of the transistors M0 and M3 is opposite to the conduction state of the transistors M1 and M2. Other combinations can also be used in other embodiments, and this embodiment is not limited thereto.

[0086] In this embodiment, the pulse width modulation signal generator 430 may include a comparator OP, a switching circuit DFF, and inverters N1 and N2. The comparator OP, the switching circuit DFF, the inverters N1 and N2 may be sequentially coupled to the output end of the H-bridge circuit 420 and receive the ramp signal VRs and the reference voltage signal VREF. In this embodiment, the comparator OP may compare the voltage difference between the ramp signal VRs and the reference voltage signal VREF. The reference voltage signal VREF may be pre-set or provided as a user input. In this embodiment, the switching circuit DFF may generate an output signal according to the output of the comparator OP. The inverters N1 and N2 may perform one-time and two-time inversion processing on the output signal of the switching circuit DFF, respectively, to output an operation signal PWMB and a pulse width modulation signal PWM with opposite logic levels. In this way, the H-bridge circuit 420 may switch the switch states of the transistors M0 to M3 in turn according to the operation signal PWMB and the pulse width modulation signal PWM, so as to switch the conductive paths PH1 and PH2 of the H-bridge circuit 420. For example, in the present embodiment, when the pulse width modulation signal PWM is at a logic low level and the operation signal PWMB is at a logic high level, the transistors M0 and M3 are turned on (the transistors M1 and M2 are turned off), and a conductive path PH1 can be formed between the power supply terminal, the transistors M0 and M3, and the load terminal of the H-bridge circuit 420. Conversely, when the pulse width modulation signal PWM is at a logic high level and the operation signal PWMB is at a logic low level, the transistors M1 and M2 are turned on (the transistors M0 and M3 are turned off), and a conductive path PH2 can be formed between the power supply terminal, the transistors M1 and M2, and the load terminal of the H-bridge circuit 420.

[0087] For the waveform diagram of the above action, please refer to Figure 5 For the convenience of explanation, it is assumed that the initial output of the switching circuit DFF is a logic low level, the pulse width modulation signal PWM is a logic low level and the operation signal PWMB is a logic high level. The output signal of the fluxgate device FG can first charge the load end of the H-bridge circuit 420 through the conductive path PH1, so that the voltage value of the ramp signal VRs on the load end gradually increases from the initial low voltage value (for example, a voltage value greater than the ground power supply GND and less than the reference voltage signal VREF, which is not limited in this embodiment). When the voltage value of the ramp signal VRs is equal to the voltage value of the reference voltage signal VREF, the switching circuit DFF can change the output signal from a logic low level to a logic high level according to the change of the output of the comparator OP, then the logic levels of the operation signal PWMB and the pulse width modulation signal PWM will be reversed, and the ramp signal VRs will change from a charging state to a discharging state. At this time, the conductive path of the H-bridge circuit 420 will change from the conductive path PH1 to the conductive path PH2, and generate a reverse current to charge the load end of the H-bridge circuit 420 again. In this way, a repetitive ramp signal VRs is formed.

[0088] In this embodiment, the chopper switch circuit 410 can switch the polarity of the output signal of the fluxgate device FG (as shown by the frequency signal CPCK) after the pulse width modulation signal PWM outputs a complete cycle (i.e., the logic level switches twice). The duty cycle sensing circuit 400 can use the frequency signal CK to sample the pulse width modulation signal PWM to calculate the number of pulses of the pulse width modulation signal PWM. Assume that the sampling results under different duty cycle periods Tp and Tn are pulse numbers DTp+DOF and -DTn+DOF, respectively. The pulse width modulation signals PWM corresponding to the pulse numbers DTp and -DTn are in opposite phases to each other, and the offset number DOF represents the pulse number offset caused by the circuit noise (e.g., temperature drift) of the inverter circuit 401 and is in phase. In this way, the duty cycle sensing circuit 400 can subtract the pulse numbers of the pulse width modulation signal PWM under different duty cycles Tp and Tn ((DTp+Doffset)-(-DTn+Doffset)=DTp+DTn) to eliminate the pulse offset number DOF caused by circuit noise and calculate the duty cycle pulse numbers DTp and DTn.

[0089] Please refer to Figure 6 . Figure 6 FIG. 1 is an operation waveform diagram of a pulse width modulation signal according to an embodiment of the present invention. Figure 6 In the embodiment shown, after the fluxgate device is powered on, the voltage value VD5A at the voltage end thereof will gradually rise. Assume that there is no leakage current output when the device is just powered on, and after a period of time after the device is powered on, the inverter circuit starts to output the pulse width modulation signal PWM. Then the leakage current sensing circuit described in the present invention can measure the number of cycles AVG and the average number of pulses of the pulse width modulation signal PWM to generate the offset signal OF. For example, in the present embodiment, taking the self-test pulse signal TEST as an example, the self-test period begins, and the leakage current sensing circuit can measure the number of cycles AVG of the pulse width modulation signal PWM in an initial period before the self-test period as 16 times, and calculate the average number of pulses as 10, then the leakage current sensing circuit can set the offset signal OF to 10. In some embodiments, the leakage current sensing circuit can adjust the number of pulses of the counting signal according to the offset signal OF during the self-test period, and reset the offset signal OF to zero after the self-test period ends.

[0090] Figure 7 FIG. 1 is a schematic diagram of an action waveform during a self-test of an embodiment of the present invention. Figure 7In the embodiment shown, after the self-test pulse signal TEST starts to enter the self-test period, the self-test current generating circuit can generate a self-test current IT to the fluxgate device for leakage current detection. For example, a DC signal ITd can be generated during the self-test period t1, and an AC signal ITa can be generated during the self-test period t2. Then, during the self-test period (t1+t2), if the fluxgate device generates leakage current, the leakage current sensing circuit can output control signals CS1 and CS2. For example, in this embodiment, a pull-up (or pull-down) signal can be output after time intervals t3 and t4, respectively, to indicate the leakage current state of the fluxgate device.

[0091] According to the above, the leakage current sensing circuit and fluxgate driver proposed by the present invention can receive the pulse width modulation signal generated by the inverter circuit according to the output signal of the fluxgate device, sense the duty cycle of the pulse width modulation signal to generate multiple control signals to indicate the leakage current state of the fluxgate device. In this way, the safety of the device can be increased.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A leakage current sensing circuit, suitable for a fluxgate device, characterized in that: The leakage current sensing circuit comprises: A duty cycle sensing circuit receives a pulse width modulation signal from an inverter circuit, samples the pulse width modulation signal using a frequency signal to sense the duty cycle of the pulse width modulation signal, and outputs a counting signal; a compensation circuit coupled to the duty cycle sensing circuit, for adjusting the number of pulses of the counting signal according to an offset signal during a self-test period; and A control signal generating circuit is coupled to the compensation circuit, and calculates an average value of the counting signal according to the pulse number of the adjusted counting signal, and compares the average value with a plurality of critical values ​​to generate a plurality of control signals respectively. The plurality of control signals are used to indicate leakage current states of the fluxgate device.

2. The leakage current sensing circuit according to claim 1, characterized in that: The compensation circuit comprises: an offset value correction circuit coupled to the duty cycle sensing circuit, generating the offset signal according to the average pulse number of the pulse width modulation signal during an initial period, and adjusting the pulse number of the counting signal according to the offset signal during the self-test period; and The filter is coupled to the offset value correction circuit and is used to filter out noise of the counting signal.

3. The leakage current sensing circuit according to claim 2, characterized in that: The compensation circuit further comprises: The temperature compensation circuit is coupled to the filter, receives the ambient temperature through a temperature sensor, and adjusts the pulse number of the counting signal according to the ambient temperature.

4. The leakage current sensing circuit according to claim 1, characterized in that: The control signal generating circuit comprises: A first absolute value operation circuit, coupled to the compensation circuit; A first average value filter, coupled to the first absolute value operation circuit; and The first comparison circuit is coupled to the first average value filter and generates a first control signal according to a first critical value.

5. The leakage current sensing circuit according to claim 4, characterized in that: The control signal generating circuit further comprises: A second averaging filter coupled to the compensation circuit; A second absolute value operation circuit, coupled to the second average value filter; and The second comparison circuit is coupled to the second absolute value operation circuit and generates a second control signal according to a second threshold value.

6. The leakage current sensing circuit according to claim 1, characterized in that: The leakage current sensing circuit further comprises: an abnormal state sensor, coupled to the duty cycle sensing circuit, the abnormal state sensor comprising: An oscillation sensing circuit, sensing whether an abnormality occurs in the frequency source to generate an oscillation abnormality signal; A frequency sensing circuit, for determining whether an abnormality occurs according to the counting signal to generate a frequency abnormality signal; an overcurrent sensing circuit, sensing an overcurrent state of the fluxgate device to generate a current abnormality signal; and The logic circuit is coupled to the oscillation sensing circuit, the frequency sensing circuit and the over-current sensing circuit, and generates a first control signal according to the abnormal oscillation signal, the abnormal frequency signal and the abnormal current signal.

7. A fluxgate driver, characterized in that: The fluxgate driver comprises: an inverter circuit coupled to the first side of the fluxgate device, generating a pulse width modulation signal according to the induced current on the first side; and A leakage current sensing circuit is coupled to the inverter circuit and receives the pulse width modulation signal to generate a plurality of control signals, wherein the leakage current sensing circuit comprises: A duty cycle sensing circuit, which utilizes a frequency signal to sample the pulse width modulation signal to sense the duty cycle of the pulse width modulation signal and outputs a counting signal; a compensation circuit coupled to the duty cycle sensing circuit, for adjusting the number of pulses of the counting signal according to an offset signal during a self-test period; and The control signal generating circuit is coupled to the compensation circuit, and calculates the average value of the counting signal according to the pulse number of the adjusted counting signal, and compares the average value with multiple critical values ​​to generate the multiple control signals respectively, wherein the multiple control signals are used to indicate the leakage current state of the fluxgate device.

8. The fluxgate driver according to claim 7, characterized in that: The inverter circuit comprises: a chopper switch circuit coupled to the first side of the fluxgate device for switching the phase of the induced current; An H-bridge circuit having a power supply terminal receiving an operating power supply and a load terminal coupled to a resistor, wherein the H-bridge circuit generates a ramp signal according to the induced current based on the pulse width modulation signal; and The PWM signal generator generates the PWM signal according to the ramp signal.

9. The fluxgate driver according to claim 8, characterized in that: The H-bridge circuit comprises: A first transistor and a second transistor, wherein first terminals of the first transistor and the second transistor receive the operating power supply together; A third transistor, a first terminal of which and a second terminal of the first transistor are commonly coupled to a first terminal of the chopper switch circuit, and control terminals of the first transistor and the third transistor commonly receive the PWM signal; and a fourth transistor, a first terminal of which and a second terminal of the second transistor are commonly coupled to the second terminal of the chopper switch circuit, a control terminal of the second transistor and the fourth transistor commonly receive an operation signal, and a second terminal of the third transistor and the fourth transistor are commonly coupled to the load terminal, The resistor is coupled between the second terminal of the fourth transistor and a ground terminal.

10. The fluxgate driver according to claim 8, characterized in that: The pulse width modulation signal generator comprises: A comparator, a first terminal of which receives the ramp signal, and a second terminal of which receives a reference voltage signal; a switching circuit coupled to the comparator; A first inverter coupled to the switching circuit; and The second inverter is coupled to the first inverter.

11. The fluxgate driver according to claim 7, characterized in that: The fluxgate driver further comprises: The self-test current generating circuit is coupled to the second side of the fluxgate device and is used to generate a self-test current so that the fluxgate device generates the induced current on the second side according to the self-test current.

12. The fluxgate driver according to claim 11, characterized in that: The self-test current generating circuit may generate a direct current signal during a first self-test period and generate an alternating current signal during a second self-test period.

13. The fluxgate driver according to claim 7, characterized in that: The fluxgate driver further comprises: The error signal output circuit is coupled to the leakage current sensing circuit and generates a plurality of prompt signals according to the plurality of control signals.

14. The fluxgate driver according to claim 7, characterized in that: The fluxgate driver further comprises: The signal format conversion circuit is coupled to the leakage current sensing circuit and converts the counting signal from a digital format to an analog format.

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